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export SystemVerilog modules to multiple files? #68
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No, only one SV file is generated. From my expirience working with one file is more convinient, specially for designs with hundreds of mudules. There is also a problem with template modules and modules with constructor parameters -- that lead to different SV modules generated. |
I do understand that handling one file is more convinient if you are generating SystemVerilog for a large set of modules. I had the experience, that I had to track issues in the generated SystemVerilog modules. For tracing and verificating the behaviour I prefer having several files for several modules. Sometimes I got lost in the file with hundreds to thousands of lines.. So it's actually a personal preference. My suggestion would be to use a flag that indexes if you want to have multiple files. |
Do you think it is possible to write a script to split one SV file into multiple files by keywords module/endmodule? |
I am using a short script doing this as a workaround. And I have no problem if you create a low priority ticket for this. |
Sounds good. Will update you when it is completed. |
Is there a way for ICSC not to write all SystemVerilog modules to one file?
I think sometimes it would be more convenient to split the modules into several files to make them easier to read.
What do you think?
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