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draft
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add rd, rs, rt
add $3, $1, $2
Instruction, in binary:
0 $1 $2 $3 0 0x20
000000 00001 00010 00011 00000 100000 = 0x221820
31_26 25_21 20_16 15_11
In the add instruction, Control has to make:
RegDst = 1 (so that $3 is selected as the WriteRegister)
Branch = 0 (no branch in add operation)
MemRead = 0 (not going to read from memory)
MemtoReg = 0 (not going to write memory data into a register)
MemWrite = 0 (not writing in memory)
ALUSrc = 0 (will use value from ReadData2, not from SignExtendOut)
RegWrite = 1 (need to write the result of the operation in $3)
whb = ?
ALUOp = 110 (convention: means it will not be used)
0110000001000001 = 0x6041
----------
sub $3, $1, $2
Instruction:
0 $1 $2 $3 0 0x22
000000 00001 00010 00011 00000 100010 = 0x221822
31_26 25_21 20_16 15_11
RegDst = 1
RegWrite = 1
ALUOp = 110
0110000001000001 = 0x6041
---------------
addi $3, $1, 100
Instruction:
8 $1 $3 100
001000 00001 00011 0000000001100100 = 0x20230064
31_26 25_21 20_16 15_0
RegDest = 0 (in addi, the result is written in 20_16)
ALUSrc = 1
RegWrite = 1
ALUOp = 000 (add)
1100000 = 0x60
-----------------
lw $3, 100($2)
Loads a word from mem[$2 + 100] to $3.
Instruction:
0x23 $2 $3 100
100011 00010 00011 0000000001100100 = 0x8C430064
31_26 25_21 20_16 15_0
RegDst = 0
Branch = 0
MemRead = 1
MemtoReg = 1
MemWrite = 0
ALUSrc = 1
RegWrite = 1
whb = 00 (convention: 00 -> w, 01 -> h, 10 -> b)
ALUOp = 000 (will add offset to $2)
0000000001101100 = 0X6C
When the instruction is loaded, memory needs another clock cycle to read Address and output the value to ReadData.
But, if we do another clock cycle, we go to a new instruction, which changes Address. So this isn't working properly. Temporary fix: add a real clock to memory and leave manual clock to PC and Registers. All memory data transfer functions will have this problem.
---
sw $3, 100($2)
Write word from register $3 to mem[$2 + 100].
Instruction:
0x2b $2 $3 100
101011 00010 00011 0000000001100100 = 0xAC430064
31_26 25_21 20_16 15_0
RegDst = 0
Branch = 0
MemRead = 0
MemtoReg = 0
MemWrite = 1
ALUSrc = 1
RegWrite = 0
whb = 00
ALUOp = 000
0000 000 00 0110000 = 0x30
---
lhu $3, 100($2)
Halfword memory to register.
Instruction:
0x25 $2 $3 100
100101 00010 00011 0000000001100100 = 0x94430064
RegDst = 0
Branch = 0
MemRead = 1
MemtoReg = 1
MemWrite = 0
ALUSrc = 1
RegWrite = 1
whb = 01
ALUOp = 000
0000 000 01 1101100 = 0xEC
---
sh $3, 100($2)
Halfword register $3 to mem[$2 + 100].
Instruction:
0x29 $2 $3 100
101001 00010 00011 0000000001100100 = 0xA4430064
RegDst = 0
Branch = 0
MemRead = 0
MemWrite = 1
ALUSrc = 1
RegWrite = 0
whb = 01
ALUOp = 000
0000 000 01 0110000 = 0xB0
---
lbu $3, 100($2)
Byte from memory to register. $3 = mem[$2 + 100]
Instruction:
0x24 $2 $3 100
100100 00010 00011 0000000001100100 = 0x90430064
RegDst = 0
Branch = 0
MemRead = 1
MemtoReg = 1
MemWrite = 0
ALUSrc = 1
RegWrite = 1
whb = 10
ALUOp = 000
0000 000 10 1101100 = 0x16C
---
sb $3, 100($2)
Memory[$2 + 100] = $3. Byte from register to memory.
Instruction:
0x28 $2 $3 100
101000 00010 00011 0000000001100100 = 0xA0430064
RegDst = 0
Branch = 0
MemRead = 0
MemWrite = 1
ALUSrc = 1
RegWrite = 0
whb = 10
ALUOp = 000
0000 000 10 0110000 = 0x130
---
lui $3, 100
$3 = 100 * 2^16. Loads constant in upper 16 bits.
Instruction:
0xf 0 $3 100
001111 00000 00011 0000000001100100 = 0x3C030064
31_26 25_21 20_16
RegDst = 0
Branch = 0
MemRead = 0
MemtoReg = 0
MemWrite = 0
ALUSrc = 1
RegWrite = 1
whb = 00
ALUOp = 000
0000 000 00 1100000 = 0x60
This is just making $3 = 100, I don't know how to make 100 * 2^16.
---
and $3, $1, $2
0 $1 $2 $3 0 0x24
000000 00001 00010 00011 00000 100100 = 0x221824
31_26 25_21 20_16 15_11
RegWrite = 1
RegDst = 1
ALUOp = 110
Rest all 0
0x6041 on ROM, same position as add and sub.
---
or $3, $1, $2
0 $1 $2 $3 0 0x25
000000 00001 00010 00011 00000 100101 = 0x221825
RegWrite = 1
RegDst = 1
ALUOp = 110
Rest all 0
0x6041
---
nor $3, $1, $2
0 $1 $2 $3 0 0x27
000000 00001 00010 00011 00000 100111 = 0x221827
RegWrite = 1
RegDst = 1
ALUOp = 110
Rest all 0
0x6041
---
andi $3, $2, 100
$3 = $2 & 100
0xc $2 $3 100
001100 00010 00011 0000000001100100 = 0x30430064
RegDst = 0
Branch = 0
MemRead = 0
MemtoReg = 0
MemWrite = 0
ALUSrc = 1
RegWrite = 1
whb = 00
ALUOp = 100
0100 000 00 1100000 = 0x4060
---
ori $3, $2, 100
$3 = $2 | 100
0xd $2 $3 100
001101 00010 00011 0000000001100100 = 0x34430064
0101 000 00 1100000 = 0x5060
---
beq $1, $2, 25
if $1 == $2 go to PC + 4 + 100
4 $1 $2 25
000100 00001 00010 0000000000011001 = 0x10220019
RegDst = x
Branch = 1
MemRead = x
MemtoReg = x
MemWrite = x
ALUSrc = 0
RegWrite = 0
whb = 0
ALUOp = 010 (subtract $2 from $1)
beq/bne = 0
0010 000000000010 = 0x2002
----
bne $1, $2, 25
if $1 != $2 go to PC + 4 + 100
5 $1 $2 25
000101 00001 00010 0000000000011001 = 0x14220019
RegDst = 0
Branch = 1
MemRead = 0
MemtoReg = 0
MemWrite = 0
ALUSrc = 0
RegWrite = 0
whb = 00
j = 0
ALUOp = 010
beq/bne = 1
1010 000000000010 = 0xa002
----
j 0
2 0
000010 00000000000000000000000000 = 0x08000000
0110 1 00000000000 = 0x6800
----
jal 0
3
000011 00000000000000000000000000 = 0x0C000000
RegDst = 11
Branch = 0
MemRead = 0
MemtoReg = 11
MemWrite = 0
ALUSrc = 0
RegWrite = 1
whb = 00
j = 1
ALUOp = 110
beq = 0
0110 1 1 1 00 1 0 0 1 0 0 1 = 0x6E49
---
jr $0
0 $0 0
000000 00000 000000000000000 = 0x0