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gtx.py
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gtx.py
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# Based on LiteSATA by Enjoy-Digital
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from gtx_init import GTXInit, BruteforceClockAligner
from line_coding import Encoder, Decoder
class GTXTransmitter(Module):
def __init__(self, clock_pads, tx_pads, sys_clk_freq):
refclk_div2 = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=clock_pads.p,
i_IB=clock_pads.n,
o_ODIV2=refclk_div2
)
self.submodules.gtx_init = GTXInit(sys_clk_freq, False)
txoutclk = Signal()
txdata = Signal(20)
self.specials += \
Instance("GTXE2_CHANNEL",
# PMA Attributes
p_PMA_RSV=0x00018480,
p_PMA_RSV2=0x2050,
p_PMA_RSV3=0,
p_PMA_RSV4=0,
p_RX_BIAS_CFG=0b100,
p_RX_CM_TRIM=0b010,
p_RX_OS_CFG=0b10000000,
p_RX_CLK25_DIV=5,
p_TX_CLK25_DIV=5,
# Power-Down Attributes
p_PD_TRANS_TIME_FROM_P2=0x3c,
p_PD_TRANS_TIME_NONE_P2=0x3c,
p_PD_TRANS_TIME_TO_P2=0x64,
# CPLL
p_CPLL_CFG=0xBC07DC,
p_CPLL_FBDIV=4,
p_CPLL_FBDIV_45=5,
p_CPLL_REFCLK_DIV=1,
p_RXOUT_DIV=2,
p_TXOUT_DIV=2,
o_CPLLLOCK=self.gtx_init.cplllock,
i_CPLLLOCKEN=1,
i_CPLLREFCLKSEL=0b001,
i_TSTIN=2**20-1,
i_GTREFCLK0=refclk_div2,
# TX clock
p_TXBUF_EN="FALSE",
p_TX_XCLK_SEL="TXUSR",
o_TXOUTCLK=txoutclk,
i_TXSYSCLKSEL=0b00,
i_TXOUTCLKSEL=0b11,
# disable RX
i_RXPD=0b11,
# Startup/Reset
i_GTTXRESET=self.gtx_init.gtXxreset,
o_TXRESETDONE=self.gtx_init.Xxresetdone,
i_TXDLYSRESET=self.gtx_init.Xxdlysreset,
o_TXDLYSRESETDONE=self.gtx_init.Xxdlysresetdone,
o_TXPHALIGNDONE=self.gtx_init.Xxphaligndone,
i_TXUSERRDY=self.gtx_init.Xxuserrdy,
# TX data
p_TX_DATA_WIDTH=20,
p_TX_INT_DATAWIDTH=0,
i_TXCHARDISPMODE=Cat(txdata[9], txdata[19]),
i_TXCHARDISPVAL=Cat(txdata[8], txdata[18]),
i_TXDATA=Cat(txdata[:8], txdata[10:18]),
i_TXUSRCLK=ClockSignal("tx"),
i_TXUSRCLK2=ClockSignal("tx"),
# TX electrical
i_TXBUFDIFFCTRL=0b100,
i_TXDIFFCTRL=0b1000,
# Pads
o_GTXTXP=tx_pads.p,
o_GTXTXN=tx_pads.n,
)
self.clock_domains.cd_tx = ClockDomain()
self.specials += Instance("BUFG",
i_I=txoutclk, o_O=self.cd_tx.clk)
self.specials += AsyncResetSynchronizer(
self.cd_tx, ~self.gtx_init.done)
self.submodules.encoder = ClockDomainsRenamer("tx")(Encoder(2, True))
self.comb += txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1]))
class GTXReceiver(Module):
def __init__(self, clock_pads, rx_pads, sys_clk_freq):
refclk_div2 = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=clock_pads.p,
i_IB=clock_pads.n,
o_ODIV2=refclk_div2
)
self.submodules.gtx_init = GTXInit(sys_clk_freq, True)
rxoutclk = Signal()
rxdata = Signal(20)
self.specials += \
Instance("GTXE2_CHANNEL",
# PMA Attributes
p_PMA_RSV=0x00018480,
p_PMA_RSV2=0x2050,
p_PMA_RSV3=0,
p_PMA_RSV4=0,
p_RX_BIAS_CFG=0b100,
p_RX_CM_TRIM=0b010,
p_RX_OS_CFG=0b10000000,
p_RX_CLK25_DIV=5,
p_TX_CLK25_DIV=5,
# Power-Down Attributes
p_PD_TRANS_TIME_FROM_P2=0x3c,
p_PD_TRANS_TIME_NONE_P2=0x3c,
p_PD_TRANS_TIME_TO_P2=0x64,
# CPLL
p_CPLL_CFG=0xBC07DC,
p_CPLL_FBDIV=4,
p_CPLL_FBDIV_45=5,
p_CPLL_REFCLK_DIV=1,
p_RXOUT_DIV=2,
p_TXOUT_DIV=2,
o_CPLLLOCK=self.gtx_init.cplllock,
i_CPLLLOCKEN=1,
i_CPLLREFCLKSEL=0b001,
i_TSTIN=2**20-1,
i_GTREFCLK0=refclk_div2,
# Startup/Reset
i_GTRXRESET=self.gtx_init.gtXxreset,
o_RXRESETDONE=self.gtx_init.Xxresetdone,
i_RXDLYSRESET=self.gtx_init.Xxdlysreset,
o_RXDLYSRESETDONE=self.gtx_init.Xxdlysresetdone,
o_RXPHALIGNDONE=self.gtx_init.Xxphaligndone,
i_RXUSERRDY=self.gtx_init.Xxuserrdy,
# RX AFE
p_RX_DFE_XYD_CFG=0,
i_RXDFEXYDEN=1,
i_RXDFEXYDHOLD=0,
i_RXDFEXYDOVRDEN=0,
i_RXLPMEN=0,
# RX clock
p_RXBUF_EN="FALSE",
p_RX_XCLK_SEL="RXUSR",
i_RXDDIEN=1,
i_RXSYSCLKSEL=0b00,
i_RXOUTCLKSEL=0b010,
o_RXOUTCLK=rxoutclk,
i_RXUSRCLK=ClockSignal("rx"),
i_RXUSRCLK2=ClockSignal("rx"),
p_RXCDR_CFG=0x03000023FF10100020,
# RX Clock Correction Attributes
p_CLK_CORRECT_USE="FALSE",
p_CLK_COR_SEQ_1_1=0b0100000000,
p_CLK_COR_SEQ_2_1=0b0100000000,
p_CLK_COR_SEQ_1_ENABLE=0b1111,
p_CLK_COR_SEQ_2_ENABLE=0b1111,
# RX data
p_RX_DATA_WIDTH=20,
p_RX_INT_DATAWIDTH=0,
o_RXDISPERR=Cat(rxdata[9], rxdata[19]),
o_RXCHARISK=Cat(rxdata[8], rxdata[18]),
o_RXDATA=Cat(rxdata[:8], rxdata[10:18]),
# disable TX
i_TXPD=0b11,
# Pads
i_GTXRXP=rx_pads.p,
i_GTXRXN=rx_pads.n,
)
self.clock_domains.cd_rx = ClockDomain()
self.specials += Instance("BUFG",
i_I=rxoutclk, o_O=self.cd_rx.clk)
self.submodules.clock_aligner = BruteforceClockAligner(
0b0101111100, sys_clk_freq)
self.comb += [
self.clock_aligner.rxdata.eq(rxdata),
self.gtx_init.restart.eq(self.clock_aligner.restart)
]
self.decoders = [ClockDomainsRenamer("rx")(Decoder(True)) for _ in range(2)]
self.submodules += self.decoders
self.comb += [
self.decoders[0].input.eq(rxdata[:10]),
self.decoders[1].input.eq(rxdata[10:]),
]