diff --git a/esp32c6/src/lib.rs b/esp32c6/src/lib.rs index 1bd5689676..d07e4c4a72 100644 --- a/esp32c6/src/lib.rs +++ b/esp32c6/src/lib.rs @@ -737,7 +737,7 @@ pub struct GPIO_SD { unsafe impl Send for GPIO_SD {} impl GPIO_SD { #[doc = r"Pointer to the register block"] - pub const PTR: *const gpio_sd::RegisterBlock = 0x6000_4f00 as *const _; + pub const PTR: *const gpio_sd::RegisterBlock = 0x6009_1f00 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const gpio_sd::RegisterBlock { diff --git a/esp32c6/svd/patches/esp32c6.yaml b/esp32c6/svd/patches/esp32c6.yaml index 8aebac04e3..3b26c4f43a 100644 --- a/esp32c6/svd/patches/esp32c6.yaml +++ b/esp32c6/svd/patches/esp32c6.yaml @@ -1,5 +1,8 @@ _svd: "../esp32c6.base.svd" +_modify: + GPIO_SD: + baseAddress: 0x60091f00 USB_DEVICE: _modify: diff --git a/esp32h2/src/gpio_sd.rs b/esp32h2/src/gpio_sd.rs new file mode 100644 index 0000000000..d95045a440 --- /dev/null +++ b/esp32h2/src/gpio_sd.rs @@ -0,0 +1,124 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + #[doc = "0x00..0x10 - Duty Cycle Configure Register of SDM%s"] + pub sigmadelta: [SIGMADELTA; 4], + _reserved1: [u8; 0x10], + #[doc = "0x20 - Clock Gating Configure Register"] + pub clock_gate: CLOCK_GATE, + #[doc = "0x24 - MISC Register"] + pub sigmadelta_misc: SIGMADELTA_MISC, + #[doc = "0x28 - PAD Compare configure Register"] + pub pad_comp_config: PAD_COMP_CONFIG, + #[doc = "0x2c - Zero Detect filter Register"] + pub pad_comp_filter: PAD_COMP_FILTER, + #[doc = "0x30..0x50 - Glitch Filter Configure Register of Channel%s"] + pub glitch_filter_ch: [GLITCH_FILTER_CH; 8], + _reserved6: [u8; 0x10], + #[doc = "0x60..0x80 - Etm Config register of Channel%s"] + pub etm_event_ch_cfg: [ETM_EVENT_CH_CFG; 8], + _reserved7: [u8; 0x20], + #[doc = "0xa0 - Etm Configure Register to decide which GPIO been chosen"] + pub etm_task_p0_cfg: ETM_TASK_P0_CFG, + #[doc = "0xa4 - Etm Configure Register to decide which GPIO been chosen"] + pub etm_task_p1_cfg: ETM_TASK_P1_CFG, + #[doc = "0xa8 - Etm Configure Register to decide which GPIO been chosen"] + pub etm_task_p2_cfg: ETM_TASK_P2_CFG, + #[doc = "0xac - Etm Configure Register to decide which GPIO been chosen"] + pub etm_task_p3_cfg: ETM_TASK_P3_CFG, + #[doc = "0xb0 - Etm Configure Register to decide which GPIO been chosen"] + pub etm_task_p4_cfg: ETM_TASK_P4_CFG, + #[doc = "0xb4 - Etm Configure Register to decide which GPIO been chosen"] + pub etm_task_p5_cfg: ETM_TASK_P5_CFG, + #[doc = "0xb8 - Etm Configure Register to decide which GPIO been chosen"] + pub etm_task_p6_cfg: ETM_TASK_P6_CFG, + _reserved14: [u8; 0x24], + #[doc = "0xe0 - GPIOSD interrupt raw register"] + pub int_raw: INT_RAW, + #[doc = "0xe4 - GPIOSD interrupt masked register"] + pub int_st: INT_ST, + #[doc = "0xe8 - GPIOSD interrupt enable register"] + pub int_ena: INT_ENA, + #[doc = "0xec - GPIOSD interrupt clear register"] + pub int_clr: INT_CLR, + _reserved18: [u8; 0x0c], + #[doc = "0xfc - Version Control Register"] + pub version: VERSION, +} +#[doc = "SIGMADELTA (rw) register accessor: Duty Cycle Configure Register of SDM%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sigmadelta::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sigmadelta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sigmadelta`] module"] +pub type SIGMADELTA = crate::Reg; +#[doc = "Duty Cycle Configure Register of SDM%s"] +pub mod sigmadelta; +#[doc = "CLOCK_GATE (rw) register accessor: Clock Gating Configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clock_gate`] module"] +pub type CLOCK_GATE = crate::Reg; +#[doc = "Clock Gating Configure Register"] +pub mod clock_gate; +#[doc = "SIGMADELTA_MISC (rw) register accessor: MISC Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sigmadelta_misc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sigmadelta_misc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sigmadelta_misc`] module"] +pub type SIGMADELTA_MISC = crate::Reg; +#[doc = "MISC Register"] +pub mod sigmadelta_misc; +#[doc = "PAD_COMP_CONFIG (rw) register accessor: PAD Compare configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad_comp_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad_comp_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pad_comp_config`] module"] +pub type PAD_COMP_CONFIG = crate::Reg; +#[doc = "PAD Compare configure Register"] +pub mod pad_comp_config; +#[doc = "PAD_COMP_FILTER (rw) register accessor: Zero Detect filter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad_comp_filter::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad_comp_filter::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pad_comp_filter`] module"] +pub type PAD_COMP_FILTER = crate::Reg; +#[doc = "Zero Detect filter Register"] +pub mod pad_comp_filter; +#[doc = "GLITCH_FILTER_CH (rw) register accessor: Glitch Filter Configure Register of Channel%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`glitch_filter_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`glitch_filter_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`glitch_filter_ch`] module"] +pub type GLITCH_FILTER_CH = crate::Reg; +#[doc = "Glitch Filter Configure Register of Channel%s"] +pub mod glitch_filter_ch; +#[doc = "ETM_EVENT_CH_CFG (rw) register accessor: Etm Config register of Channel%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_event_ch_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_event_ch_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_event_ch_cfg`] module"] +pub type ETM_EVENT_CH_CFG = crate::Reg; +#[doc = "Etm Config register of Channel%s"] +pub mod etm_event_ch_cfg; +#[doc = "ETM_TASK_P0_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p0_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p0_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_task_p0_cfg`] module"] +pub type ETM_TASK_P0_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p0_cfg; +#[doc = "ETM_TASK_P1_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p1_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p1_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_task_p1_cfg`] module"] +pub type ETM_TASK_P1_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p1_cfg; +#[doc = "ETM_TASK_P2_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p2_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p2_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_task_p2_cfg`] module"] +pub type ETM_TASK_P2_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p2_cfg; +#[doc = "ETM_TASK_P3_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p3_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p3_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_task_p3_cfg`] module"] +pub type ETM_TASK_P3_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p3_cfg; +#[doc = "ETM_TASK_P4_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p4_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p4_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_task_p4_cfg`] module"] +pub type ETM_TASK_P4_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p4_cfg; +#[doc = "ETM_TASK_P5_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p5_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p5_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_task_p5_cfg`] module"] +pub type ETM_TASK_P5_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p5_cfg; +#[doc = "ETM_TASK_P6_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p6_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p6_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etm_task_p6_cfg`] module"] +pub type ETM_TASK_P6_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p6_cfg; +#[doc = "INT_RAW (r) register accessor: GPIOSD interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "GPIOSD interrupt raw register"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: GPIOSD interrupt masked register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "GPIOSD interrupt masked register"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: GPIOSD interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "GPIOSD interrupt enable register"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: GPIOSD interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "GPIOSD interrupt clear register"] +pub mod int_clr; +#[doc = "VERSION (rw) register accessor: Version Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`version`] module"] +pub type VERSION = crate::Reg; +#[doc = "Version Control Register"] +pub mod version; diff --git a/esp32h2/src/gpio_sd/clock_gate.rs b/esp32h2/src/gpio_sd/clock_gate.rs new file mode 100644 index 0000000000..ed9681504c --- /dev/null +++ b/esp32h2/src/gpio_sd/clock_gate.rs @@ -0,0 +1,59 @@ +#[doc = "Register `CLOCK_GATE` reader"] +pub type R = crate::R; +#[doc = "Register `CLOCK_GATE` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - Clock enable bit of configuration registers for sigma delta modulation."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Clock enable bit of configuration registers for sigma delta modulation."] +pub type CLK_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Clock enable bit of configuration registers for sigma delta modulation."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLOCK_GATE") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bit 0 - Clock enable bit of configuration registers for sigma delta modulation."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Clock Gating Configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLOCK_GATE_SPEC; +impl crate::RegisterSpec for CLOCK_GATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"] +impl crate::Readable for CLOCK_GATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"] +impl crate::Writable for CLOCK_GATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLOCK_GATE to value 0"] +impl crate::Resettable for CLOCK_GATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/etm_event_ch_cfg.rs b/esp32h2/src/gpio_sd/etm_event_ch_cfg.rs new file mode 100644 index 0000000000..5e05921281 --- /dev/null +++ b/esp32h2/src/gpio_sd/etm_event_ch_cfg.rs @@ -0,0 +1,81 @@ +#[doc = "Register `ETM_EVENT_CH%s_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_EVENT_CH%s_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_CH0_EVENT_SEL` reader - Etm event channel select gpio."] +pub type ETM_CH0_EVENT_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_CH0_EVENT_SEL` writer - Etm event channel select gpio."] +pub type ETM_CH0_EVENT_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +#[doc = "Field `ETM_CH0_EVENT_EN` reader - Etm event send enable bit."] +pub type ETM_CH0_EVENT_EN_R = crate::BitReader; +#[doc = "Field `ETM_CH0_EVENT_EN` writer - Etm event send enable bit."] +pub type ETM_CH0_EVENT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bits 0:4 - Etm event channel select gpio."] + #[inline(always)] + pub fn etm_ch0_event_sel(&self) -> ETM_CH0_EVENT_SEL_R { + ETM_CH0_EVENT_SEL_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 7 - Etm event send enable bit."] + #[inline(always)] + pub fn etm_ch0_event_en(&self) -> ETM_CH0_EVENT_EN_R { + ETM_CH0_EVENT_EN_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_EVENT_CH_CFG") + .field( + "etm_ch0_event_sel", + &format_args!("{}", self.etm_ch0_event_sel().bits()), + ) + .field( + "etm_ch0_event_en", + &format_args!("{}", self.etm_ch0_event_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bits 0:4 - Etm event channel select gpio."] + #[inline(always)] + #[must_use] + pub fn etm_ch0_event_sel(&mut self) -> ETM_CH0_EVENT_SEL_W { + ETM_CH0_EVENT_SEL_W::new(self) + } + #[doc = "Bit 7 - Etm event send enable bit."] + #[inline(always)] + #[must_use] + pub fn etm_ch0_event_en(&mut self) -> ETM_CH0_EVENT_EN_W { + ETM_CH0_EVENT_EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Config register of Channel%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_event_ch_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_event_ch_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_EVENT_CH_CFG_SPEC; +impl crate::RegisterSpec for ETM_EVENT_CH_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_event_ch_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_EVENT_CH_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_event_ch_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_EVENT_CH_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_EVENT_CH%s_CFG to value 0"] +impl crate::Resettable for ETM_EVENT_CH_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/etm_task_p0_cfg.rs b/esp32h2/src/gpio_sd/etm_task_p0_cfg.rs new file mode 100644 index 0000000000..7b9775b8b3 --- /dev/null +++ b/esp32h2/src/gpio_sd/etm_task_p0_cfg.rs @@ -0,0 +1,195 @@ +#[doc = "Register `ETM_TASK_P0_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P0_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO0_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO0_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO0_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO0_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO0_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO0_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO0_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO0_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO1_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO1_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO1_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO1_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO1_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO1_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO1_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO1_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO2_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO2_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO2_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO2_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO2_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO2_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO2_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO2_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO3_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO3_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO3_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO3_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO3_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO3_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO3_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO3_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio0_en(&self) -> ETM_TASK_GPIO0_EN_R { + ETM_TASK_GPIO0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio0_sel(&self) -> ETM_TASK_GPIO0_SEL_R { + ETM_TASK_GPIO0_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio1_en(&self) -> ETM_TASK_GPIO1_EN_R { + ETM_TASK_GPIO1_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio1_sel(&self) -> ETM_TASK_GPIO1_SEL_R { + ETM_TASK_GPIO1_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio2_en(&self) -> ETM_TASK_GPIO2_EN_R { + ETM_TASK_GPIO2_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio2_sel(&self) -> ETM_TASK_GPIO2_SEL_R { + ETM_TASK_GPIO2_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio3_en(&self) -> ETM_TASK_GPIO3_EN_R { + ETM_TASK_GPIO3_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio3_sel(&self) -> ETM_TASK_GPIO3_SEL_R { + ETM_TASK_GPIO3_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P0_CFG") + .field( + "etm_task_gpio0_en", + &format_args!("{}", self.etm_task_gpio0_en().bit()), + ) + .field( + "etm_task_gpio0_sel", + &format_args!("{}", self.etm_task_gpio0_sel().bits()), + ) + .field( + "etm_task_gpio1_en", + &format_args!("{}", self.etm_task_gpio1_en().bit()), + ) + .field( + "etm_task_gpio1_sel", + &format_args!("{}", self.etm_task_gpio1_sel().bits()), + ) + .field( + "etm_task_gpio2_en", + &format_args!("{}", self.etm_task_gpio2_en().bit()), + ) + .field( + "etm_task_gpio2_sel", + &format_args!("{}", self.etm_task_gpio2_sel().bits()), + ) + .field( + "etm_task_gpio3_en", + &format_args!("{}", self.etm_task_gpio3_en().bit()), + ) + .field( + "etm_task_gpio3_sel", + &format_args!("{}", self.etm_task_gpio3_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio0_en(&mut self) -> ETM_TASK_GPIO0_EN_W { + ETM_TASK_GPIO0_EN_W::new(self) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio0_sel(&mut self) -> ETM_TASK_GPIO0_SEL_W { + ETM_TASK_GPIO0_SEL_W::new(self) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio1_en(&mut self) -> ETM_TASK_GPIO1_EN_W { + ETM_TASK_GPIO1_EN_W::new(self) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio1_sel(&mut self) -> ETM_TASK_GPIO1_SEL_W { + ETM_TASK_GPIO1_SEL_W::new(self) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio2_en(&mut self) -> ETM_TASK_GPIO2_EN_W { + ETM_TASK_GPIO2_EN_W::new(self) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio2_sel(&mut self) -> ETM_TASK_GPIO2_SEL_W { + ETM_TASK_GPIO2_SEL_W::new(self) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio3_en(&mut self) -> ETM_TASK_GPIO3_EN_W { + ETM_TASK_GPIO3_EN_W::new(self) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio3_sel(&mut self) -> ETM_TASK_GPIO3_SEL_W { + ETM_TASK_GPIO3_SEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p0_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p0_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P0_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P0_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p0_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P0_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p0_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P0_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P0_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P0_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/etm_task_p1_cfg.rs b/esp32h2/src/gpio_sd/etm_task_p1_cfg.rs new file mode 100644 index 0000000000..d75069ecb3 --- /dev/null +++ b/esp32h2/src/gpio_sd/etm_task_p1_cfg.rs @@ -0,0 +1,195 @@ +#[doc = "Register `ETM_TASK_P1_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P1_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO4_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO4_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO4_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO4_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO4_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO4_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO4_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO4_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO5_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO5_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO5_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO5_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO5_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO5_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO5_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO5_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO6_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO6_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO6_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO6_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO6_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO6_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO6_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO6_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO7_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO7_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO7_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO7_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO7_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO7_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO7_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO7_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio4_en(&self) -> ETM_TASK_GPIO4_EN_R { + ETM_TASK_GPIO4_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio4_sel(&self) -> ETM_TASK_GPIO4_SEL_R { + ETM_TASK_GPIO4_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio5_en(&self) -> ETM_TASK_GPIO5_EN_R { + ETM_TASK_GPIO5_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio5_sel(&self) -> ETM_TASK_GPIO5_SEL_R { + ETM_TASK_GPIO5_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio6_en(&self) -> ETM_TASK_GPIO6_EN_R { + ETM_TASK_GPIO6_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio6_sel(&self) -> ETM_TASK_GPIO6_SEL_R { + ETM_TASK_GPIO6_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio7_en(&self) -> ETM_TASK_GPIO7_EN_R { + ETM_TASK_GPIO7_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio7_sel(&self) -> ETM_TASK_GPIO7_SEL_R { + ETM_TASK_GPIO7_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P1_CFG") + .field( + "etm_task_gpio4_en", + &format_args!("{}", self.etm_task_gpio4_en().bit()), + ) + .field( + "etm_task_gpio4_sel", + &format_args!("{}", self.etm_task_gpio4_sel().bits()), + ) + .field( + "etm_task_gpio5_en", + &format_args!("{}", self.etm_task_gpio5_en().bit()), + ) + .field( + "etm_task_gpio5_sel", + &format_args!("{}", self.etm_task_gpio5_sel().bits()), + ) + .field( + "etm_task_gpio6_en", + &format_args!("{}", self.etm_task_gpio6_en().bit()), + ) + .field( + "etm_task_gpio6_sel", + &format_args!("{}", self.etm_task_gpio6_sel().bits()), + ) + .field( + "etm_task_gpio7_en", + &format_args!("{}", self.etm_task_gpio7_en().bit()), + ) + .field( + "etm_task_gpio7_sel", + &format_args!("{}", self.etm_task_gpio7_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio4_en(&mut self) -> ETM_TASK_GPIO4_EN_W { + ETM_TASK_GPIO4_EN_W::new(self) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio4_sel(&mut self) -> ETM_TASK_GPIO4_SEL_W { + ETM_TASK_GPIO4_SEL_W::new(self) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio5_en(&mut self) -> ETM_TASK_GPIO5_EN_W { + ETM_TASK_GPIO5_EN_W::new(self) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio5_sel(&mut self) -> ETM_TASK_GPIO5_SEL_W { + ETM_TASK_GPIO5_SEL_W::new(self) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio6_en(&mut self) -> ETM_TASK_GPIO6_EN_W { + ETM_TASK_GPIO6_EN_W::new(self) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio6_sel(&mut self) -> ETM_TASK_GPIO6_SEL_W { + ETM_TASK_GPIO6_SEL_W::new(self) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio7_en(&mut self) -> ETM_TASK_GPIO7_EN_W { + ETM_TASK_GPIO7_EN_W::new(self) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio7_sel(&mut self) -> ETM_TASK_GPIO7_SEL_W { + ETM_TASK_GPIO7_SEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p1_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p1_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P1_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P1_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p1_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P1_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p1_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P1_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P1_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P1_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/etm_task_p2_cfg.rs b/esp32h2/src/gpio_sd/etm_task_p2_cfg.rs new file mode 100644 index 0000000000..80ba8ff694 --- /dev/null +++ b/esp32h2/src/gpio_sd/etm_task_p2_cfg.rs @@ -0,0 +1,195 @@ +#[doc = "Register `ETM_TASK_P2_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P2_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO8_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO8_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO8_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO8_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO8_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO8_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO8_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO8_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO9_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO9_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO9_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO9_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO9_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO9_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO9_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO9_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO10_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO10_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO10_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO10_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO10_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO10_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO10_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO10_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO11_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO11_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO11_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO11_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO11_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO11_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO11_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO11_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio8_en(&self) -> ETM_TASK_GPIO8_EN_R { + ETM_TASK_GPIO8_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio8_sel(&self) -> ETM_TASK_GPIO8_SEL_R { + ETM_TASK_GPIO8_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio9_en(&self) -> ETM_TASK_GPIO9_EN_R { + ETM_TASK_GPIO9_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio9_sel(&self) -> ETM_TASK_GPIO9_SEL_R { + ETM_TASK_GPIO9_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio10_en(&self) -> ETM_TASK_GPIO10_EN_R { + ETM_TASK_GPIO10_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio10_sel(&self) -> ETM_TASK_GPIO10_SEL_R { + ETM_TASK_GPIO10_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio11_en(&self) -> ETM_TASK_GPIO11_EN_R { + ETM_TASK_GPIO11_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio11_sel(&self) -> ETM_TASK_GPIO11_SEL_R { + ETM_TASK_GPIO11_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P2_CFG") + .field( + "etm_task_gpio8_en", + &format_args!("{}", self.etm_task_gpio8_en().bit()), + ) + .field( + "etm_task_gpio8_sel", + &format_args!("{}", self.etm_task_gpio8_sel().bits()), + ) + .field( + "etm_task_gpio9_en", + &format_args!("{}", self.etm_task_gpio9_en().bit()), + ) + .field( + "etm_task_gpio9_sel", + &format_args!("{}", self.etm_task_gpio9_sel().bits()), + ) + .field( + "etm_task_gpio10_en", + &format_args!("{}", self.etm_task_gpio10_en().bit()), + ) + .field( + "etm_task_gpio10_sel", + &format_args!("{}", self.etm_task_gpio10_sel().bits()), + ) + .field( + "etm_task_gpio11_en", + &format_args!("{}", self.etm_task_gpio11_en().bit()), + ) + .field( + "etm_task_gpio11_sel", + &format_args!("{}", self.etm_task_gpio11_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio8_en(&mut self) -> ETM_TASK_GPIO8_EN_W { + ETM_TASK_GPIO8_EN_W::new(self) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio8_sel(&mut self) -> ETM_TASK_GPIO8_SEL_W { + ETM_TASK_GPIO8_SEL_W::new(self) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio9_en(&mut self) -> ETM_TASK_GPIO9_EN_W { + ETM_TASK_GPIO9_EN_W::new(self) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio9_sel(&mut self) -> ETM_TASK_GPIO9_SEL_W { + ETM_TASK_GPIO9_SEL_W::new(self) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio10_en(&mut self) -> ETM_TASK_GPIO10_EN_W { + ETM_TASK_GPIO10_EN_W::new(self) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio10_sel(&mut self) -> ETM_TASK_GPIO10_SEL_W { + ETM_TASK_GPIO10_SEL_W::new(self) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio11_en(&mut self) -> ETM_TASK_GPIO11_EN_W { + ETM_TASK_GPIO11_EN_W::new(self) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio11_sel(&mut self) -> ETM_TASK_GPIO11_SEL_W { + ETM_TASK_GPIO11_SEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p2_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p2_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P2_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P2_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p2_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P2_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p2_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P2_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P2_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P2_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/etm_task_p3_cfg.rs b/esp32h2/src/gpio_sd/etm_task_p3_cfg.rs new file mode 100644 index 0000000000..7422038f7e --- /dev/null +++ b/esp32h2/src/gpio_sd/etm_task_p3_cfg.rs @@ -0,0 +1,195 @@ +#[doc = "Register `ETM_TASK_P3_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P3_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO12_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO12_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO12_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO12_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO12_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO12_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO12_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO12_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO13_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO13_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO13_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO13_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO13_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO13_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO13_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO13_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO14_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO14_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO14_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO14_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO14_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO14_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO14_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO14_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO15_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO15_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO15_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO15_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO15_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO15_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO15_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO15_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio12_en(&self) -> ETM_TASK_GPIO12_EN_R { + ETM_TASK_GPIO12_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio12_sel(&self) -> ETM_TASK_GPIO12_SEL_R { + ETM_TASK_GPIO12_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio13_en(&self) -> ETM_TASK_GPIO13_EN_R { + ETM_TASK_GPIO13_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio13_sel(&self) -> ETM_TASK_GPIO13_SEL_R { + ETM_TASK_GPIO13_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio14_en(&self) -> ETM_TASK_GPIO14_EN_R { + ETM_TASK_GPIO14_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio14_sel(&self) -> ETM_TASK_GPIO14_SEL_R { + ETM_TASK_GPIO14_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio15_en(&self) -> ETM_TASK_GPIO15_EN_R { + ETM_TASK_GPIO15_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio15_sel(&self) -> ETM_TASK_GPIO15_SEL_R { + ETM_TASK_GPIO15_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P3_CFG") + .field( + "etm_task_gpio12_en", + &format_args!("{}", self.etm_task_gpio12_en().bit()), + ) + .field( + "etm_task_gpio12_sel", + &format_args!("{}", self.etm_task_gpio12_sel().bits()), + ) + .field( + "etm_task_gpio13_en", + &format_args!("{}", self.etm_task_gpio13_en().bit()), + ) + .field( + "etm_task_gpio13_sel", + &format_args!("{}", self.etm_task_gpio13_sel().bits()), + ) + .field( + "etm_task_gpio14_en", + &format_args!("{}", self.etm_task_gpio14_en().bit()), + ) + .field( + "etm_task_gpio14_sel", + &format_args!("{}", self.etm_task_gpio14_sel().bits()), + ) + .field( + "etm_task_gpio15_en", + &format_args!("{}", self.etm_task_gpio15_en().bit()), + ) + .field( + "etm_task_gpio15_sel", + &format_args!("{}", self.etm_task_gpio15_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio12_en(&mut self) -> ETM_TASK_GPIO12_EN_W { + ETM_TASK_GPIO12_EN_W::new(self) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio12_sel(&mut self) -> ETM_TASK_GPIO12_SEL_W { + ETM_TASK_GPIO12_SEL_W::new(self) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio13_en(&mut self) -> ETM_TASK_GPIO13_EN_W { + ETM_TASK_GPIO13_EN_W::new(self) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio13_sel(&mut self) -> ETM_TASK_GPIO13_SEL_W { + ETM_TASK_GPIO13_SEL_W::new(self) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio14_en(&mut self) -> ETM_TASK_GPIO14_EN_W { + ETM_TASK_GPIO14_EN_W::new(self) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio14_sel(&mut self) -> ETM_TASK_GPIO14_SEL_W { + ETM_TASK_GPIO14_SEL_W::new(self) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio15_en(&mut self) -> ETM_TASK_GPIO15_EN_W { + ETM_TASK_GPIO15_EN_W::new(self) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio15_sel(&mut self) -> ETM_TASK_GPIO15_SEL_W { + ETM_TASK_GPIO15_SEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p3_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p3_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P3_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P3_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p3_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P3_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p3_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P3_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P3_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P3_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/etm_task_p4_cfg.rs b/esp32h2/src/gpio_sd/etm_task_p4_cfg.rs new file mode 100644 index 0000000000..c3c589651d --- /dev/null +++ b/esp32h2/src/gpio_sd/etm_task_p4_cfg.rs @@ -0,0 +1,195 @@ +#[doc = "Register `ETM_TASK_P4_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P4_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO16_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO16_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO16_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO16_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO16_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO16_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO16_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO16_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO17_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO17_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO17_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO17_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO17_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO17_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO17_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO17_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO18_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO18_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO18_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO18_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO18_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO18_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO18_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO18_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO19_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO19_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO19_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO19_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO19_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO19_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO19_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO19_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio16_en(&self) -> ETM_TASK_GPIO16_EN_R { + ETM_TASK_GPIO16_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio16_sel(&self) -> ETM_TASK_GPIO16_SEL_R { + ETM_TASK_GPIO16_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio17_en(&self) -> ETM_TASK_GPIO17_EN_R { + ETM_TASK_GPIO17_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio17_sel(&self) -> ETM_TASK_GPIO17_SEL_R { + ETM_TASK_GPIO17_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio18_en(&self) -> ETM_TASK_GPIO18_EN_R { + ETM_TASK_GPIO18_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio18_sel(&self) -> ETM_TASK_GPIO18_SEL_R { + ETM_TASK_GPIO18_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio19_en(&self) -> ETM_TASK_GPIO19_EN_R { + ETM_TASK_GPIO19_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio19_sel(&self) -> ETM_TASK_GPIO19_SEL_R { + ETM_TASK_GPIO19_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P4_CFG") + .field( + "etm_task_gpio16_en", + &format_args!("{}", self.etm_task_gpio16_en().bit()), + ) + .field( + "etm_task_gpio16_sel", + &format_args!("{}", self.etm_task_gpio16_sel().bits()), + ) + .field( + "etm_task_gpio17_en", + &format_args!("{}", self.etm_task_gpio17_en().bit()), + ) + .field( + "etm_task_gpio17_sel", + &format_args!("{}", self.etm_task_gpio17_sel().bits()), + ) + .field( + "etm_task_gpio18_en", + &format_args!("{}", self.etm_task_gpio18_en().bit()), + ) + .field( + "etm_task_gpio18_sel", + &format_args!("{}", self.etm_task_gpio18_sel().bits()), + ) + .field( + "etm_task_gpio19_en", + &format_args!("{}", self.etm_task_gpio19_en().bit()), + ) + .field( + "etm_task_gpio19_sel", + &format_args!("{}", self.etm_task_gpio19_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio16_en(&mut self) -> ETM_TASK_GPIO16_EN_W { + ETM_TASK_GPIO16_EN_W::new(self) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio16_sel(&mut self) -> ETM_TASK_GPIO16_SEL_W { + ETM_TASK_GPIO16_SEL_W::new(self) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio17_en(&mut self) -> ETM_TASK_GPIO17_EN_W { + ETM_TASK_GPIO17_EN_W::new(self) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio17_sel(&mut self) -> ETM_TASK_GPIO17_SEL_W { + ETM_TASK_GPIO17_SEL_W::new(self) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio18_en(&mut self) -> ETM_TASK_GPIO18_EN_W { + ETM_TASK_GPIO18_EN_W::new(self) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio18_sel(&mut self) -> ETM_TASK_GPIO18_SEL_W { + ETM_TASK_GPIO18_SEL_W::new(self) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio19_en(&mut self) -> ETM_TASK_GPIO19_EN_W { + ETM_TASK_GPIO19_EN_W::new(self) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio19_sel(&mut self) -> ETM_TASK_GPIO19_SEL_W { + ETM_TASK_GPIO19_SEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p4_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p4_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P4_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P4_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p4_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P4_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p4_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P4_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P4_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P4_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/etm_task_p5_cfg.rs b/esp32h2/src/gpio_sd/etm_task_p5_cfg.rs new file mode 100644 index 0000000000..7dc1900334 --- /dev/null +++ b/esp32h2/src/gpio_sd/etm_task_p5_cfg.rs @@ -0,0 +1,195 @@ +#[doc = "Register `ETM_TASK_P5_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P5_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO20_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO20_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO20_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO20_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO20_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO20_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO20_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO20_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO21_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO21_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO21_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO21_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO21_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO21_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO21_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO21_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO22_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO22_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO22_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO22_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO22_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO22_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO22_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO22_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO23_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO23_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO23_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO23_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO23_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO23_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO23_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO23_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio20_en(&self) -> ETM_TASK_GPIO20_EN_R { + ETM_TASK_GPIO20_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio20_sel(&self) -> ETM_TASK_GPIO20_SEL_R { + ETM_TASK_GPIO20_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio21_en(&self) -> ETM_TASK_GPIO21_EN_R { + ETM_TASK_GPIO21_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio21_sel(&self) -> ETM_TASK_GPIO21_SEL_R { + ETM_TASK_GPIO21_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio22_en(&self) -> ETM_TASK_GPIO22_EN_R { + ETM_TASK_GPIO22_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio22_sel(&self) -> ETM_TASK_GPIO22_SEL_R { + ETM_TASK_GPIO22_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio23_en(&self) -> ETM_TASK_GPIO23_EN_R { + ETM_TASK_GPIO23_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio23_sel(&self) -> ETM_TASK_GPIO23_SEL_R { + ETM_TASK_GPIO23_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P5_CFG") + .field( + "etm_task_gpio20_en", + &format_args!("{}", self.etm_task_gpio20_en().bit()), + ) + .field( + "etm_task_gpio20_sel", + &format_args!("{}", self.etm_task_gpio20_sel().bits()), + ) + .field( + "etm_task_gpio21_en", + &format_args!("{}", self.etm_task_gpio21_en().bit()), + ) + .field( + "etm_task_gpio21_sel", + &format_args!("{}", self.etm_task_gpio21_sel().bits()), + ) + .field( + "etm_task_gpio22_en", + &format_args!("{}", self.etm_task_gpio22_en().bit()), + ) + .field( + "etm_task_gpio22_sel", + &format_args!("{}", self.etm_task_gpio22_sel().bits()), + ) + .field( + "etm_task_gpio23_en", + &format_args!("{}", self.etm_task_gpio23_en().bit()), + ) + .field( + "etm_task_gpio23_sel", + &format_args!("{}", self.etm_task_gpio23_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio20_en(&mut self) -> ETM_TASK_GPIO20_EN_W { + ETM_TASK_GPIO20_EN_W::new(self) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio20_sel(&mut self) -> ETM_TASK_GPIO20_SEL_W { + ETM_TASK_GPIO20_SEL_W::new(self) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio21_en(&mut self) -> ETM_TASK_GPIO21_EN_W { + ETM_TASK_GPIO21_EN_W::new(self) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio21_sel(&mut self) -> ETM_TASK_GPIO21_SEL_W { + ETM_TASK_GPIO21_SEL_W::new(self) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio22_en(&mut self) -> ETM_TASK_GPIO22_EN_W { + ETM_TASK_GPIO22_EN_W::new(self) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio22_sel(&mut self) -> ETM_TASK_GPIO22_SEL_W { + ETM_TASK_GPIO22_SEL_W::new(self) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio23_en(&mut self) -> ETM_TASK_GPIO23_EN_W { + ETM_TASK_GPIO23_EN_W::new(self) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio23_sel(&mut self) -> ETM_TASK_GPIO23_SEL_W { + ETM_TASK_GPIO23_SEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p5_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p5_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P5_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P5_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p5_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P5_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p5_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P5_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P5_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P5_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/etm_task_p6_cfg.rs b/esp32h2/src/gpio_sd/etm_task_p6_cfg.rs new file mode 100644 index 0000000000..34dac4b6ea --- /dev/null +++ b/esp32h2/src/gpio_sd/etm_task_p6_cfg.rs @@ -0,0 +1,195 @@ +#[doc = "Register `ETM_TASK_P6_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P6_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO24_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO24_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO24_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO24_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO24_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO24_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO24_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO24_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO25_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO25_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO25_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO25_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO25_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO25_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO25_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO25_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO26_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO26_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO26_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO26_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO26_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO26_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO26_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO26_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ETM_TASK_GPIO27_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO27_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO27_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO27_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `ETM_TASK_GPIO27_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO27_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO27_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO27_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio24_en(&self) -> ETM_TASK_GPIO24_EN_R { + ETM_TASK_GPIO24_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio24_sel(&self) -> ETM_TASK_GPIO24_SEL_R { + ETM_TASK_GPIO24_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio25_en(&self) -> ETM_TASK_GPIO25_EN_R { + ETM_TASK_GPIO25_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio25_sel(&self) -> ETM_TASK_GPIO25_SEL_R { + ETM_TASK_GPIO25_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio26_en(&self) -> ETM_TASK_GPIO26_EN_R { + ETM_TASK_GPIO26_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio26_sel(&self) -> ETM_TASK_GPIO26_SEL_R { + ETM_TASK_GPIO26_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio27_en(&self) -> ETM_TASK_GPIO27_EN_R { + ETM_TASK_GPIO27_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio27_sel(&self) -> ETM_TASK_GPIO27_SEL_R { + ETM_TASK_GPIO27_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P6_CFG") + .field( + "etm_task_gpio24_en", + &format_args!("{}", self.etm_task_gpio24_en().bit()), + ) + .field( + "etm_task_gpio24_sel", + &format_args!("{}", self.etm_task_gpio24_sel().bits()), + ) + .field( + "etm_task_gpio25_en", + &format_args!("{}", self.etm_task_gpio25_en().bit()), + ) + .field( + "etm_task_gpio25_sel", + &format_args!("{}", self.etm_task_gpio25_sel().bits()), + ) + .field( + "etm_task_gpio26_en", + &format_args!("{}", self.etm_task_gpio26_en().bit()), + ) + .field( + "etm_task_gpio26_sel", + &format_args!("{}", self.etm_task_gpio26_sel().bits()), + ) + .field( + "etm_task_gpio27_en", + &format_args!("{}", self.etm_task_gpio27_en().bit()), + ) + .field( + "etm_task_gpio27_sel", + &format_args!("{}", self.etm_task_gpio27_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio24_en(&mut self) -> ETM_TASK_GPIO24_EN_W { + ETM_TASK_GPIO24_EN_W::new(self) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio24_sel(&mut self) -> ETM_TASK_GPIO24_SEL_W { + ETM_TASK_GPIO24_SEL_W::new(self) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio25_en(&mut self) -> ETM_TASK_GPIO25_EN_W { + ETM_TASK_GPIO25_EN_W::new(self) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio25_sel(&mut self) -> ETM_TASK_GPIO25_SEL_W { + ETM_TASK_GPIO25_SEL_W::new(self) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio26_en(&mut self) -> ETM_TASK_GPIO26_EN_W { + ETM_TASK_GPIO26_EN_W::new(self) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio26_sel(&mut self) -> ETM_TASK_GPIO26_SEL_W { + ETM_TASK_GPIO26_SEL_W::new(self) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio27_en(&mut self) -> ETM_TASK_GPIO27_EN_W { + ETM_TASK_GPIO27_EN_W::new(self) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio27_sel(&mut self) -> ETM_TASK_GPIO27_SEL_W { + ETM_TASK_GPIO27_SEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p6_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p6_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P6_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P6_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p6_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P6_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p6_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P6_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P6_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P6_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/glitch_filter_ch.rs b/esp32h2/src/gpio_sd/glitch_filter_ch.rs new file mode 100644 index 0000000000..b005167691 --- /dev/null +++ b/esp32h2/src/gpio_sd/glitch_filter_ch.rs @@ -0,0 +1,125 @@ +#[doc = "Register `GLITCH_FILTER_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `GLITCH_FILTER_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `FILTER_CH0_EN` reader - Glitch Filter channel enable bit."] +pub type FILTER_CH0_EN_R = crate::BitReader; +#[doc = "Field `FILTER_CH0_EN` writer - Glitch Filter channel enable bit."] +pub type FILTER_CH0_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `FILTER_CH0_INPUT_IO_NUM` reader - Glitch Filter input io number."] +pub type FILTER_CH0_INPUT_IO_NUM_R = crate::FieldReader; +#[doc = "Field `FILTER_CH0_INPUT_IO_NUM` writer - Glitch Filter input io number."] +pub type FILTER_CH0_INPUT_IO_NUM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +#[doc = "Field `FILTER_CH0_WINDOW_THRES` reader - Glitch Filter window threshold."] +pub type FILTER_CH0_WINDOW_THRES_R = crate::FieldReader; +#[doc = "Field `FILTER_CH0_WINDOW_THRES` writer - Glitch Filter window threshold."] +pub type FILTER_CH0_WINDOW_THRES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +#[doc = "Field `FILTER_CH0_WINDOW_WIDTH` reader - Glitch Filter window width."] +pub type FILTER_CH0_WINDOW_WIDTH_R = crate::FieldReader; +#[doc = "Field `FILTER_CH0_WINDOW_WIDTH` writer - Glitch Filter window width."] +pub type FILTER_CH0_WINDOW_WIDTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +impl R { + #[doc = "Bit 0 - Glitch Filter channel enable bit."] + #[inline(always)] + pub fn filter_ch0_en(&self) -> FILTER_CH0_EN_R { + FILTER_CH0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:6 - Glitch Filter input io number."] + #[inline(always)] + pub fn filter_ch0_input_io_num(&self) -> FILTER_CH0_INPUT_IO_NUM_R { + FILTER_CH0_INPUT_IO_NUM_R::new(((self.bits >> 1) & 0x3f) as u8) + } + #[doc = "Bits 7:12 - Glitch Filter window threshold."] + #[inline(always)] + pub fn filter_ch0_window_thres(&self) -> FILTER_CH0_WINDOW_THRES_R { + FILTER_CH0_WINDOW_THRES_R::new(((self.bits >> 7) & 0x3f) as u8) + } + #[doc = "Bits 13:18 - Glitch Filter window width."] + #[inline(always)] + pub fn filter_ch0_window_width(&self) -> FILTER_CH0_WINDOW_WIDTH_R { + FILTER_CH0_WINDOW_WIDTH_R::new(((self.bits >> 13) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GLITCH_FILTER_CH") + .field( + "filter_ch0_en", + &format_args!("{}", self.filter_ch0_en().bit()), + ) + .field( + "filter_ch0_input_io_num", + &format_args!("{}", self.filter_ch0_input_io_num().bits()), + ) + .field( + "filter_ch0_window_thres", + &format_args!("{}", self.filter_ch0_window_thres().bits()), + ) + .field( + "filter_ch0_window_width", + &format_args!("{}", self.filter_ch0_window_width().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bit 0 - Glitch Filter channel enable bit."] + #[inline(always)] + #[must_use] + pub fn filter_ch0_en(&mut self) -> FILTER_CH0_EN_W { + FILTER_CH0_EN_W::new(self) + } + #[doc = "Bits 1:6 - Glitch Filter input io number."] + #[inline(always)] + #[must_use] + pub fn filter_ch0_input_io_num( + &mut self, + ) -> FILTER_CH0_INPUT_IO_NUM_W { + FILTER_CH0_INPUT_IO_NUM_W::new(self) + } + #[doc = "Bits 7:12 - Glitch Filter window threshold."] + #[inline(always)] + #[must_use] + pub fn filter_ch0_window_thres( + &mut self, + ) -> FILTER_CH0_WINDOW_THRES_W { + FILTER_CH0_WINDOW_THRES_W::new(self) + } + #[doc = "Bits 13:18 - Glitch Filter window width."] + #[inline(always)] + #[must_use] + pub fn filter_ch0_window_width( + &mut self, + ) -> FILTER_CH0_WINDOW_WIDTH_W { + FILTER_CH0_WINDOW_WIDTH_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Glitch Filter Configure Register of Channel%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`glitch_filter_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`glitch_filter_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GLITCH_FILTER_CH_SPEC; +impl crate::RegisterSpec for GLITCH_FILTER_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`glitch_filter_ch::R`](R) reader structure"] +impl crate::Readable for GLITCH_FILTER_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`glitch_filter_ch::W`](W) writer structure"] +impl crate::Writable for GLITCH_FILTER_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GLITCH_FILTER_CH%s to value 0"] +impl crate::Resettable for GLITCH_FILTER_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/int_clr.rs b/esp32h2/src/gpio_sd/int_clr.rs new file mode 100644 index 0000000000..ec7e639725 --- /dev/null +++ b/esp32h2/src/gpio_sd/int_clr.rs @@ -0,0 +1,38 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `PAD_COMP_INT_CLR` writer - Pad compare interrupt clear"] +pub type PAD_COMP_INT_CLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Pad compare interrupt clear"] + #[inline(always)] + #[must_use] + pub fn pad_comp_int_clr(&mut self) -> PAD_COMP_INT_CLR_W { + PAD_COMP_INT_CLR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIOSD interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/int_ena.rs b/esp32h2/src/gpio_sd/int_ena.rs new file mode 100644 index 0000000000..fb0e7efaa6 --- /dev/null +++ b/esp32h2/src/gpio_sd/int_ena.rs @@ -0,0 +1,62 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `PAD_COMP_INT_ENA` reader - Pad compare interrupt enable"] +pub type PAD_COMP_INT_ENA_R = crate::BitReader; +#[doc = "Field `PAD_COMP_INT_ENA` writer - Pad compare interrupt enable"] +pub type PAD_COMP_INT_ENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 0 - Pad compare interrupt enable"] + #[inline(always)] + pub fn pad_comp_int_ena(&self) -> PAD_COMP_INT_ENA_R { + PAD_COMP_INT_ENA_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "pad_comp_int_ena", + &format_args!("{}", self.pad_comp_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bit 0 - Pad compare interrupt enable"] + #[inline(always)] + #[must_use] + pub fn pad_comp_int_ena(&mut self) -> PAD_COMP_INT_ENA_W { + PAD_COMP_INT_ENA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIOSD interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/int_raw.rs b/esp32h2/src/gpio_sd/int_raw.rs new file mode 100644 index 0000000000..a4e4b6efcc --- /dev/null +++ b/esp32h2/src/gpio_sd/int_raw.rs @@ -0,0 +1,39 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `PAD_COMP_INT_RAW` reader - Pad compare raw interrupt"] +pub type PAD_COMP_INT_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Pad compare raw interrupt"] + #[inline(always)] + pub fn pad_comp_int_raw(&self) -> PAD_COMP_INT_RAW_R { + PAD_COMP_INT_RAW_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "pad_comp_int_raw", + &format_args!("{}", self.pad_comp_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "GPIOSD interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/int_st.rs b/esp32h2/src/gpio_sd/int_st.rs new file mode 100644 index 0000000000..ac288012a8 --- /dev/null +++ b/esp32h2/src/gpio_sd/int_st.rs @@ -0,0 +1,39 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `PAD_COMP_INT_ST` reader - Pad compare masked interrupt"] +pub type PAD_COMP_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Pad compare masked interrupt"] + #[inline(always)] + pub fn pad_comp_int_st(&self) -> PAD_COMP_INT_ST_R { + PAD_COMP_INT_ST_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "pad_comp_int_st", + &format_args!("{}", self.pad_comp_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "GPIOSD interrupt masked register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/pad_comp_config.rs b/esp32h2/src/gpio_sd/pad_comp_config.rs new file mode 100644 index 0000000000..4e3729999c --- /dev/null +++ b/esp32h2/src/gpio_sd/pad_comp_config.rs @@ -0,0 +1,110 @@ +#[doc = "Register `PAD_COMP_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `PAD_COMP_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `XPD_COMP` reader - Pad compare enable bit."] +pub type XPD_COMP_R = crate::BitReader; +#[doc = "Field `XPD_COMP` writer - Pad compare enable bit."] +pub type XPD_COMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `MODE_COMP` reader - 1 to enable external reference from PAD\\[0\\]. 0 to enable internal reference, meanwhile PAD\\[0\\] can be used as a regular GPIO."] +pub type MODE_COMP_R = crate::BitReader; +#[doc = "Field `MODE_COMP` writer - 1 to enable external reference from PAD\\[0\\]. 0 to enable internal reference, meanwhile PAD\\[0\\] can be used as a regular GPIO."] +pub type MODE_COMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `DREF_COMP` reader - internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST."] +pub type DREF_COMP_R = crate::FieldReader; +#[doc = "Field `DREF_COMP` writer - internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST."] +pub type DREF_COMP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +#[doc = "Field `ZERO_DET_MODE` reader - Zero Detect mode select."] +pub type ZERO_DET_MODE_R = crate::FieldReader; +#[doc = "Field `ZERO_DET_MODE` writer - Zero Detect mode select."] +pub type ZERO_DET_MODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +impl R { + #[doc = "Bit 0 - Pad compare enable bit."] + #[inline(always)] + pub fn xpd_comp(&self) -> XPD_COMP_R { + XPD_COMP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1 to enable external reference from PAD\\[0\\]. 0 to enable internal reference, meanwhile PAD\\[0\\] can be used as a regular GPIO."] + #[inline(always)] + pub fn mode_comp(&self) -> MODE_COMP_R { + MODE_COMP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:4 - internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST."] + #[inline(always)] + pub fn dref_comp(&self) -> DREF_COMP_R { + DREF_COMP_R::new(((self.bits >> 2) & 7) as u8) + } + #[doc = "Bits 5:6 - Zero Detect mode select."] + #[inline(always)] + pub fn zero_det_mode(&self) -> ZERO_DET_MODE_R { + ZERO_DET_MODE_R::new(((self.bits >> 5) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD_COMP_CONFIG") + .field("xpd_comp", &format_args!("{}", self.xpd_comp().bit())) + .field("mode_comp", &format_args!("{}", self.mode_comp().bit())) + .field("dref_comp", &format_args!("{}", self.dref_comp().bits())) + .field( + "zero_det_mode", + &format_args!("{}", self.zero_det_mode().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bit 0 - Pad compare enable bit."] + #[inline(always)] + #[must_use] + pub fn xpd_comp(&mut self) -> XPD_COMP_W { + XPD_COMP_W::new(self) + } + #[doc = "Bit 1 - 1 to enable external reference from PAD\\[0\\]. 0 to enable internal reference, meanwhile PAD\\[0\\] can be used as a regular GPIO."] + #[inline(always)] + #[must_use] + pub fn mode_comp(&mut self) -> MODE_COMP_W { + MODE_COMP_W::new(self) + } + #[doc = "Bits 2:4 - internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST."] + #[inline(always)] + #[must_use] + pub fn dref_comp(&mut self) -> DREF_COMP_W { + DREF_COMP_W::new(self) + } + #[doc = "Bits 5:6 - Zero Detect mode select."] + #[inline(always)] + #[must_use] + pub fn zero_det_mode(&mut self) -> ZERO_DET_MODE_W { + ZERO_DET_MODE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PAD Compare configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad_comp_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad_comp_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD_COMP_CONFIG_SPEC; +impl crate::RegisterSpec for PAD_COMP_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad_comp_config::R`](R) reader structure"] +impl crate::Readable for PAD_COMP_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad_comp_config::W`](W) writer structure"] +impl crate::Writable for PAD_COMP_CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD_COMP_CONFIG to value 0"] +impl crate::Resettable for PAD_COMP_CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/pad_comp_filter.rs b/esp32h2/src/gpio_sd/pad_comp_filter.rs new file mode 100644 index 0000000000..a69816588a --- /dev/null +++ b/esp32h2/src/gpio_sd/pad_comp_filter.rs @@ -0,0 +1,62 @@ +#[doc = "Register `PAD_COMP_FILTER` reader"] +pub type R = crate::R; +#[doc = "Register `PAD_COMP_FILTER` writer"] +pub type W = crate::W; +#[doc = "Field `ZERO_DET_FILTER_CNT` reader - Zero Detect filter cycle length"] +pub type ZERO_DET_FILTER_CNT_R = crate::FieldReader; +#[doc = "Field `ZERO_DET_FILTER_CNT` writer - Zero Detect filter cycle length"] +pub type ZERO_DET_FILTER_CNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +impl R { + #[doc = "Bits 0:31 - Zero Detect filter cycle length"] + #[inline(always)] + pub fn zero_det_filter_cnt(&self) -> ZERO_DET_FILTER_CNT_R { + ZERO_DET_FILTER_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD_COMP_FILTER") + .field( + "zero_det_filter_cnt", + &format_args!("{}", self.zero_det_filter_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bits 0:31 - Zero Detect filter cycle length"] + #[inline(always)] + #[must_use] + pub fn zero_det_filter_cnt(&mut self) -> ZERO_DET_FILTER_CNT_W { + ZERO_DET_FILTER_CNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Zero Detect filter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad_comp_filter::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad_comp_filter::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD_COMP_FILTER_SPEC; +impl crate::RegisterSpec for PAD_COMP_FILTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad_comp_filter::R`](R) reader structure"] +impl crate::Readable for PAD_COMP_FILTER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad_comp_filter::W`](W) writer structure"] +impl crate::Writable for PAD_COMP_FILTER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD_COMP_FILTER to value 0"] +impl crate::Resettable for PAD_COMP_FILTER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/sigmadelta.rs b/esp32h2/src/gpio_sd/sigmadelta.rs new file mode 100644 index 0000000000..87d7fd6b90 --- /dev/null +++ b/esp32h2/src/gpio_sd/sigmadelta.rs @@ -0,0 +1,78 @@ +#[doc = "Register `SIGMADELTA%s` reader"] +pub type R = crate::R; +#[doc = "Register `SIGMADELTA%s` writer"] +pub type W = crate::W; +#[doc = "Field `SD_IN` reader - This field is used to configure the duty cycle of sigma delta modulation output."] +pub type SD_IN_R = crate::FieldReader; +#[doc = "Field `SD_IN` writer - This field is used to configure the duty cycle of sigma delta modulation output."] +pub type SD_IN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +#[doc = "Field `SD_PRESCALE` reader - This field is used to set a divider value to divide APB clock."] +pub type SD_PRESCALE_R = crate::FieldReader; +#[doc = "Field `SD_PRESCALE` writer - This field is used to set a divider value to divide APB clock."] +pub type SD_PRESCALE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +impl R { + #[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."] + #[inline(always)] + pub fn sd_in(&self) -> SD_IN_R { + SD_IN_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - This field is used to set a divider value to divide APB clock."] + #[inline(always)] + pub fn sd_prescale(&self) -> SD_PRESCALE_R { + SD_PRESCALE_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SIGMADELTA") + .field("sd_in", &format_args!("{}", self.sd_in().bits())) + .field( + "sd_prescale", + &format_args!("{}", self.sd_prescale().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."] + #[inline(always)] + #[must_use] + pub fn sd_in(&mut self) -> SD_IN_W { + SD_IN_W::new(self) + } + #[doc = "Bits 8:15 - This field is used to set a divider value to divide APB clock."] + #[inline(always)] + #[must_use] + pub fn sd_prescale(&mut self) -> SD_PRESCALE_W { + SD_PRESCALE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Duty Cycle Configure Register of SDM%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sigmadelta::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sigmadelta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SIGMADELTA_SPEC; +impl crate::RegisterSpec for SIGMADELTA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sigmadelta::R`](R) reader structure"] +impl crate::Readable for SIGMADELTA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sigmadelta::W`](W) writer structure"] +impl crate::Writable for SIGMADELTA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SIGMADELTA%s to value 0xff00"] +impl crate::Resettable for SIGMADELTA_SPEC { + const RESET_VALUE: Self::Ux = 0xff00; +} diff --git a/esp32h2/src/gpio_sd/sigmadelta_misc.rs b/esp32h2/src/gpio_sd/sigmadelta_misc.rs new file mode 100644 index 0000000000..ced994893d --- /dev/null +++ b/esp32h2/src/gpio_sd/sigmadelta_misc.rs @@ -0,0 +1,78 @@ +#[doc = "Register `SIGMADELTA_MISC` reader"] +pub type R = crate::R; +#[doc = "Register `SIGMADELTA_MISC` writer"] +pub type W = crate::W; +#[doc = "Field `FUNCTION_CLK_EN` reader - Clock enable bit of sigma delta modulation."] +pub type FUNCTION_CLK_EN_R = crate::BitReader; +#[doc = "Field `FUNCTION_CLK_EN` writer - Clock enable bit of sigma delta modulation."] +pub type FUNCTION_CLK_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +#[doc = "Field `SPI_SWAP` reader - Reserved."] +pub type SPI_SWAP_R = crate::BitReader; +#[doc = "Field `SPI_SWAP` writer - Reserved."] +pub type SPI_SWAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl R { + #[doc = "Bit 30 - Clock enable bit of sigma delta modulation."] + #[inline(always)] + pub fn function_clk_en(&self) -> FUNCTION_CLK_EN_R { + FUNCTION_CLK_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Reserved."] + #[inline(always)] + pub fn spi_swap(&self) -> SPI_SWAP_R { + SPI_SWAP_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SIGMADELTA_MISC") + .field( + "function_clk_en", + &format_args!("{}", self.function_clk_en().bit()), + ) + .field("spi_swap", &format_args!("{}", self.spi_swap().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bit 30 - Clock enable bit of sigma delta modulation."] + #[inline(always)] + #[must_use] + pub fn function_clk_en(&mut self) -> FUNCTION_CLK_EN_W { + FUNCTION_CLK_EN_W::new(self) + } + #[doc = "Bit 31 - Reserved."] + #[inline(always)] + #[must_use] + pub fn spi_swap(&mut self) -> SPI_SWAP_W { + SPI_SWAP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MISC Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sigmadelta_misc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sigmadelta_misc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SIGMADELTA_MISC_SPEC; +impl crate::RegisterSpec for SIGMADELTA_MISC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sigmadelta_misc::R`](R) reader structure"] +impl crate::Readable for SIGMADELTA_MISC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sigmadelta_misc::W`](W) writer structure"] +impl crate::Writable for SIGMADELTA_MISC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SIGMADELTA_MISC to value 0"] +impl crate::Resettable for SIGMADELTA_MISC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32h2/src/gpio_sd/version.rs b/esp32h2/src/gpio_sd/version.rs new file mode 100644 index 0000000000..770e39fe85 --- /dev/null +++ b/esp32h2/src/gpio_sd/version.rs @@ -0,0 +1,62 @@ +#[doc = "Register `VERSION` reader"] +pub type R = crate::R; +#[doc = "Register `VERSION` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_SD_DATE` reader - Version control register."] +pub type GPIO_SD_DATE_R = crate::FieldReader; +#[doc = "Field `GPIO_SD_DATE` writer - Version control register."] +pub type GPIO_SD_DATE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 28, O, u32>; +impl R { + #[doc = "Bits 0:27 - Version control register."] + #[inline(always)] + pub fn gpio_sd_date(&self) -> GPIO_SD_DATE_R { + GPIO_SD_DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VERSION") + .field( + "gpio_sd_date", + &format_args!("{}", self.gpio_sd_date().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +impl W { + #[doc = "Bits 0:27 - Version control register."] + #[inline(always)] + #[must_use] + pub fn gpio_sd_date(&mut self) -> GPIO_SD_DATE_W { + GPIO_SD_DATE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`version::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VERSION_SPEC; +impl crate::RegisterSpec for VERSION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`version::R`](R) reader structure"] +impl crate::Readable for VERSION_SPEC {} +#[doc = "`write(|w| ..)` method takes [`version::W`](W) writer structure"] +impl crate::Writable for VERSION_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VERSION to value 0x0220_8120"] +impl crate::Resettable for VERSION_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_8120; +} diff --git a/esp32h2/src/hmac/query_error.rs b/esp32h2/src/hmac/query_error.rs index 14d9f6932f..a431ccd05c 100644 --- a/esp32h2/src/hmac/query_error.rs +++ b/esp32h2/src/hmac/query_error.rs @@ -1,19 +1,19 @@ #[doc = "Register `QUERY_ERROR` reader"] pub type R = crate::R; -#[doc = "Field `QUREY_CHECK` reader - Hmac configuration state. 0: key are agree with purpose. 1: error"] -pub type QUREY_CHECK_R = crate::BitReader; +#[doc = "Field `QUERY_CHECK` reader - Hmac configuration state. 0: key are agree with purpose. 1: error"] +pub type QUERY_CHECK_R = crate::BitReader; impl R { #[doc = "Bit 0 - Hmac configuration state. 0: key are agree with purpose. 1: error"] #[inline(always)] - pub fn qurey_check(&self) -> QUREY_CHECK_R { - QUREY_CHECK_R::new((self.bits & 1) != 0) + pub fn query_check(&self) -> QUERY_CHECK_R { + QUERY_CHECK_R::new((self.bits & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("QUERY_ERROR") - .field("qurey_check", &format_args!("{}", self.qurey_check().bit())) + .field("query_check", &format_args!("{}", self.query_check().bit())) .finish() } } diff --git a/esp32h2/src/lib.rs b/esp32h2/src/lib.rs index eadd6c6819..bd6a72f6a3 100644 --- a/esp32h2/src/lib.rs +++ b/esp32h2/src/lib.rs @@ -606,6 +606,52 @@ impl core::fmt::Debug for GPIO { } #[doc = "General Purpose Input/Output"] pub mod gpio; +#[doc = "Sigma-Delta Modulation"] +pub struct GPIO_SD { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GPIO_SD {} +impl GPIO_SD { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gpio_sd::RegisterBlock = 0x6009_1f00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpio_sd::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for GPIO_SD { + type Target = gpio_sd::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GPIO_SD { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_SD").finish() + } +} +#[doc = "Sigma-Delta Modulation"] +pub mod gpio_sd; #[doc = "HMAC (Hash-based Message Authentication Code) Accelerator"] pub struct HMAC { _marker: PhantomData<*const ()>, @@ -2697,6 +2743,8 @@ pub struct Peripherals { pub EFUSE: EFUSE, #[doc = "GPIO"] pub GPIO: GPIO, + #[doc = "GPIO_SD"] + pub GPIO_SD: GPIO_SD, #[doc = "HMAC"] pub HMAC: HMAC, #[doc = "HP_APM"] @@ -2833,6 +2881,9 @@ impl Peripherals { GPIO: GPIO { _marker: PhantomData, }, + GPIO_SD: GPIO_SD { + _marker: PhantomData, + }, HMAC: HMAC { _marker: PhantomData, }, diff --git a/esp32h2/svd/esp32h2.base.svd b/esp32h2/svd/esp32h2.base.svd index 93d95ecd9e..5fe1ae4a81 100644 --- a/esp32h2/svd/esp32h2.base.svd +++ b/esp32h2/svd/esp32h2.base.svd @@ -4,7 +4,7 @@ ESPRESSIF ESP32-H2 ESP32 H-Series - 7 + 8 32-bit RISC-V MCU & Bluetooth 5 (LE) & IEEE 802.15.4 Copyright 2023 Espressif Systems (Shanghai) PTE LTD @@ -7296,6 +7296,718 @@ + + GPIO_SD + Sigma-Delta Modulation + GPIOSD + 0x60091F00 + + 0x0 + 0x90 + registers + + + + 4 + 0x4 + SIGMADELTA%s + Duty Cycle Configure Register of SDM%s + 0x0 + 0x20 + 0x0000FF00 + + + SD_IN + This field is used to configure the duty cycle of sigma delta modulation output. + 0 + 8 + read-write + + + SD_PRESCALE + This field is used to set a divider value to divide APB clock. + 8 + 8 + read-write + + + + + CLOCK_GATE + Clock Gating Configure Register + 0x20 + 0x20 + + + CLK_EN + Clock enable bit of configuration registers for sigma delta modulation. + 0 + 1 + read-write + + + + + SIGMADELTA_MISC + MISC Register + 0x24 + 0x20 + + + FUNCTION_CLK_EN + Clock enable bit of sigma delta modulation. + 30 + 1 + read-write + + + SPI_SWAP + Reserved. + 31 + 1 + read-write + + + + + PAD_COMP_CONFIG + PAD Compare configure Register + 0x28 + 0x20 + + + XPD_COMP + Pad compare enable bit. + 0 + 1 + read-write + + + MODE_COMP + 1 to enable external reference from PAD[0]. 0 to enable internal reference, meanwhile PAD[0] can be used as a regular GPIO. + 1 + 1 + read-write + + + DREF_COMP + internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST. + 2 + 3 + read-write + + + ZERO_DET_MODE + Zero Detect mode select. + 5 + 2 + read-write + + + + + PAD_COMP_FILTER + Zero Detect filter Register + 0x2C + 0x20 + + + ZERO_DET_FILTER_CNT + Zero Detect filter cycle length + 0 + 32 + read-write + + + + + 8 + 0x4 + GLITCH_FILTER_CH%s + Glitch Filter Configure Register of Channel%s + 0x30 + 0x20 + + + FILTER_CH0_EN + Glitch Filter channel enable bit. + 0 + 1 + read-write + + + FILTER_CH0_INPUT_IO_NUM + Glitch Filter input io number. + 1 + 6 + read-write + + + FILTER_CH0_WINDOW_THRES + Glitch Filter window threshold. + 7 + 6 + read-write + + + FILTER_CH0_WINDOW_WIDTH + Glitch Filter window width. + 13 + 6 + read-write + + + + + 8 + 0x4 + ETM_EVENT_CH%s_CFG + Etm Config register of Channel%s + 0x60 + 0x20 + + + ETM_CH0_EVENT_SEL + Etm event channel select gpio. + 0 + 5 + read-write + + + ETM_CH0_EVENT_EN + Etm event send enable bit. + 7 + 1 + read-write + + + + + ETM_TASK_P0_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA0 + 0x20 + + + ETM_TASK_GPIO0_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO0_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO1_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO1_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO2_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO2_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO3_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO3_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P1_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA4 + 0x20 + + + ETM_TASK_GPIO4_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO4_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO5_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO5_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO6_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO6_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO7_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO7_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P2_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA8 + 0x20 + + + ETM_TASK_GPIO8_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO8_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO9_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO9_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO10_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO10_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO11_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO11_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P3_CFG + Etm Configure Register to decide which GPIO been chosen + 0xAC + 0x20 + + + ETM_TASK_GPIO12_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO12_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO13_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO13_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO14_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO14_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO15_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO15_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P4_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB0 + 0x20 + + + ETM_TASK_GPIO16_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO16_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO17_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO17_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO18_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO18_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO19_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO19_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P5_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB4 + 0x20 + + + ETM_TASK_GPIO20_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO20_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO21_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO21_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO22_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO22_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO23_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO23_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P6_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB8 + 0x20 + + + ETM_TASK_GPIO24_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO24_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO25_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO25_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO26_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO26_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO27_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO27_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + INT_RAW + GPIOSD interrupt raw register + 0xE0 + 0x20 + + + PAD_COMP_INT_RAW + Pad compare raw interrupt + 0 + 1 + read-only + + + + + INT_ST + GPIOSD interrupt masked register + 0xE4 + 0x20 + + + PAD_COMP_INT_ST + Pad compare masked interrupt + 0 + 1 + read-only + + + + + INT_ENA + GPIOSD interrupt enable register + 0xE8 + 0x20 + + + PAD_COMP_INT_ENA + Pad compare interrupt enable + 0 + 1 + read-write + + + + + INT_CLR + GPIOSD interrupt clear register + 0xEC + 0x20 + + + PAD_COMP_INT_CLR + Pad compare interrupt clear + 0 + 1 + write-only + + + + + VERSION + Version Control Register + 0xFC + 0x20 + 0x02208120 + + + GPIO_SD_DATE + Version control register. + 0 + 28 + read-write + + + + + HMAC HMAC (Hash-based Message Authentication Code) Accelerator @@ -7464,7 +8176,7 @@ 0x20 - QUREY_CHECK + QUERY_CHECK Hmac configuration state. 0: key are agree with purpose. 1: error 0 1