From 33e4212f4360d2f909245e2c48a45466140903f6 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Tue, 22 Oct 2024 12:43:52 +0200 Subject: [PATCH] Align RSA interrupt enable register/field name for S2/S3 with other chips --- esp32s2/src/rsa.rs | 12 ++--- esp32s2/src/rsa/int_ena.rs | 48 ++++++++++++++++++++ esp32s2/src/rsa/interrupt_ena.rs | 48 -------------------- esp32s2/svd/patches/esp32s2.yaml | 10 +++++ esp32s3/src/rsa.rs | 12 ++--- esp32s3/src/rsa/int_ena.rs | 48 ++++++++++++++++++++ esp32s3/src/rsa/interrupt_ena.rs | 48 -------------------- esp32s3/svd/patches/esp32s3.yaml | 76 ++++++++++++++++++-------------- 8 files changed, 161 insertions(+), 141 deletions(-) create mode 100644 esp32s2/src/rsa/int_ena.rs delete mode 100644 esp32s2/src/rsa/interrupt_ena.rs create mode 100644 esp32s3/src/rsa/int_ena.rs delete mode 100644 esp32s3/src/rsa/interrupt_ena.rs diff --git a/esp32s2/src/rsa.rs b/esp32s2/src/rsa.rs index e15e3047e..79e446e41 100644 --- a/esp32s2/src/rsa.rs +++ b/esp32s2/src/rsa.rs @@ -17,7 +17,7 @@ pub struct RegisterBlock { constant_time: CONSTANT_TIME, search_enable: SEARCH_ENABLE, search_pos: SEARCH_POS, - interrupt_ena: INTERRUPT_ENA, + int_ena: INT_ENA, date: DATE, } impl RegisterBlock { @@ -122,8 +122,8 @@ impl RegisterBlock { } #[doc = "0x82c - RSA interrupt enable register"] #[inline(always)] - pub const fn interrupt_ena(&self) -> &INTERRUPT_ENA { - &self.interrupt_ena + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena } #[doc = "0x830 - Version control register"] #[inline(always)] @@ -175,10 +175,10 @@ pub mod search_enable; pub type SEARCH_POS = crate::Reg; #[doc = "The search position"] pub mod search_pos; -#[doc = "INTERRUPT_ENA (rw) register accessor: RSA interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`interrupt_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interrupt_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interrupt_ena`] module"] -pub type INTERRUPT_ENA = crate::Reg; +#[doc = "INT_ENA (rw) register accessor: RSA interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; #[doc = "RSA interrupt enable register"] -pub mod interrupt_ena; +pub mod int_ena; #[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] pub type DATE = crate::Reg; #[doc = "Version control register"] diff --git a/esp32s2/src/rsa/int_ena.rs b/esp32s2/src/rsa/int_ena.rs new file mode 100644 index 000000000..f17e2caca --- /dev/null +++ b/esp32s2/src/rsa/int_ena.rs @@ -0,0 +1,48 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `INT_ENA` reader - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] +pub type INT_ENA_R = crate::BitReader; +#[doc = "Field `INT_ENA` writer - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] +pub type INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] + #[inline(always)] + pub fn int_ena(&self) -> INT_ENA_R { + INT_ENA_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field("int_ena", &self.int_ena()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] + #[inline(always)] + #[must_use] + pub fn int_ena(&mut self) -> INT_ENA_W { + INT_ENA_W::new(self, 0) + } +} +#[doc = "RSA interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0x01"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/esp32s2/src/rsa/interrupt_ena.rs b/esp32s2/src/rsa/interrupt_ena.rs deleted file mode 100644 index 0e23195f6..000000000 --- a/esp32s2/src/rsa/interrupt_ena.rs +++ /dev/null @@ -1,48 +0,0 @@ -#[doc = "Register `INTERRUPT_ENA` reader"] -pub type R = crate::R; -#[doc = "Register `INTERRUPT_ENA` writer"] -pub type W = crate::W; -#[doc = "Field `INTERRUPT_ENA` reader - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] -pub type INTERRUPT_ENA_R = crate::BitReader; -#[doc = "Field `INTERRUPT_ENA` writer - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] -pub type INTERRUPT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] - #[inline(always)] - pub fn interrupt_ena(&self) -> INTERRUPT_ENA_R { - INTERRUPT_ENA_R::new((self.bits & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("INTERRUPT_ENA") - .field("interrupt_ena", &self.interrupt_ena()) - .finish() - } -} -impl W { - #[doc = "Bit 0 - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] - #[inline(always)] - #[must_use] - pub fn interrupt_ena(&mut self) -> INTERRUPT_ENA_W { - INTERRUPT_ENA_W::new(self, 0) - } -} -#[doc = "RSA interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`interrupt_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interrupt_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct INTERRUPT_ENA_SPEC; -impl crate::RegisterSpec for INTERRUPT_ENA_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`interrupt_ena::R`](R) reader structure"] -impl crate::Readable for INTERRUPT_ENA_SPEC {} -#[doc = "`write(|w| ..)` method takes [`interrupt_ena::W`](W) writer structure"] -impl crate::Writable for INTERRUPT_ENA_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets INTERRUPT_ENA to value 0x01"] -impl crate::Resettable for INTERRUPT_ENA_SPEC { - const RESET_VALUE: u32 = 0x01; -} diff --git a/esp32s2/svd/patches/esp32s2.yaml b/esp32s2/svd/patches/esp32s2.yaml index 07ccf711e..77c5db445 100644 --- a/esp32s2/svd/patches/esp32s2.yaml +++ b/esp32s2/svd/patches/esp32s2.yaml @@ -342,3 +342,13 @@ SYSTIMER: USB0: _include: ../../../common_patches/usb0.yaml + +RSA: + _modify: + INTERRUPT_ENA: + name: INT_ENA + + INT_ENA: + _modify: + INTERRUPT_ENA: + name: INT_ENA diff --git a/esp32s3/src/rsa.rs b/esp32s3/src/rsa.rs index fe58fe6e4..931b77afd 100644 --- a/esp32s3/src/rsa.rs +++ b/esp32s3/src/rsa.rs @@ -17,7 +17,7 @@ pub struct RegisterBlock { constant_time: CONSTANT_TIME, search_enable: SEARCH_ENABLE, search_pos: SEARCH_POS, - interrupt_ena: INTERRUPT_ENA, + int_ena: INT_ENA, date: DATE, } impl RegisterBlock { @@ -122,8 +122,8 @@ impl RegisterBlock { } #[doc = "0x82c - RSA interrupt enable register"] #[inline(always)] - pub const fn interrupt_ena(&self) -> &INTERRUPT_ENA { - &self.interrupt_ena + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena } #[doc = "0x830 - RSA version control register"] #[inline(always)] @@ -191,10 +191,10 @@ pub mod search_enable; pub type SEARCH_POS = crate::Reg; #[doc = "RSA search position configure register"] pub mod search_pos; -#[doc = "INTERRUPT_ENA (rw) register accessor: RSA interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`interrupt_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interrupt_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interrupt_ena`] module"] -pub type INTERRUPT_ENA = crate::Reg; +#[doc = "INT_ENA (rw) register accessor: RSA interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; #[doc = "RSA interrupt enable register"] -pub mod interrupt_ena; +pub mod int_ena; #[doc = "DATE (rw) register accessor: RSA version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] pub type DATE = crate::Reg; #[doc = "RSA version control register"] diff --git a/esp32s3/src/rsa/int_ena.rs b/esp32s3/src/rsa/int_ena.rs new file mode 100644 index 000000000..f586503c0 --- /dev/null +++ b/esp32s3/src/rsa/int_ena.rs @@ -0,0 +1,48 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `INT_ENA` reader - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] +pub type INT_ENA_R = crate::BitReader; +#[doc = "Field `INT_ENA` writer - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] +pub type INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] + #[inline(always)] + pub fn int_ena(&self) -> INT_ENA_R { + INT_ENA_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field("int_ena", &self.int_ena()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] + #[inline(always)] + #[must_use] + pub fn int_ena(&mut self) -> INT_ENA_W { + INT_ENA_W::new(self, 0) + } +} +#[doc = "RSA interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s3/src/rsa/interrupt_ena.rs b/esp32s3/src/rsa/interrupt_ena.rs deleted file mode 100644 index a7325a622..000000000 --- a/esp32s3/src/rsa/interrupt_ena.rs +++ /dev/null @@ -1,48 +0,0 @@ -#[doc = "Register `INTERRUPT_ENA` reader"] -pub type R = crate::R; -#[doc = "Register `INTERRUPT_ENA` writer"] -pub type W = crate::W; -#[doc = "Field `INTERRUPT_ENA` reader - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] -pub type INTERRUPT_ENA_R = crate::BitReader; -#[doc = "Field `INTERRUPT_ENA` writer - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] -pub type INTERRUPT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] - #[inline(always)] - pub fn interrupt_ena(&self) -> INTERRUPT_ENA_R { - INTERRUPT_ENA_R::new((self.bits & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("INTERRUPT_ENA") - .field("interrupt_ena", &self.interrupt_ena()) - .finish() - } -} -impl W { - #[doc = "Bit 0 - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."] - #[inline(always)] - #[must_use] - pub fn interrupt_ena(&mut self) -> INTERRUPT_ENA_W { - INTERRUPT_ENA_W::new(self, 0) - } -} -#[doc = "RSA interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`interrupt_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interrupt_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct INTERRUPT_ENA_SPEC; -impl crate::RegisterSpec for INTERRUPT_ENA_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`interrupt_ena::R`](R) reader structure"] -impl crate::Readable for INTERRUPT_ENA_SPEC {} -#[doc = "`write(|w| ..)` method takes [`interrupt_ena::W`](W) writer structure"] -impl crate::Writable for INTERRUPT_ENA_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets INTERRUPT_ENA to value 0"] -impl crate::Resettable for INTERRUPT_ENA_SPEC { - const RESET_VALUE: u32 = 0; -} diff --git a/esp32s3/svd/patches/esp32s3.yaml b/esp32s3/svd/patches/esp32s3.yaml index aba7f79b3..75ee5bc2a 100644 --- a/esp32s3/svd/patches/esp32s3.yaml +++ b/esp32s3/svd/patches/esp32s3.yaml @@ -66,21 +66,21 @@ _add: usage: registers registers: GEN_CTRL: - description: "FE General Control Register" - addressOffset: 0x0090 - size: 0x2 - access: read-write - fields: - IQ_EST_FORCE_PU: - description: "Force Power Up for IQ Estimation" - bitOffset: 5 - bitWidth: 1 - access: read-write - IQ_EST_FORCE_PD: - description: "Force Power Down for IQ Estimation" - bitOffset: 4 - bitWidth: 1 - access: read-write + description: "FE General Control Register" + addressOffset: 0x0090 + size: 0x2 + access: read-write + fields: + IQ_EST_FORCE_PU: + description: "Force Power Up for IQ Estimation" + bitOffset: 5 + bitWidth: 1 + access: read-write + IQ_EST_FORCE_PD: + description: "Force Power Down for IQ Estimation" + bitOffset: 4 + bitWidth: 1 + access: read-write FE2: description: need des baseAddress: 0x60005000 @@ -91,21 +91,21 @@ _add: usage: registers registers: TX_INTERP_CTRL: - description: "FE2 TX Interpolation Control Register" - addressOffset: 0x00f0 - size: 0x20 - access: read-write - fields: - TX_INF_FORCE_PU: - description: "Force Power Up field" - bitOffset: 10 - bitWidth: 1 - access: read-write - TX_INF_FORCE_PD: - description: "Force Power Down field" - bitOffset: 9 - bitWidth: 1 - access: read-write + description: "FE2 TX Interpolation Control Register" + addressOffset: 0x00f0 + size: 0x20 + access: read-write + fields: + TX_INF_FORCE_PU: + description: "Force Power Up field" + bitOffset: 10 + bitWidth: 1 + access: read-write + TX_INF_FORCE_PD: + description: "Force Power Down field" + bitOffset: 9 + bitWidth: 1 + access: read-write _modify: SPI?: @@ -139,7 +139,7 @@ I2C0: _modify: INT_STATUS: name: INT_ST - _include: + _include: - ../../../common_patches/int_strip.yaml - ../../../common_patches/i2c0.yaml @@ -167,7 +167,7 @@ RTC_CNTL: _include: ../../../common_patches/int_strip.yaml LEDC: - _include: + _include: - ../../../common_patches/ledc_collect.yaml - ../../../common_patches/ledc_int.yaml @@ -226,7 +226,7 @@ SPI2: _include: ../../../common_patches/spi_dma_int_strip.yaml SYSTIMER: - _include: + _include: - ../../../common_patches/int_strip.yaml - ../../../common_patches/systimer.yaml - ../../../common_patches/systimer_real_target.yaml @@ -452,3 +452,13 @@ LCD_CAM: FallingEdge: [2, Delayed by the falling edge of LCD_CLK] _array: DOUT*_MODE: {} + +RSA: + _modify: + INTERRUPT_ENA: + name: INT_ENA + + INT_ENA: + _modify: + INTERRUPT_ENA: + name: INT_ENA