forked from flashrom/flashrom
-
Notifications
You must be signed in to change notification settings - Fork 0
/
chipset_enable.c
2141 lines (1912 loc) · 78 KB
/
chipset_enable.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* This file is part of the flashrom project.
*
* Copyright (C) 2000 Silicon Integrated System Corporation
* Copyright (C) 2005-2009 coresystems GmbH
* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
* Copyright (C) 2009 Kontron Modular Computers GmbH
* Copyright (C) 2011, 2012 Stefan Tauner
* Copyright (C) 2017 secunet Security Networks AG
* (Written by Nico Huber <nico.huber@secunet.com> for secunet)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Contains the chipset specific flash enables.
*/
#define _LARGEFILE64_SOURCE
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <inttypes.h>
#include <errno.h>
#include "flash.h"
#include "programmer.h"
#include "hwaccess.h"
#define NOT_DONE_YET 1
#if defined(__i386__) || defined(__x86_64__)
static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
/*
* ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
* 0xFFFE0000-0xFFFFFFFF ROM select enable.
*/
tmp = pci_read_byte(dev, 0x47);
tmp |= 0x46;
rpci_write_byte(dev, 0x47, tmp);
return 0;
}
static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
/* enable ROMCS for writes */
tmp = pci_read_byte(dev, 0x43);
tmp |= 0x80;
pci_write_byte(dev, 0x43, tmp);
/* read the bootstrapping register */
tmp = pci_read_byte(dev, 0x40) & 0x3;
switch (tmp) {
case 3:
internal_buses_supported &= BUS_FWH;
break;
case 2:
internal_buses_supported &= BUS_LPC;
break;
default:
internal_buses_supported &= BUS_PARALLEL;
break;
}
return 0;
}
static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
tmp = pci_read_byte(dev, 0xd0);
tmp |= 0xf8;
rpci_write_byte(dev, 0xd0, tmp);
return 0;
}
static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
{
#define SIS_MAPREG 0x40
uint8_t new, newer;
/* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
/* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
new = pci_read_byte(dev, SIS_MAPREG);
new &= (~0x04); /* No idea why we clear bit 2. */
new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
rpci_write_byte(dev, SIS_MAPREG, new);
newer = pci_read_byte(dev, SIS_MAPREG);
if (newer != new) { /* FIXME: share this with other code? */
msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
SIS_MAPREG, new, name);
msg_pinfo("Stuck at 0x%02x.\n", newer);
return -1;
}
return 0;
}
static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
{
struct pci_dev *sbdev;
sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
if (!sbdev)
sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
if (!sbdev)
sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
if (!sbdev)
msg_perr("No southbridge found for %s!\n", name);
if (sbdev)
msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
sbdev->vendor_id, sbdev->device_id,
sbdev->bus, sbdev->dev, sbdev->func);
return sbdev;
}
static int enable_flash_sis501(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
int ret = 0;
struct pci_dev *sbdev;
sbdev = find_southbridge(dev->vendor_id, name);
if (!sbdev)
return -1;
ret = enable_flash_sis_mapping(sbdev, name);
tmp = sio_read(0x22, 0x80);
tmp &= (~0x20);
tmp |= 0x4;
sio_write(0x22, 0x80, tmp);
tmp = sio_read(0x22, 0x70);
tmp &= (~0x20);
tmp |= 0x4;
sio_write(0x22, 0x70, tmp);
return ret;
}
static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
int ret = 0;
struct pci_dev *sbdev;
sbdev = find_southbridge(dev->vendor_id, name);
if (!sbdev)
return -1;
ret = enable_flash_sis_mapping(sbdev, name);
tmp = sio_read(0x22, 0x50);
tmp &= (~0x20);
tmp |= 0x4;
sio_write(0x22, 0x50, tmp);
return ret;
}
static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t dis_mask, uint8_t en_mask)
{
#define SIS_REG 0x45
uint8_t new, newer;
int ret = 0;
struct pci_dev *sbdev;
sbdev = find_southbridge(dev->vendor_id, name);
if (!sbdev)
return -1;
ret = enable_flash_sis_mapping(sbdev, name);
new = pci_read_byte(sbdev, SIS_REG);
new &= (~dis_mask);
new |= en_mask;
rpci_write_byte(sbdev, SIS_REG, new);
newer = pci_read_byte(sbdev, SIS_REG);
if (newer != new) { /* FIXME: share this with other code? */
msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SIS_REG, new, name);
msg_pinfo("Stuck at 0x%02x\n", newer);
ret = -1;
}
return ret;
}
static int enable_flash_sis530(struct pci_dev *dev, const char *name)
{
return enable_flash_sis5x0(dev, name, 0x20, 0x04);
}
static int enable_flash_sis540(struct pci_dev *dev, const char *name)
{
return enable_flash_sis5x0(dev, name, 0x80, 0x40);
}
/* Datasheet:
* - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
* - URL: http://www.intel.com/design/intarch/datashts/290562.htm
* - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
* - Order Number: 290562-001
*/
static int enable_flash_piix4(struct pci_dev *dev, const char *name)
{
uint16_t old, new;
uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
internal_buses_supported &= BUS_PARALLEL;
old = pci_read_word(dev, xbcs);
/* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
* FFF00000-FFF7FFFF are forwarded to ISA).
* Note: This bit is reserved on PIIX/PIIX3/MPIIX.
* Set bit 7: Extended BIOS Enable (PCI master accesses to
* FFF80000-FFFDFFFF are forwarded to ISA).
* Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
* the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
* of 1 Mbyte, or the aliases at the top of 4 Gbyte
* (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
* Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
* Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
*/
if (dev->device_id == 0x122e || dev->device_id == 0x7000
|| dev->device_id == 0x1234)
new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
else
new = old | 0x02c4;
if (new == old)
return 0;
rpci_write_word(dev, xbcs, new);
if (pci_read_word(dev, xbcs) != new) { /* FIXME: share this with other code? */
msg_pinfo("Setting register 0x%04x to 0x%04x on %s failed (WARNING ONLY).\n", xbcs, new, name);
return -1;
}
return 0;
}
/* Handle BIOS_CNTL (aka. BCR). Disable locks and enable writes. The register can either be in PCI config space
* at the offset given by 'bios_cntl' or at the memory-mapped address 'addr'.
*
* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom
* chipsets/SoCs it is even 32b, but just treating it as 8 bit wide seems to work fine in practice. */
static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, void *addr,
struct pci_dev *dev, uint8_t bios_cntl)
{
uint8_t old, new, wanted;
switch (ich_generation) {
case CHIPSET_ICH_UNKNOWN:
return ERROR_FATAL;
/* Non-SPI-capable */
case CHIPSET_ICH:
case CHIPSET_ICH2345:
break;
/* Some Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to
* what other SPI-capable chipsets have at DCh. Others like Bay Trail use a memmapped register.
* The Tunnel Creek datasheet contains a lot of details about the SPI controller, among other things it
* mentions that the prefetching and caching does only happen for direct memory reads.
* Therefore - at least for Tunnel Creek - it should not matter to flashrom because we use the
* programmed access only and not memory mapping. */
case CHIPSET_TUNNEL_CREEK:
case CHIPSET_POULSBO:
case CHIPSET_CENTERTON:
old = pci_read_byte(dev, bios_cntl + 1);
msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis");
break;
case CHIPSET_BAYTRAIL:
case CHIPSET_ICH7:
default: /* Future version might behave the same */
if (ich_generation == CHIPSET_BAYTRAIL)
old = (mmio_readl(addr) >> 2) & 0x3;
else
old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3;
msg_pdbg("SPI Read Configuration: ");
if (old == 3)
msg_pdbg("invalid prefetching/caching settings, ");
else
msg_pdbg("prefetching %sabled, caching %sabled, ",
(old & 0x2) ? "en" : "dis",
(old & 0x1) ? "dis" : "en");
}
if (ich_generation == CHIPSET_BAYTRAIL)
wanted = old = mmio_readl(addr);
else
wanted = old = pci_read_byte(dev, bios_cntl);
/*
* Quote from the 6 Series datasheet (Document Number: 324645-004):
* "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP)
* 1 = BIOS region SMM protection is enabled.
* The BIOS Region is not writable unless all processors are in SMM."
* In earlier chipsets this bit is reserved.
*
* Try to unset it in any case.
* It won't hurt and makes sense in some cases according to Stefan Reinauer.
*
* At least in Centerton aforementioned bit is located at bit 7. It is unspecified in all other Atom
* and Desktop chipsets before Ibex Peak/5 Series, but we reset bit 5 anyway.
*/
int smm_bwp_bit;
if (ich_generation == CHIPSET_CENTERTON)
smm_bwp_bit = 7;
else
smm_bwp_bit = 5;
wanted &= ~(1 << smm_bwp_bit);
/* Tunnel Creek has a cache disable at bit 2 of the lowest BIOS_CNTL byte. */
if (ich_generation == CHIPSET_TUNNEL_CREEK)
wanted |= (1 << 2);
wanted |= (1 << 0); /* Set BIOS Write Enable */
wanted &= ~(1 << 1); /* Disable lock (futile) */
/* Only write the register if it's necessary */
if (wanted != old) {
if (ich_generation == CHIPSET_BAYTRAIL) {
rmmio_writel(wanted, addr);
new = mmio_readl(addr);
} else {
rpci_write_byte(dev, bios_cntl, wanted);
new = pci_read_byte(dev, bios_cntl);
}
} else
new = old;
msg_pdbg("\nBIOS_CNTL = 0x%02x: ", new);
msg_pdbg("BIOS Lock Enable: %sabled, ", (new & (1 << 1)) ? "en" : "dis");
msg_pdbg("BIOS Write Enable: %sabled\n", (new & (1 << 0)) ? "en" : "dis");
if (new & (1 << smm_bwp_bit))
msg_pwarn("Warning: BIOS region SMM protection is enabled!\n");
if (new != wanted)
msg_pwarn("Warning: Setting BIOS Control at 0x%x from 0x%02x to 0x%02x failed.\n"
"New value is 0x%02x.\n", bios_cntl, old, wanted, new);
/* Return an error if we could not set the write enable only. */
if (!(new & (1 << 0)))
return -1;
return 0;
}
static int enable_flash_ich_bios_cntl_config_space(struct pci_dev *dev, enum ich_chipset ich_generation,
uint8_t bios_cntl)
{
return enable_flash_ich_bios_cntl_common(ich_generation, NULL, dev, bios_cntl);
}
static int enable_flash_ich_bios_cntl_memmapped(enum ich_chipset ich_generation, void *addr)
{
return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0);
}
static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation)
{
uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */
bool implemented = 0;
void *ilb = NULL; /* Only for Baytrail */
switch (ich_generation) {
case CHIPSET_ICH:
/* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB
* and therefore do only feature FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */
break;
case CHIPSET_ICH2345:
fwh_sel1 = 0xe8;
fwh_sel2 = 0xee;
fwh_dec_en_lo = 0xf0;
fwh_dec_en_hi = 0xe3;
implemented = 1;
break;
case CHIPSET_POULSBO:
case CHIPSET_TUNNEL_CREEK:
/* FIXME: Similar to ICH and ICH-0, Tunnel Creek and Poulsbo do only feature one register each,
* FWH_DEC_EN (D7h) and FWH_SEL (D0h). */
break;
case CHIPSET_CENTERTON:
/* FIXME: Similar to above FWH_DEC_EN (D4h) and FWH_SEL (D0h). */
break;
case CHIPSET_BAYTRAIL: {
uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */
if (ilb_base == 0) {
msg_perr("Error: Invalid ILB_BASE_ADDRESS\n");
return ERROR_FATAL;
}
ilb = rphysmap("BYT IBASE", ilb_base, 512);
fwh_sel1 = 0x18;
fwh_dec_en_lo = 0xd8;
fwh_dec_en_hi = 0xd9;
implemented = 1;
break;
}
case CHIPSET_ICH6:
case CHIPSET_ICH7:
default: /* Future version might behave the same */
fwh_sel1 = 0xd0;
fwh_sel2 = 0xd4;
fwh_dec_en_lo = 0xd8;
fwh_dec_en_hi = 0xd9;
implemented = 1;
break;
}
char *idsel = extract_programmer_param("fwh_idsel");
if (idsel && strlen(idsel)) {
if (!implemented) {
msg_perr("Error: fwh_idsel= specified, but (yet) unsupported on this chipset.\n");
goto idsel_garbage_out;
}
errno = 0;
/* Base 16, nothing else makes sense. */
uint64_t fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16);
if (errno) {
msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n");
goto idsel_garbage_out;
}
uint64_t fwh_mask = 0xffffffff;
if (fwh_sel2 > 0)
fwh_mask |= (0xffffULL << 32);
if (fwh_idsel & ~fwh_mask) {
msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n");
goto idsel_garbage_out;
}
uint64_t fwh_idsel_old;
if (ich_generation == CHIPSET_BAYTRAIL) {
fwh_idsel_old = mmio_readl(ilb + fwh_sel1);
rmmio_writel(fwh_idsel, ilb + fwh_sel1);
} else {
fwh_idsel_old = (uint64_t)pci_read_long(dev, fwh_sel1) << 16;
rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff);
if (fwh_sel2 > 0) {
fwh_idsel_old |= pci_read_word(dev, fwh_sel2);
rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff);
}
}
msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n",
fwh_idsel_old, fwh_idsel);
/* FIXME: Decode settings are not changed. */
} else if (idsel) {
msg_perr("Error: fwh_idsel= specified, but no value given.\n");
idsel_garbage_out:
free(idsel);
return ERROR_FATAL;
}
free(idsel);
if (!implemented) {
msg_pdbg2("FWH IDSEL handling is not implemented on this chipset.\n");
return 0;
}
/* Ignore all legacy ranges below 1 MB.
* We currently only support flashing the chip which responds to
* IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
* have to be adjusted.
*/
int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0;
bool contiguous = 1;
uint32_t fwh_conf;
if (ich_generation == CHIPSET_BAYTRAIL)
fwh_conf = mmio_readl(ilb + fwh_sel1);
else
fwh_conf = pci_read_long(dev, fwh_sel1);
int i;
/* FWH_SEL1 */
for (i = 7; i >= 0; i--) {
int tmp = (fwh_conf >> (i * 4)) & 0xf;
msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
(0x1ff8 + i) * 0x80000,
(0x1ff0 + i) * 0x80000,
tmp);
if ((tmp == 0) && contiguous) {
max_decode_fwh_idsel = (8 - i) * 0x80000;
} else {
contiguous = 0;
}
}
if (fwh_sel2 > 0) {
/* FWH_SEL2 */
fwh_conf = pci_read_word(dev, fwh_sel2);
for (i = 3; i >= 0; i--) {
int tmp = (fwh_conf >> (i * 4)) & 0xf;
msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
(0xff4 + i) * 0x100000,
(0xff0 + i) * 0x100000,
tmp);
if ((tmp == 0) && contiguous) {
max_decode_fwh_idsel = (8 - i) * 0x100000;
} else {
contiguous = 0;
}
}
}
contiguous = 1;
/* FWH_DEC_EN1 */
fwh_conf = pci_read_byte(dev, fwh_dec_en_hi);
fwh_conf <<= 8;
fwh_conf |= pci_read_byte(dev, fwh_dec_en_lo);
for (i = 7; i >= 0; i--) {
int tmp = (fwh_conf >> (i + 0x8)) & 0x1;
msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
(0x1ff8 + i) * 0x80000,
(0x1ff0 + i) * 0x80000,
tmp ? "en" : "dis");
if ((tmp == 1) && contiguous) {
max_decode_fwh_decode = (8 - i) * 0x80000;
} else {
contiguous = 0;
}
}
for (i = 3; i >= 0; i--) {
int tmp = (fwh_conf >> i) & 0x1;
msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
(0xff4 + i) * 0x100000,
(0xff0 + i) * 0x100000,
tmp ? "en" : "dis");
if ((tmp == 1) && contiguous) {
max_decode_fwh_decode = (8 - i) * 0x100000;
} else {
contiguous = 0;
}
}
max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh);
return 0;
}
static int enable_flash_ich_fwh(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
{
int err;
/* Configure FWH IDSEL decoder maps. */
if ((err = enable_flash_ich_fwh_decode(dev, ich_generation)) != 0)
return err;
internal_buses_supported &= BUS_FWH;
return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl);
}
static int enable_flash_ich0(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_fwh(dev, CHIPSET_ICH, 0x4e);
}
static int enable_flash_ich2345(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_fwh(dev, CHIPSET_ICH2345, 0x4e);
}
static int enable_flash_ich6(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_fwh(dev, CHIPSET_ICH6, 0xdc);
}
static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8);
}
static enum chipbustype enable_flash_ich_report_gcs(
struct pci_dev *const dev, const enum ich_chipset ich_generation, const uint8_t *const rcrb)
{
uint32_t gcs;
const char *reg_name;
bool bild, top_swap;
switch (ich_generation) {
case CHIPSET_BAYTRAIL:
reg_name = "GCS";
gcs = mmio_readl(rcrb + 0);
bild = gcs & 1;
top_swap = (gcs & 2) >> 1;
break;
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
reg_name = "BIOS_SPI_BC";
gcs = pci_read_long(dev, 0xdc);
bild = (gcs >> 7) & 1;
top_swap = (gcs >> 4) & 1;
break;
default:
reg_name = "GCS";
gcs = mmio_readl(rcrb + 0x3410);
bild = gcs & 1;
top_swap = mmio_readb(rcrb + 0x3414) & 1;
break;
}
msg_pdbg("%s = 0x%x: ", reg_name, gcs);
msg_pdbg("BIOS Interface Lock-Down: %sabled, ", bild ? "en" : "dis");
struct boot_straps {
const char *name;
enum chipbustype bus;
};
static const struct boot_straps boot_straps_EP80579[] =
{ { "SPI", BUS_SPI },
{ "reserved", BUS_NONE },
{ "reserved", BUS_NONE },
{ "LPC", BUS_LPC | BUS_FWH } };
static const struct boot_straps boot_straps_ich7_nm10[] =
{ { "reserved", BUS_NONE },
{ "SPI", BUS_SPI },
{ "PCI", BUS_NONE },
{ "LPC", BUS_LPC | BUS_FWH } };
static const struct boot_straps boot_straps_tunnel_creek[] =
{ { "SPI", BUS_SPI },
{ "LPC", BUS_LPC | BUS_FWH } };
static const struct boot_straps boot_straps_ich8910[] =
{ { "SPI", BUS_SPI },
{ "SPI", BUS_SPI },
{ "PCI", BUS_NONE },
{ "LPC", BUS_LPC | BUS_FWH } };
static const struct boot_straps boot_straps_pch567[] =
{ { "LPC", BUS_LPC | BUS_FWH },
{ "reserved", BUS_NONE },
{ "PCI", BUS_NONE },
{ "SPI", BUS_SPI } };
static const struct boot_straps boot_straps_pch89_baytrail[] =
{ { "LPC", BUS_LPC | BUS_FWH },
{ "reserved", BUS_NONE },
{ "reserved", BUS_NONE },
{ "SPI", BUS_SPI } };
static const struct boot_straps boot_straps_pch8_lp[] =
{ { "SPI", BUS_SPI },
{ "LPC", BUS_LPC | BUS_FWH } };
static const struct boot_straps boot_straps_apl[] =
{ { "SPI", BUS_SPI },
{ "reserved", BUS_NONE } };
static const struct boot_straps boot_straps_unknown[] =
{ { "unknown", BUS_NONE },
{ "unknown", BUS_NONE },
{ "unknown", BUS_NONE },
{ "unknown", BUS_NONE } };
const struct boot_straps *boot_straps;
switch (ich_generation) {
case CHIPSET_ICH7:
/* EP80579 may need further changes, but this is the least
* intrusive way to get correct BOOT Strap printing without
* changing the rest of its code path). */
if (dev->device_id == 0x5031)
boot_straps = boot_straps_EP80579;
else
boot_straps = boot_straps_ich7_nm10;
break;
case CHIPSET_ICH8:
case CHIPSET_ICH9:
case CHIPSET_ICH10:
boot_straps = boot_straps_ich8910;
break;
case CHIPSET_TUNNEL_CREEK:
boot_straps = boot_straps_tunnel_creek;
break;
case CHIPSET_5_SERIES_IBEX_PEAK:
case CHIPSET_6_SERIES_COUGAR_POINT:
case CHIPSET_7_SERIES_PANTHER_POINT:
boot_straps = boot_straps_pch567;
break;
case CHIPSET_8_SERIES_LYNX_POINT:
case CHIPSET_9_SERIES_WILDCAT_POINT:
case CHIPSET_BAYTRAIL:
boot_straps = boot_straps_pch89_baytrail;
break;
case CHIPSET_8_SERIES_LYNX_POINT_LP:
case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
boot_straps = boot_straps_pch8_lp;
break;
case CHIPSET_APOLLO_LAKE:
boot_straps = boot_straps_apl;
break;
case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all
boot_straps = boot_straps_unknown;
break;
default:
msg_gerr("%s: unknown ICH generation. Please report!\n", __func__);
boot_straps = boot_straps_unknown;
break;
}
uint8_t bbs;
switch (ich_generation) {
case CHIPSET_TUNNEL_CREEK:
bbs = (gcs >> 1) & 0x1;
break;
case CHIPSET_8_SERIES_LYNX_POINT_LP:
case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
/* LP PCHs use a single bit for BBS */
bbs = (gcs >> 10) & 0x1;
break;
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
bbs = (gcs >> 6) & 0x1;
break;
default:
/* Other chipsets use two bits for BBS */
bbs = (gcs >> 10) & 0x3;
break;
}
msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, boot_straps[bbs].name);
/* Centerton has its TS bit in [GPE0BLK] + 0x30 while the exact location for Tunnel Creek is unknown. */
if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON)
msg_pdbg("Top Swap: %s\n", (top_swap) ? "enabled (A16(+) inverted)" : "not enabled");
return boot_straps[bbs].bus;
}
static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
{
/* Get physical address of Root Complex Register Block */
uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000;
msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra);
/* Map RCBA to virtual memory */
void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000);
if (rcrb == ERROR_PTR)
return ERROR_FATAL;
const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
/* Handle FWH-related parameters and initialization */
int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl);
if (ret_fwh == ERROR_FATAL)
return ret_fwh;
/*
* It seems that the ICH7 does not support SPI and LPC chips at the same time. When booted
* from LPC, the SCIP bit will never clear, which causes long delays and many error messages.
* To avoid this, we will not enable SPI on ICH7 when the southbridge is strapped to LPC.
*/
if (ich_generation == CHIPSET_ICH7 && (boot_buses & BUS_LPC))
return 0;
/* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */
uint16_t spibar_offset;
switch (ich_generation) {
case CHIPSET_BAYTRAIL:
case CHIPSET_ICH_UNKNOWN:
return ERROR_FATAL;
case CHIPSET_ICH7:
case CHIPSET_ICH8:
case CHIPSET_TUNNEL_CREEK:
case CHIPSET_CENTERTON:
spibar_offset = 0x3020;
break;
case CHIPSET_ICH9:
default: /* Future version might behave the same */
spibar_offset = 0x3800;
break;
}
msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " + 0x%04x\n", PRIxPTR_WIDTH, (uintptr_t)rcrb, spibar_offset);
void *spibar = rcrb + spibar_offset;
/* This adds BUS_SPI */
int ret_spi = ich_init_spi(spibar, ich_generation);
if (ret_spi == ERROR_FATAL)
return ret_spi;
if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi))
return ERROR_NONFATAL;
/* Suppress unknown laptop warning if we booted from SPI. */
if (boot_buses & BUS_SPI)
laptop_ok = 1;
return 0;
}
static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_TUNNEL_CREEK, 0xd8);
}
static int enable_flash_s12x0(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_CENTERTON, 0xd8);
}
static int enable_flash_ich7(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_ICH7, 0xdc);
}
static int enable_flash_ich8(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_ICH8, 0xdc);
}
static int enable_flash_ich9(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_ICH9, 0xdc);
}
static int enable_flash_ich10(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_ICH10, 0xdc);
}
/* Ibex Peak aka. 5 series & 3400 series */
static int enable_flash_pch5(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc);
}
/* Cougar Point aka. 6 series & c200 series */
static int enable_flash_pch6(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc);
}
/* Panther Point aka. 7 series */
static int enable_flash_pch7(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc);
}
/* Lynx Point aka. 8 series */
static int enable_flash_pch8(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc);
}
/* Lynx Point LP aka. 8 series low-power */
static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc);
}
/* Wellsburg (for Haswell-EP Xeons) */
static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc);
}
/* Wildcat Point */
static int enable_flash_pch9(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc);
}
/* Wildcat Point LP */
static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc);
}
/* Sunrise Point */
static int enable_flash_pch100_shutdown(void *const pci_acc)
{
pci_cleanup(pci_acc);
return 0;
}
static int enable_flash_pch100_or_c620(
struct pci_dev *const dev, const char *const name,
const int slot, const int func, const enum ich_chipset pch_generation)
{
int ret = ERROR_FATAL;
/*
* The SPI PCI device is usually hidden (by hiding PCI vendor
* and device IDs). So we need a PCI access method that works
* even when the OS doesn't know the PCI device. We can't use
* this method globally since it would bring along other con-
* straints (e.g. on PCI domains, extended PCIe config space).
*/
struct pci_access *const pci_acc = pci_alloc();
struct pci_access *const saved_pacc = pacc;
if (!pci_acc) {
msg_perr("Can't allocate PCI accessor.\n");
return ret;
}
pci_acc->method = PCI_ACCESS_I386_TYPE1;
pci_init(pci_acc);
register_shutdown(enable_flash_pch100_shutdown, pci_acc);
struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, slot, func);
if (!spi_dev) {
msg_perr("Can't allocate PCI device.\n");
return ret;
}
/* Modify pacc so the rpci_write can register the undo callback with a
* device using the correct pci_access */
pacc = pci_acc;
const enum chipbustype boot_buses = enable_flash_ich_report_gcs(spi_dev, pch_generation, NULL);
const int ret_bc = enable_flash_ich_bios_cntl_config_space(spi_dev, pch_generation, 0xdc);
if (ret_bc == ERROR_FATAL)
goto _freepci_ret;
const uint32_t phys_spibar = pci_read_long(spi_dev, PCI_BASE_ADDRESS_0) & 0xfffff000;
void *const spibar = rphysmap("SPIBAR", phys_spibar, 0x1000);
if (spibar == ERROR_PTR)
goto _freepci_ret;
msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " (phys = 0x%08x)\n", PRIxPTR_WIDTH, (uintptr_t)spibar, phys_spibar);
/* This adds BUS_SPI */
const int ret_spi = ich_init_spi(spibar, pch_generation);
if (ret_spi != ERROR_FATAL) {
if (ret_bc || ret_spi)
ret = ERROR_NONFATAL;
else
ret = 0;
}
/* Suppress unknown laptop warning if we booted from SPI. */
if (!ret && (boot_buses & BUS_SPI))
laptop_ok = 1;
_freepci_ret:
pci_free_dev(spi_dev);
pacc = saved_pacc;
return ret;
}
static int enable_flash_pch100(struct pci_dev *const dev, const char *const name)
{
return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_100_SERIES_SUNRISE_POINT);
}
static int enable_flash_c620(struct pci_dev *const dev, const char *const name)
{
return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG);
}
static int enable_flash_pch300(struct pci_dev *const dev, const char *const name)
{
return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT);
}
static int enable_flash_apl(struct pci_dev *const dev, const char *const name)
{
return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE);
}
/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
* These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
*
* Differences include:
* - RCBA at LPC config 0xF0 too but mapped range is only 4 B long instead of 16 kB.
* - GCS at [RCRB] + 0 (instead of [RCRB] + 0x3410).
* - TS (Top Swap) in GCS (instead of [RCRB] + 0x3414).
* - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800).
* - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC).
*/
static int enable_flash_silvermont(struct pci_dev *dev, const char *name)
{
enum ich_chipset ich_generation = CHIPSET_BAYTRAIL;
/* Get physical address of Root Complex Register Block */
uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00;
msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba);
/* Handle GCS (in RCRB) */
void *rcrb = physmap("BYT RCRB", rcba, 4);
const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
physunmap(rcrb, 4);
/* Handle fwh_idsel parameter */
int ret_fwh = enable_flash_ich_fwh_decode(dev, ich_generation);
if (ret_fwh == ERROR_FATAL)
return ret_fwh;
internal_buses_supported &= BUS_FWH;