- Synopsis
-
Extract and zero-extend bits.
- Mnemonic
-
th.extu rd, rs1, imm1, imm2
- Encoding
{reg:[
{ bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] },
{ bits: 5, name: 'rd' },
{ bits: 3, name: 0x3, attr: ['Arithmetic'] },
{ bits: 5, name: 'rs1' },
{ bits: 6, name: 'imm2' },
{ bits: 6, name: 'imm1' },
]}
- Description
-
This operation extract the bits imm1..imm2 from register rs1, zero-extends the value, and stores the result in rd.
- Operation
reg[rd] := zero_extend(reg[rs1][imm1:imm2])- Permission
-
This instruction can be executed in all privilege levels.
- Exceptions
-
This instruction does not trigger any exceptions.
- Included in
| Extension |
|---|
XTheadBb ([xtheadbb]) |