- Synopsis
-
Invalidate all I-cache on all harts
- Mnemonic
-
th.icache.ialls
- Encoding
{reg:[ { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, { bits: 5, name: 0x0 }, { bits: 3, name: 0x0, attr: ['CMO'] }, { bits: 5, name: 0x0 }, { bits: 5, name: 0x11, attr: ['iache.ialls'] }, { bits: 7, name: 0x00 }, ]}
- Description
-
This instruction invalidates all cache lines of the instruction cache on all harts (using broadcasting). Dirty cache lines will not be written back to the next-level storage.
- Operation
if (priv_level == U)
{
<raise illegal instruction exception>
}
<invalidate all instruction cache lines on all harts>
- Permission
-
This instruction can be executed in all privilege levels higher than
U
mode. Attempts to execute this instruction inU
mode raise an illegal instruction exception. - Exceptions
-
This instruction does not trigger any exceptions.
- Included in
Extension | HW requirements |
---|---|
XTheadCmo ([xtheadcmo]) |
I-cache |