flrw.adoc

th.flrw

Synopsis

Load indexed single-precision floating point value.

Mnemonic

th.flrw rd, rs1, rs2, imm2

Encoding

{reg:[
    { bits:  7, name: 0xb, attr: ['custom-0, 32 bit'] },
    { bits:  5, name: 'rd' },
    { bits:  3, name: 0x6, attr: ['FMem-Load'] },
    { bits:  5, name: 'rs1' },
    { bits:  5, name: 'rs2' },
    { bits:  2, name: 'imm2' },
    { bits:  5, name: 0x08 },
]}

Description

This instruction loads a single-precision floating point value into FP register rd from the address rs1 + (rs2 << imm2).

If the D extension is available the value will be one-extended.

Operation

addr := rs1 + (rs2 << imm2)
rd := one_extend(fmem[addr+3:addr])

Permission

This instruction can be executed in all privilege levels.

Exceptions

This instruction triggers the same exceptions that two corresponding FLW instructions would trigger.

Included in

Extension
XTheadFMemIdx ([xtheadfmemidx])