sfence_vmas.adoc

th.sfence.vmas

Synopsis

Invalidate TLB (page table cache) on all harts via broadcasting.

Mnemonic

th.sfence.vmas rs1, rs2

Encoding

{reg:[
    { bits:  7, name: 0xb, attr: ['custom-0, 32 bit'] },
    { bits:  5, name: 0x0 },
    { bits:  3, name: 0x0, attr: ['CMO'] },
    { bits:  5, name: 'rs1', attr: ['VA'] },
    { bits:  5, name: 'rs2', attr: ['ASID'] },
    { bits:  7, name: 0x02 },
]}

Description

This instruction invalidates the TLB (page table cache) on all harts via broadcasting. The register rs1 holds the virtual address (VA) and rs2 holds the address space identifier (ASID) of the TLB entry that will be invalidated on all harts via broadcasting.

An operand that is zero is interpreted as match-all. E.g. if rs2 is zero, then all TLB entries that match the VA in rs1 are invalidated on all harts via broadcasting. Consequently, if both operands, rs1 and rs2, are zero, then all TLB entries are invalidated on all harts via broadcasting.

Operation

if (priv_level == U)
{
  <raise illegal instruction exception>
}

if _rs1_ != 0
{
  va := _rs1_
}
else
{
  va := _MATCH_ALL_VA_
}

if _rs2_ != 0
{
  asid := _rs2_
}
else
{
  asid := _MATCH_ALL_ASID_
}

msg := encode_invalidate_tlb(va, asid)
broadcast_to_all_harts(msg)

Permission

This instruction can be executed in all privilege levels higher than U mode. Attempts to execute this instruction in U mode raise an illegal instruction exception.

Exceptions

This instruction does not trigger any exceptions.

Included in

Extension
XTheadSync ([xtheasync])