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.gitignore
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*.DS_Store
*.log
*.wdf
*.wpc
*.xml
*.jou
*.str
*.lpr
*.rst
*xsim.mem
*.dcp
*.tcl
*.vds
*.pb
*.rpt
*.js
*.sh
*.bat
*.wdb
*.prj
*.ini
*.obj
*.c
*.info
*.html
*.rlx
*.svtype
*.rtti
*.type
*.xdbg
*.dbg
*.reloc
*.exe
*.sdb
*.xpr
*.wcfg
*.vdi
*.rpx
*.wdm
*.icloud
*.data
*.map
*.rtd
*.out
*.0
*.0_temp
*.super
*.gnd
*.edf
verilog/lab.runs/synth_1/.Xil/Datapath_propImpl.xdc
verilog/lab.runs/synth_1/__synthesis_is_complete__
verilog/lab.sim/sim_1/behav/xsim/glbl.v
verilog/lab.sim/sim_1/synth/func/xsim/Datapath_tb_func_synth.v
verilog/lab_part2.sim/sim_1/synth/func/xsim/Datapath_tb_func_synth.v
*htr.txt
*Compile_Options.txt
*TempBreakPointFile.txt
*tight_setup_hold_pins.txt
verilog/lab.ip_user_files/mem_init_files/Data_memory.mem
verilog/lab.ip_user_files/mem_init_files/Instruction_mem.mem
verilog/lab.ip_user_files/mem_init_files/Instruction_memory.mem
verilog/lab.sim/sim_1/behav/xsim/Data_memory.mem
verilog/lab.sim/sim_1/behav/xsim/Instruction_mem.mem
verilog/lab.sim/sim_1/behav/xsim/Instruction_memory.mem
verilog/lab.ip_user_files/mem_init_files/empty_dm.mem
verilog/lab.ip_user_files/mem_init_files/test_mips9_18.mem
verilog/lab.ip_user_files/mem_init_files/test_sp_im.mem
verilog/lab.ip_user_files/mem_init_files/vbsme_im.mem
verilog/lab.ip_user_files/mem_init_files/vbsme_dm.mem
verilog/lab.sim/sim_1/behav/xsim/empty_dm.mem
verilog/lab.sim/sim_1/behav/xsim/test_sp_im.mem
verilog/lab.sim/sim_1/behav/xsim/test_mips9_18.mem
verilog/lab.sim/sim_1/behav/xsim/vbsme_dm.mem
verilog/lab.sim/sim_1/behav/xsim/vbsme_im.mem
verilog/lab.ip_user_files/mem_init_files/test_frame.mem
verilog/lab.ip_user_files/mem_init_files/test_vbsme_frame.mem
verilog/lab.sim/sim_1/behav/xsim/test_frame.mem
verilog/lab.sim/sim_1/behav/xsim/test_vbsme_frame.mem
verilog/lab.ip_user_files/mem_init_files/test_bp.mem
verilog/lab.sim/sim_1/behav/xsim/test_bp.mem
verilog/lab.sim/sim_1/synth/func/xsim/vbsme_im.mem
verilog/lab.sim/sim_1/synth/func/xsim/vbsme_dm.mem
verilog/lab.sim/sim_1/synth/func/xsim/test_vbsme_frame.mem
verilog/lab.sim/sim_1/synth/func/xsim/test_sp_im.mem
verilog/lab.sim/sim_1/synth/func/xsim/test_mips9_18.mem
verilog/lab.sim/sim_1/synth/func/xsim/test_frame.mem
verilog/lab.sim/sim_1/synth/func/xsim/test_bp.mem
verilog/lab.sim/sim_1/synth/func/xsim/Instruction_memory.mem
verilog/lab.sim/sim_1/synth/func/xsim/empty_dm.mem
verilog/lab.sim/sim_1/synth/func/xsim/Data_memory.mem
verilog/lab.sim/sim_1/impl/func/xsim/vbsme_im.mem
verilog/lab.sim/sim_1/impl/func/xsim/vbsme_dm.mem
verilog/lab.sim/sim_1/impl/func/xsim/test_vbsme_frame.mem
verilog/lab.sim/sim_1/impl/func/xsim/test_sp_im.mem
verilog/lab.sim/sim_1/impl/func/xsim/test_mips9_18.mem
verilog/lab.sim/sim_1/impl/func/xsim/test_frame.mem
verilog/lab.sim/sim_1/impl/func/xsim/test_bp.mem
verilog/lab.sim/sim_1/impl/func/xsim/Instruction_memory.mem
verilog/lab.sim/sim_1/impl/func/xsim/empty_dm.mem
verilog/lab.sim/sim_1/impl/func/xsim/Datapath_tb_func_impl.v
verilog/lab.sim/sim_1/impl/func/xsim/Data_memory.mem
verilog/project_1/project_1.ip_user_files/mem_init_files/Data_memory.mem
verilog/project_1/project_1.ip_user_files/mem_init_files/empty_dm.mem
verilog/project_1/project_1.ip_user_files/mem_init_files/Instruction_memory.mem
verilog/project_1/project_1.ip_user_files/mem_init_files/test_bp.mem
verilog/project_1/project_1.ip_user_files/mem_init_files/test_frame.mem
verilog/project_1/project_1.ip_user_files/mem_init_files/test_mips9_18.mem
verilog/project_1/project_1.ip_user_files/mem_init_files/test_sp_im.mem
verilog/project_1/project_1.ip_user_files/mem_init_files/test_vbsme_frame.mem
verilog/project_1/project_1.ip_user_files/mem_init_files/vbsme_dm.mem
verilog/project_1/project_1.ip_user_files/mem_init_files/vbsme_im.mem
verilog/project_1/project_1.sim/sim_1/behav/xsim/Data_memory.mem
verilog/project_1/project_1.runs/synth_1/__synthesis_is_complete__
verilog/project_1/project_1.sim/sim_1/behav/xsim/empty_dm.mem
verilog/project_1/project_1.sim/sim_1/behav/xsim/glbl.v
verilog/project_1/project_1.sim/sim_1/behav/xsim/Instruction_memory.mem
verilog/project_1/project_1.sim/sim_1/behav/xsim/test_bp.mem
verilog/project_1/project_1.sim/sim_1/behav/xsim/test_mips9_18.mem
verilog/project_1/project_1.sim/sim_1/behav/xsim/test_sp_im.mem
verilog/project_1/project_1.sim/sim_1/behav/xsim/test_vbsme_frame.mem
verilog/project_1/project_1.sim/sim_1/behav/xsim/vbsme_dm.mem
verilog/project_1/project_1.sim/sim_1/behav/xsim/vbsme_im.mem
verilog/project_1/project_1.sim/sim_1/behav/xsim/test_frame.mem
verilog/lab.runs/synth_1/__synthesis_is_running__
verilog/project_1/project_1.runs/synth_1/.Xil/Datapath_propImpl.xdc
verilog/lab.srcs/sources_1/new/Data_memory.mem