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computer.qsf
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computer.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 14:46:20 April 30, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# computer_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY computer
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:46:20 APRIL 30, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name BOARD "DE1-SoC Board"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE pipe_regs/mem_wb.v
set_global_assignment -name VERILOG_FILE pipe_regs/if_id.v
set_global_assignment -name VERILOG_FILE pipe_regs/id_ex.v
set_global_assignment -name VERILOG_FILE pipe_regs/ex_mem.v
set_global_assignment -name VERILOG_FILE hazard_detection.v
set_global_assignment -name VERILOG_FILE forwarding.v
set_global_assignment -name QIP_FILE memory/rom.qip
set_global_assignment -name QIP_FILE memory/ram.qip
set_global_assignment -name VERILOG_FILE memory/inst_mem.v
set_global_assignment -name VERILOG_FILE memory/data_mem.v
set_global_assignment -name VERILOG_FILE io_control/seven_seg.v
set_global_assignment -name VERILOG_FILE io_control/output_control.v
set_global_assignment -name VERILOG_FILE io_control/multiplier.v
set_global_assignment -name VERILOG_FILE io_control/input_control.v
set_global_assignment -name VERILOG_FILE components/registers.v
set_global_assignment -name VERILOG_FILE components/extender.v
set_global_assignment -name VERILOG_FILE components/dff32.v
set_global_assignment -name VERILOG_FILE components/alu_control.v
set_global_assignment -name VERILOG_FILE components/alu.v
set_global_assignment -name VERILOG_FILE cpu.v
set_global_assignment -name VERILOG_FILE control.v
set_global_assignment -name VERILOG_FILE computer.v
set_location_assignment PIN_AF14 -to mem_clock
set_location_assignment PIN_AE12 -to input1[4]
set_location_assignment PIN_AD10 -to input1[3]
set_location_assignment PIN_AC9 -to input1[2]
set_location_assignment PIN_AE11 -to input1[1]
set_location_assignment PIN_AD12 -to input1[0]
set_location_assignment PIN_AD11 -to input2[4]
set_location_assignment PIN_AF10 -to input2[3]
set_location_assignment PIN_AF9 -to input2[2]
set_location_assignment PIN_AC12 -to input2[1]
set_location_assignment PIN_AB12 -to input2[0]
set_location_assignment PIN_AA25 -to output1[13]
set_location_assignment PIN_AA26 -to output1[12]
set_location_assignment PIN_AB26 -to output1[11]
set_location_assignment PIN_AB27 -to output1[10]
set_location_assignment PIN_Y27 -to output1[9]
set_location_assignment PIN_AA28 -to output1[8]
set_location_assignment PIN_V25 -to output1[7]
set_location_assignment PIN_W25 -to output1[6]
set_location_assignment PIN_V23 -to output1[5]
set_location_assignment PIN_W24 -to output1[4]
set_location_assignment PIN_W22 -to output1[3]
set_location_assignment PIN_Y24 -to output1[2]
set_location_assignment PIN_Y23 -to output1[1]
set_location_assignment PIN_AA24 -to output1[0]
set_location_assignment PIN_AB22 -to output2[13]
set_location_assignment PIN_AB25 -to output2[12]
set_location_assignment PIN_AB28 -to output2[11]
set_location_assignment PIN_AC25 -to output2[10]
set_location_assignment PIN_AD25 -to output2[9]
set_location_assignment PIN_AC27 -to output2[8]
set_location_assignment PIN_AD26 -to output2[7]
set_location_assignment PIN_AC30 -to output2[6]
set_location_assignment PIN_AC29 -to output2[5]
set_location_assignment PIN_AD30 -to output2[4]
set_location_assignment PIN_AC28 -to output2[3]
set_location_assignment PIN_AD29 -to output2[2]
set_location_assignment PIN_AE29 -to output2[1]
set_location_assignment PIN_AB23 -to output2[0]
set_location_assignment PIN_AD27 -to output3[13]
set_location_assignment PIN_AF30 -to output3[12]
set_location_assignment PIN_AF29 -to output3[11]
set_location_assignment PIN_AG30 -to output3[10]
set_location_assignment PIN_AH30 -to output3[9]
set_location_assignment PIN_AH29 -to output3[8]
set_location_assignment PIN_AJ29 -to output3[7]
set_location_assignment PIN_AH28 -to output3[6]
set_location_assignment PIN_AG28 -to output3[5]
set_location_assignment PIN_AF28 -to output3[4]
set_location_assignment PIN_AG27 -to output3[3]
set_location_assignment PIN_AE28 -to output3[2]
set_location_assignment PIN_AE27 -to output3[1]
set_location_assignment PIN_AE26 -to output3[0]
set_location_assignment PIN_V16 -to overflow
set_location_assignment PIN_AA14 -to reset_bar
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top