README-VHDL.md

This is a most popular repository list for VHDL sorted by number of stars

STARS	FORKS	ISSUES	LAST COMMIT	NAME/PLACE	DESCRIPTION
1670	298	253	20 hours ago	ghdl/1	VHDL 2008/93/87 simulator
1259	485	9	a month ago	aws-fpga/2	Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
1132	544	20	9 years ago	Open-Source-FPGA-Bitcoin-Miner/3	A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
1095	76	22	13 days ago	Time-Appliance-Project/4	Develop an end-to-end hypothetical reference model, network architectures, performance objectives and the methods to distribute, operate, monitor time synchronization within data center and much more...
892	122	12	6 hours ago	neorv32/5	🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
771	39	1	6 years ago	FPGA_Webserver/6	A work-in-progress for what is to be a software-free web server for static content.
765	231	25	5 days ago	chipwhisperer/7	ChipWhisperer - the complete open-source toolchain for side-channel power analysis and glitching attacks
562	133	7	7 years ago	gplgpu/8	GPL v3 2D/3D graphics engine in verilog
552	209	184	a month ago	vunit/9	VUnit is a unit testing framework for VHDL/SystemVerilog
490	74	20	7 months ago	gcvideo/10	GameCube Digital AV converter
432	90	31	2 years ago	PoC/11	IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
415	62	13	2 hours ago	nvc/12	VHDL compiler and simulator
404	132	11	3 years ago	dsi-shield/13	Arduino MIPI DSI Shield
402	55	12	a month ago	hal/14	HAL – The Hardware Analyzer
393	177	6	4 years ago	parallella-hw/15	Parallella board design files
385	143	3	5 years ago	parallella-examples/16	Community created parallella projects
356	94	23	3 days ago	f32c/17	A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
303	89	4	3 years ago	CSI2Rx/18	Open Source 4k CSI-2 Rx core for Xilinx FPGAs
296	36	7	2 years ago	opl3_fpga/19	Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
293	42	6	10 months ago	bladeRF-wiphy/20	bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
283	22	0	5 months ago	forth-cpu/21	A Forth CPU and System on a Chip, based on the J1, written in VHDL
256	69	27	2 months ago	UVVM/22	UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
240	29	23	a month ago	ghdl-yosys-plugin/23	VHDL synthesis (based on ghdl)
237	41	14	11 days ago	a2i/24	None
234	38	2	6 years ago	FPGA_DisplayPort/25	An implementation of DisplayPort protocol for FPGAs
228	47	1	3 years ago	tinyTPU/26	Implementation of a Tensor Processing Unit for embedded systems and the IoT.
225	67	15	3 months ago	ThunderScope/27	ThunderScope GitHub Repo
219	32	4	1 year, 5 months ago	potato/28	A simple RISC-V processor for use in FPGA designs.
214	60	7	4 years ago	hardh264/29	A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
203	33	13	1 year, 5 months ago	C64-Video-Enhancement/30	Component video modification for the C64 8-bit computer
197	60	3	1 year, 4 months ago	ZYNQ7010-7020_AD9363/31	基于ZYNQ+AD9363的开源SDR硬件
193	13	0	8 months ago	PlayStation_MiSTer/32	PlayStation for MiSTer FPGA
192	28	14	5 months ago	fletcher/33	Fletcher: A framework to integrate FPGA accelerators with Apache Arrow
190	67	199	2 months ago	mega65-core/34	MEGA65 FPGA core
184	22	4	8 months ago	neo430/35	💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
177	47	20	11 days ago	OSVVM/36	OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
174	64	0	5 years ago	VHDL_Lib/37	Library of VHDL components that are useful in larger designs.
168	51	1	4 years ago	vna2/38	Second version of homemade 30 MHz - 6 GHz VNA
168	37	4	7 days ago	surf/39	A huge VHDL library for FPGA development
167	32	4	a month ago	OpenXenium/40	OpenXenium - Open Source Xenium Modchip CPLD replacement project for the Original Xbox
160	35	32	1 year, 4 months ago	rust_hdl/41	None
159	74	4	2 years ago	fmcw3/42	Two RX-channel 6 GHz FMCW radar design files
157	41	0	2 years ago	XJTU-Tripler/43	XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.
147	17	0	6 years ago	space-invaders-vhdl/44	Space Invaders game implemented with VHDL
144	82	15	25 days ago	Cosmos-plus-OpenSSD/45	Cosmos OpenSSD + Hardware and Software source distribution
137	51	10	3 years ago	Artix-7-HDMI-processing/46	Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA
136	63	47	6 hours ago	SNES_MiSTer/47	SNES for MiSTer
135	13	0	7 months ago	hdl4fpga/48	VHDL library 4 FPGAs
133	28	1	7 years ago	zpu/49	The Zylin ZPU
130	12	0	1 year, 11 months ago	RPU/50	Basic RISC-V CPU implementation in VHDL.
125	4	5	2 years ago	FPGBA/51	GBA on FPGA
130	36	8	4 years ago	vhdl-extras/52	Flexible VHDL library
120	106	2	1 year, 5 months ago	Digital-Design-Lab/53	None
120	19	7	a month ago	gbaHD/54	An open-source GBA consolizer.
118	65	1	6 months ago	spi-master/55	SPI Master for FPGA - VHDL and Verilog
116	24	0	6 years ago	neppielight/56	FPGA-based HDMI ambient lighting
116	15	0	4 months ago	nexys4ddr/57	Various projects for the Nexys4DDR board from Digilent
114	50	0	5 years ago	ethernet_mac/58	Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
112	44	61	3 months ago	axiom-firmware/59	AXIOM firmware (linux image, gateware and software tools)
111	32	47	6 hours ago	PSX_MiSTer/60	PSX for MiSTer
108	33	8	11 days ago	GBA_MiSTer/61	GBA for MiSTer
108	69	16	a month ago	patmos/62	Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
116	12	1	6 years ago	TPU/63	TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.
103	12	5	7 months ago	Digital-IDE/64	在vscode上的数字设计开发插件
100	27	0	6 years ago	HDMI2USB-jahanzeb-firmware/65	Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
96	25	0	1 year, 3 months ago	spi-fpga/66	SPI master and SPI slave for FPGA written in VHDL
95	7	0	5 months ago	captouch/67	👇 Add capacitive touch buttons to any FPGA!
94	15	16	19 hours ago	w11/68	PDP-11/70 CPU core and SoC
93	11	2	3 years ago	freezing-spice/69	A pipelined RISCV implementation in VHDL
92	27	13	6 months ago	bladeRF-adsb/70	bladeRF ADS-B hardware decoder
92	26	7	1 year, 10 months ago	sdram-fpga/71	A FPGA core for a simple SDRAM controller.
92	13	0	2 years ago	greta/72	GRETA expansion board for the Amiga 500 computer with Fast RAM, microSD mass storage and Ethernet controller, powered by FPGA technology.
91	19	8	6 months ago	AtomBusMon/73	This project is an open-source In-Circuit Emulator for the 6502, 65C02, Z80, 6809 and 6809E 8-bit processors. See:
88	23	0	1 year, 3 months ago	PYNQ-DL/74	Xilinx Deep Learning IP
89	39	0	4 years ago	Simon_Speck_Ciphers/75	Implementations of the Simon and Speck Block Ciphers
93	56	2	2 years ago	Hackster/76	Files used with hackster examples
90	37	1	9 years ago	ZynqBTC/77	A Bitcoin miner for the Zynq chip utilizing the Zedboard.
85	41	1	6 years ago	hard-cv/78	A repository of IPs for hardware computer vision (FPGA)
83	21	0	4 months ago	FPGA-proj/79	FPGA project
87	24	0	5 years ago	fpga-multi-effect/80	FPGA-based Multi-Effects system for the electric guitar
83	29	5	2 months ago	zxuno/81	All the files for ZX-Uno project repository
81	52	1	4 years ago	ZPUino-HDL/82	ZPUino HDL implementation
76	23	0	1 year, 9 months ago	Image-Processing/83	Image Processing Toolbox in Verilog using Basys3 FPGA
76	12	5	1 year, 1 day ago	deniser/84	Amiga Denise chip replacement
76	12	1	1 year, 10 months ago	Rudi-RV32I/85	A rudimental RISCV CPU supporting RV32I instructions, in VHDL
75	14	0	4 years ago	vpcie/86	implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture
75	36	0	2 months ago	Learn-FPGA-Programming/87	Learn FPGA Programming, published by Packt
74	147	3	4 years ago	Basys3/88	None
72	4	0	3 months ago	Gauntlet_FPGA/89	FPGA implementation of Atari's Gauntlet arcade game
70	15	3	5 months ago	leros/90	A Tiny Processor Core
69	19	0	4 years ago	RFToolSDR/91	AD9361 based USB3 SDR
68	29	3	2 years ago	IIoT-EDDP/92	The repository contains the design database and documentation for Electric Drives Demonstration Platform
68	28	0	8 years ago	FPGA-Oscilloscope/93	Design, Documentation, Schematic, Board, Code files for the FPGA Oscilloscope project using an Altera Cyclone III FPGA.
67	7	1	4 years ago	q27/94	27-Queens Puzzle: Massively Parellel Enumeration and Solution Counting
67	27	0	3 months ago	apis_anatolia/95	"Apis Anatolia" YouTube kanalında yayınlanan VHDL ve FPGA dersleri ile ilgili kodları içermektedir.
68	2	1	8 years ago	yafc/96	Yet Another Forth Core...
64	51	9	6 years ago	logi-projects/97	None
64	5	0	1 year, 7 months ago	bit-serial/98	A bit-serial CPU written in VHDL, with a simulator written in C.
63	43	3	a month ago	TurboGrafx16_MiSTer/99	TurboGrafx-16 CD / PC Engine CD for MiSTer
63	16	4	3 months ago	phywhispererusb/100	PhyWhisperer-USB: Hardware USB Trigger
62	26	5	2 years ago	haddoc2/101	Caffe to VHDL
65	13	1	3 years ago	CoPro6502/102	FPGA implementations of BBC Micro Co Processors (65C02, Z80, 6809, 68000, x86, ARM2, PDP-11, 32016)
61	6	1	22 days ago	SonicSurface/103	Generating Airborne Ultrasonic Amplitude Patterns Using an Open Hardware Phased Array
61	22	2	8 years ago	Arduino-Soft-Core/104	None
61	82	0	2 years ago	FPGA/105	FPGA
61	9	3	5 days ago	jt51/106	YM2151 clone in verilog. FPGA proven.
60	11	6	3 years ago	ReonV/107	ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.
60	8	1	2 years ago	1bitSDR/108	Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom
59	13	2	1 year, 6 months ago	fpga-fft/109	A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
59	12	8	7 months ago	JSON-for-VHDL/110	A JSON library implemented in VHDL.
59	8	0	3 days ago	neoTRNG/111	🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA.
58	11	2	5 months ago	scaffold/112	Donjon hardware tool for circuits security evaluation
58	41	3	5 years ago	sublime-vhdl/113	VHDL Package for Sublime Text
57	5	0	8 months ago	fpga_puf/114	🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
56	21	0	8 years ago	FpgasNowWhat/115	Source for the "FPGAs?! Now What?" Book
59	32	1	4 years ago	SiaFpgaMiner/116	VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin
61	49	0	6 years ago	ODriveFPGA/117	High performance motor control
55	15	4	1 year, 2 months ago	A-VideoBoard/118	FPGA board to create a component video signal for vintage computers.
61	22	1	1 year, 4 months ago	uart-for-fpga/119	Simple UART controller for FPGA written in VHDL
56	32	1	6 years ago	uart/120	A VHDL UART for communicating over a serial link with an FPGA
55	37	0	a month ago	rfsoc_qpsk/121	PYNQ example of using the RFSoC as a QPSK transceiver.
53	19	14	6 months ago	X68000_MiSTer/122	Sharp X68000 for MiSTer
52	29	0	9 years ago	VHDL/123	VHDL Samples
52	16	1	3 months ago	dvb_fpga/124	RTL implementation of components for DVB-S2
51	29	1	2 years ago	fpgagen/125	SEGA Genesis/Megadrive core, running on a Altera/Terasic DE1 board.
51	13	0	2 years ago	Nexys4DDR-ARM-M3-Plate-Recognition/126	车牌识别,FPGA,2019全国大学生集成电路创新创业大赛
51	9	0	1 year, 21 days ago	R3DUX/127	None
51	31	0	a day ago	BIT-CS-Learning/128	保存一下我自己整理的北理工计科的学习资料，欢迎分享资源
53	17	5	11 months ago	AppleIISd/129	SD card based ProFile replacement for IIe
50	17	0	a month ago	intfftk/130	Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
50	11	1	1 year, 10 months ago	fos/131	FOS - FPGA Operating System
50	28	1	2 years ago	FPGA-I2C-Minion/132	A simple I2C minion in VHDL
49	3	1	8 days ago	psl_with_ghdl/133	Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
49	11	4	2 years ago	FlowBlaze/134	FlowBlaze: Stateful Packet Processing in Hardware
49	1	0	1 year, 3 months ago	fpga-dns-adtm/135	High-performance/Low-Latency FPGA-based DNS attack detector and threat mitigator
48	2	0	1 year, 6 months ago	MandelbrotInVHDL/136	What better way to learn VHDL, than to do some fractals?
47	9	6	30 days ago	AXI4/137	AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
49	11	0	5 years ago	FPGA-radio/138	Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC
48	13	0	2 years ago	flexray-interceptor/139	FPGA project to man-in-the-middle attack Flexray
47	21	3	24 days ago	Mist_FPGA/140	None
46	14	3	8 years ago	libv/141	Useful set of library functions for VHDL
47	35	1	2 years ago	LimeSDR-Mini_GW/142	LimeSDR-Mini board FPGA project
46	2	6	a month ago	mc1/143	A computer (FPGA SoC) based on the MRISC32-A1 CPU
47	30	0	4 years ago	AX7010/144	None
46	30	7	6 years ago	Papilio-Arcade/145	A collection of arcade games targeted for Papilio FPGA boards. Many of the games are from FPGAArcade.com.
45	23	2	4 years ago	Vivado-KMeans/146	Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs
45	74	5	2 months ago	mlib_devel/147	None
45	18	0	6 years ago	flearadio/148	Digital FM Radio Receiver for FPGA
44	22	0	4 years ago	jTDC/149	FPGA based 30ps RMS TDCs
44	19	20	4 years ago	HDMI2USB-numato-opsis-sample-code/150	Example code for the Numato Opsis board, the first HDMI2USB production board.
43	21	0	10 days ago	MultiComp/151	Spins of Grant Searle's MultiComp project on various hardware
43	8	0	14 days ago	satcat5/152	SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
42	9	0	2 months ago	SneakySnake/153	SneakySnake:snake: is the first and the only pre-alignment filtering algorithm that works efficiently and fast on modern CPU, FPGA, and GPU architectures. It greatly (by more than two orders of magnitude) expedites sequence alignment calculation for both short and long reads. Described in the Bioinformatics (2020) by Alser et al. https://arxiv.org/abs/1910.09020.
41	16	1	4 years ago	FGPU/154	FGPU is a soft GPU architecture general purpose computing
41	17	1	a month ago	rfsoc_sam/155	RFSoC Spectrum Analyser Module on PYNQ.
41	44	21	11 days ago	SMS_MiSTer/156	Sega Master System for MiSTer
40	16	3	5 years ago	fphdl/157	VHDL-2008 Support Library
40	18	0	7 years ago	MIPS-processor/158	MIPS processor designed in VHDL
39	22	0	2 years ago	tinycrypt/159	Crypto stuff. Don't use.
39	26	3	21 days ago	Zybo-Z7-20-pcam-5c/160	None
39	11	0	1 year, 8 months ago	Digital-Hardware-Modelling/161	Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
39	2	1	1 year, 1 month ago	neoapple2/162	Port of Stephen A. Edwards's Apple2fpga to PYNQ-Z1 (Xilinx Zynq FPGA), to emulate an Apple II+.
38	10	10	2 months ago	FPGA-robotics/163	Verilog library for developing robotics applications using FPGAs
38	3	2	3 years ago	UnAmiga/164	Implementation of Amiga 500/1200 in Altera Cyclone IV FPGA
42	15	4	4 years ago	mce2vga/165	MDA/CGA/EGA to VGA FPGA Converter V2.00
37	15	0	6 years ago	fpga-spectrum/166	Sinclair ZX Spectrum 48k and 128k on an Altera DE1 FPGA board
41	5	0	2 years ago	PYNQ-Torch/167	PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform
36	16	0	1 year, 6 months ago	NN_RGB_FPGA/168	FPGA Design of a Neural Network for Color Detection
36	9	7	2 months ago	BeebFpga/169	None
36	12	0	8 years ago	FPGAPCE/170	PC-Engine / Turbografx-16 clone running on an Altera DE1 board.
35	12	0	a month ago	fp23fftk/171	Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
34	13	0	5 years ago	openMixR/172	4k Mixed Reality headset
34	16	0	4 years ago	FPGA-Speech-Recognition/173	Expiremental Speech Recognition System using VHDL & MATLAB.
35	14	1	8 years ago	img_process_vhdl/174	Image Processing on FPGA using VHDL
38	16	1	3 years ago	PYNQ_softmax/175	achieve softmax in PYNQ with heterogeneous computing.
35	4	0	3 months ago	MicroPET/176	A Commodore PET replica and more - with all new parts in 2022
33	9	0	1 year, 6 months ago	cryptocores/177	cryptography ip-cores in vhdl / verilog
33	14	1	1 year, 24 days ago	vhdl-hdmi-out/178	HDMI Out VHDL code for 7-series Xilinx FPGAs
33	13	1	6 years ago	rgb2vga/179	Analog RGB 15Khz to VGA 31Khz in FGPA
33	17	0	8 years ago	XuLA/180	Everything to do with the XuLA FPGA board: schematics, layout, firmware, example FPGA designs, documentation, etc.
33	11	5	10 months ago	cps2_digiav/181	CPS2 digital AV interface
33	9	1	6 years ago	FPGA_GigabitTx/182	Sending UDP packets out over a Gigabit PHY with an FPGA.
32	19	0	4 months ago	MIPI_CSI2_TX/183	VHDL code for using Xilinx MGT gigabit transceivers/LVDS lines for MIPI CSI-2 TX protocol
32	186	0	a month ago	digital-electronics-1/184	VHDL course at Brno University of Technology
32	15	3	a month ago	ahir/185	Algorithm to hardware compilation tools (e.g. C to VHDL).
31	20	0	a month ago	zynq_cam_isp_demo/186	基于verilog实现了ISP图像处理IP
31	2	0	8 years ago	arm4u/187	ARM4U
31	8	0	9 years ago	MIPS32/188	A MIPS32 CPU implemented by VHDL
31	286	0	4 years ago	vivado-library/189	None
31	16	4	4 months ago	Apple-II_MiSTer/190	Apple II+ for MiSTer
32	4	0	3 months ago	vboard/191	Virtual development board for HDL design
32	1	0	6 years ago	fpga-vt/192	VT100-style terminal implemented on FPGA in VHDL
31	8	5	7 hours ago	Arcade_m72/193	None
30	19	21	9 months ago	Orio/194	Orio is an open-source extensible framework for the definition of domain-specific languages and generation of optimized code for multiple architecture targets, including support for empirical autotuning of the generated code.
30	6	1	4 years ago	riscv-tomthumb/195	A small RISC-V RV32I core written in VHDL, intended as testbed for my personal VHDL learning
30	24	9	7 months ago	Atari2600_MiSTer/196	Atari 2600 for MiSTer
30	22	3	6 years ago	altera-de2-ann/197	Artificial Neural Network on Altera DE2
30	10	0	8 years ago	FP-V-GA-Text/198	A simple to use VHDL module to display text on VGA display.
30	9	0	2 years ago	pano_man/199	Simulation of the classic Pacman arcade game on a PanoLogic thin client.
30	5	0	2 years ago	BenEaterVHDL/200	VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)
30	4	0	27 days ago	xpm_vhdl/201	A translation of the Xilinx XPM library to VHDL for simulation purposes
33	17	0	4 years ago	Designing-a-Custom-AXI-Slave-Peripheral/202	A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
30	10	0	3 years ago	ZYNQ-PYNQ-Z2-Gobang/203	2018第二届全国大学生FPGA创新设计邀请赛的作品
31	2	0	6 years ago	Sweet32-CPU/204	Sweet32 32bit MRISC CPU - VHDL and software toolchain sources (including documentation)
31	5	1	1 year, 4 months ago	FPGACosmacELF/205	A re-creation of a Cosmac ELF computer, Coded in SpinalHDL
30	5	3	3 years ago	AladdinLCD/206	Convert the cheap AladdinXT 4032 Original Xbox modchip to an LCD driver for TSOP modded consoles.
30	16	1	2 years ago	Accelerating-Quantized-CNN-Inference-on-FPGA/207	Accelerating-Quantized-CNN-Inference-on-FPGA(RTL)
30	16	0	2 years ago	Rattlesnake/208	PulseRain Rattlesnake - RISCV RV32IMC Soft CPU
32	8	0	2 years ago	FPGA-Class-D-Amplifier/209	None
29	11	0	10 years ago	vhdl-nes/210	nes emulator based on VHDL
35	10	2	1 year, 25 days ago	AES-VHDL/211	VHDL Implementation of AES Algorithm
29	0	0	6 days ago	xormix/212	A hardware-optimized high-quality pseudorandom number generator
28	17	3	6 years ago	OpenRIO/213	Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
28	19	6	14 days ago	msx1fpga/214	MSX1 cloned in FPGA
28	2	0	2 years ago	aes/215	AES-128 hardware implementation
32	5	0	2 years ago	tiny_z80/216	Business Card Sized Z80 Single Board Computer
28	21	12	6 months ago	MSX_MiSTer/217	MSX for MiSTer
29	14	0	8 years ago	FPGA-FAST/218	FPGA FAST image feature detector implementation in VHDL
29	9	2	2 years ago	AtomFpga/219	Dave's version of the Acorn Atom FPGA, based on AlanD's original from stardot.org.uk
28	22	0	3 years ago	fpga-miner/220	💰 A simplified version of an FPGA bitcoin miner 💰
28	12	0	6 years ago	FPGA-OV7670-cam/221	VHDL/FPGA/OV7670
28	8	0	3 years ago	Motion-Detection-System-Based-On-Background-Reconstruction/222	This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to build a DMA based image data cache transmission system. On this basis, Verilog HDL was used to design the axi4-stream interface based IP core for image processing, so as to build a high real-time moving target detection system. In our design, we focus on the optimization of processing pipeline, improve the traditional frame difference method, and achieve the optimization goal of saving logical resources through the accumulation compression and reconstruction expansion of cached background frames.
29	31	3	6 years ago	logi-hard/223	All Logi specific HDL code (platform specific interface, extension boards, specific hdl, etc)
28	8	2	6 years ago	ZPUFlex/224	A highly-configurable and compact variant of the ZPU processor core
31	5	2	1 year, 8 months ago	FPGA-OV2640/225	This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA.
30	13	0	4 years ago	SpaceInvadersFpgaGame/226	Verilog implementation of the classic arcade game Space Invaders for the Zedboard FPGA board
27	1	0	2 years ago	router/227	清华大学2019计网联合实验第一组
27	8	3	1 year, 1 month ago	TG68K.C/228	switchable 68K CPU-Core
27	3	1	a month ago	MSX-Development/229	MSX is a great 8 bit computer architecture created by ASCII and Microsoft. It was really big in Japan and also in Brazil.
27	16	1	5 years ago	fpga/230	VHDL description of the custom Demolicious GPU. Built during a single semester at NTNU
29	20	2	4 years ago	Designing-a-Custom-AXI-Master-using-BFMs/231	A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
32	3	0	10 months ago	formal_hw_verification/232	Trying to verify Verilog/VHDL designs with formal methods and tools
26	9	1	2 years ago	jcore-cpu/233	J-Core J2/J32 5 stage pipeline CPU core
26	9	1	11 years ago	Floating_Point_Library-JHU/234	VHDL for basic floating-point operations.
27	5	0	2 years ago	NTSC-composite-encoder/235	How to generate NTSC compliant(?) composite color video with an FPGA
26	9	0	4 years ago	memsec/236	Framework for building transparent memory encryption and authentication solutions
27	12	4	3 years ago	ppa-pcmcia-sram/237	PCMCIA SRAM card project (Sakura)
26	11	0	2 months ago	Open-GPGPU-FlexGrip-/238	FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
25	9	1	4 years ago	snickerdoodle-examples/239	Example projects for snickerdoodle
33	14	0	11 months ago	FPGAandImage/240	image processing based FPGA
28	12	0	1 year, 7 months ago	PoC-Examples/241	This repository contains synthesizable examples which use the PoC-Library.
26	12	0	8 years ago	Camera-Tracking/242	Our project is the system that enables a moving camera to track a moving object in real time. We plan on doing this by having a camera mounted to a swivel using two servo motors to allow for the camera’s direction to be controlled. The camera data will be read into the FPGA board and some basic object recognition algorithm will be used to  identify an some object and determine if the camera needs to be moved to keep the object in the field of vision. In addition to the auto tracking mode, we plan on having an IR remote to allow for manual panning, mode selection, and power on and off. If there is additional time we would like to also interface the FPGA to a Raspberry Pi board running a linux web server to allow for email alerts (when object moves) and web based control.
26	14	0	6 years ago	STREAM/243	FPGA development platform for high-performance RF and digital design
26	3	0	2 years ago	fpga-nat64/244	A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.
28	5	0	1 year, 10 months ago	ArtyS7-RPU-SoC/245	Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.
25	15	5	7 months ago	fpga_bitcoin_miner/246	None
25	10	1	4 years ago	vcnn/247	Verilog Convolutional Neural Network on PYNQ
25	12	0	5 years ago	FPGA_Neural-Network/248	The objective is to implement a Neural Network in VHDL code. It is aiming the Cyclone II FPGA Starter Development Kit hardware, but the Neural Network part is meant to be generic, thus it can be used along with different hardware setups.
25	18	5	3 years ago	blockmon/249	A Modular System for Flexible, High-Performance Traffic http://www.ict-mplane.eu/
26	5	5	4 years ago	MARK_II/250	Simple SoC in VHDL with full toolchain and custom board.
25	8	2	1 year, 2 months ago	NVMeCHA/251	NVMe Controller featuring Hardware Acceleration
27	27	22	6 months ago	ipbus-firmware/252	Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol
25	14	2	2 years ago	Pynq-CV-OV5640/253	Pynq computer vision examples with an OV5640 camera
27	10	1	2 years ago	ZipML-XeonFPGA/254	FPGA-based stochastic gradient descent (powered by ZipML - Low-precision machine learning on reconfigurable hardware)
26	19	0	6 years ago	alpha-software/255	Axiom Alpha prototype software (FPGA, Linux, etc.)
24	12	2	3 years ago	Nexys-4-DDR-OOB/256	None
25	17	0	2 years ago	mist-cores/257	core files for the MiST fpga
24	11	0	3 years ago	fft/258	synthesizable FFT IP block for FPGA designs
26	9	1	7 years ago	la16fw/259	Alternative Logic16 Firmware
24	2	2	2 years ago	ese-vdp/260	VHDL implementation of YAMAHA V9938
24	7	0	8 months ago	Xoodoo/261	None
24	32	19	1 year, 9 months ago	mksocfpga/262	Hostmot2 FPGA code for SoC/FPGA platforms from Altera and Xilinx
24	6	0	7 years ago	FPGA-LVDS-LCD-Hack/263	Basic code that displays simple shapes generated from Lattice FPGA directly to LVDS display
24	5	0	3 years ago	pid-fpga-vhdl/264	This project was part of the VLSI Lab. It implements PID control using an FPGA.
24	11	2	3 years ago	ReVerSE-U16/265	Development Kit
27	10	0	6 years ago	PicoBlaze-Library/266	The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).
24	6	0	2 years ago	secd/267	SECD microprocessor reimplementation in VHDL
24	15	1	4 years ago	SRAI_HW_ACCEL_WINDOWS10_PCIe/268	PCIe based accelerator for VCU1525 with xDMA based on Windows10 and Windows Server 2016 development environment
24	1	0	6 years ago	fpga-trace/269	FPGA accelerated ray tracer, implemented in C++ and HLS
24	9	2	2 years ago	cpu86/270	🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA
24	13	3	2 years ago	WishboneAXI/271	Wishbone to AXI bridge (VHDL)
23	19	0	6 years ago	zynq_examples/272	None
23	8	0	3 years ago	nesfpga/273	A Simple FPGA Implementation of the Nintendo Entertainment System
23	1	1	4 years ago	N.I.G.E.-Machine/274	A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is currently hosted on the Digilent Nexys 4 and Nexys 4 DDR
23	3	0	6 years ago	opa/275	Open Processor Architecture
26	12	1	6 years ago	FPGA_SDR/276	Software Defined Radio receiver in Marsohod2 Altera Cyclone III board
23	12	0	2 months ago	fpga_examples/277	Example code in vhdl to help starting new projects using FPGA devices.
23	23	0	9 years ago	rgbmatrix-fpga/278	Adafruit RGB LED Matrix Display Driver for use with FPGAs (written in VHDL)
23	13	21	6 months ago	Atari800_MiSTer/279	Atari 800XL/65XE/130XE for MiSTer
22	9	0	4 years ago	Spectrum/280	Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.
22	8	0	7 years ago	hdl/281	Collection of hardware description languages writings and code snippets
23	1	43	1 year, 2 months ago	Codelib/282	None
22	11	6	4 years ago	OneChipMSX/283	A port of the OneChipMSX project to the Turbo Chameleon 64 and in time, hopefully other boards, too.
22	1	0	3 days ago	fpga_torture/284	🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
23	8	6	3 years ago	EP994A/285	My TI-99/4A clone, two versions: FPGA+TMS99105 CPU and FPGA with my CPU core
27	2	0	2 months ago	noasic/286	An open-source VHDL library for FPGA design.
22	1	0	5 years ago	from-key-array-to-the-LED-lattice/287	None
23	9	11	7 years ago	r-vex/288	A reconfigurable and extensible VLIW processor implemented in VHDL
27	10	1	6 years ago	VGA-Text-Generator/289	A basic VGA text generator for verilog and vhdl
23	1	0	5 months ago	gb-research/290	Game Boy hardware research
21	17	2	7 years ago	zedboard_audio/291	A Audio Interface for the Zedboard
21	28	0	5 years ago	Zedboard-old/292	None
21	3	0	3 months ago	Z80-512K/293	Z80 CPU and Memory Module
21	1	0	a month ago	vhdl-format/294	VHDL String Formatting Library
21	9	0	6 months ago	hackasat-final-2021/295	None
20	7	1	6 years ago	VHDL-Pong/296	A Pong game written in VHDL using a Xilinx Spartan 3 board. VGA + PS/2 Keyboard + Sound support.
23	5	1	1 year, 7 months ago	second_order_sigma_delta_DAC/297	A comparison of 1st and 2nd order sigma delta DAC for FPGA
21	9	0	3 years ago	Hi-DMM/298	Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)
21	7	0	3 years ago	vga_generator/299	A collection of VHDL projects for generating VGA output
21	12	0	3 years ago	sha256/300	A simple SHA-256 implementation in VHDL
21	4	9	a month ago	mrisc32-a1/301	A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
21	3	0	3 months ago	libvhdl/302	Library of reusable VHDL components
21	16	0	a month ago	itc99-poli/303	ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino (I99T)
22	5	0	1 year, 8 months ago	hd6309sbc/304	Hitachi HD6309 Singleboard Computer
21	21	0	2 years ago	gnss-baseband/305	Baseband Receiver IP for GPS like DSSS signals
20	5	0	6 years ago	fpga-bbc/306	Acorn BBC Micro on an Altera DE1 FPGA board
20	6	0	9 years ago	robotron-fpga/307	FPGA implementation of Robotron: 2084
20	2	0	4 years ago	gs4502b/308	Experimental pipelined 4502 CPU design
20	3	1	4 years ago	whirlyfly/309	Hardware RNG for Papilio One based on the original Whirlygig
21	13	0	2 years ago	vhdl_prng/310	Pseudo Random Number Generators as synthesizable VHDL code
28	4	1	1 year, 19 days ago	catapult-v3-smartnic-re/311	Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
20	13	0	2 years ago	jpeg_open/312	A hardware MJPEG encoder and RTP transmitter
21	10	0	6 years ago	fpga_fibre_scan/313	本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互，CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程： 1. 链路初始化： 在上位机完成USB固件的下载，并读取固件的信息状态描述后，通过上电复位或者手动复位，通过串口发送0X55给上位机，表明链路打通，一次握手成功。 2. 超声波发射与AD数据接收：在收到上位机通过串口发送的0X02指令后，开启（START），发送超声方波信号，（注：该START信号在处理过程被改变成包络信号）因为只是单阵元，所以就没有接收延迟聚焦的问题，但有皮肤表皮的客观实际和单阵元回波的时间消耗，所以在等到C_CORDIC_DELAY（1000）后，才开始AD数据的采集。（注：具体多少厚度，需要细算）。每次采集4096个数据，形成一个扫描线；总共需要采集300根扫描线，若不够，则需重新发送方波，并接收AD数据。 3. 剪切波发送： 在采集到第33根扫描线后，开始剪切波的发送，简单的发送50HZ的单载波就可以，此后的AD数据就含有剪切波的信息。 4. 控制通路的信息： 这里通过CYUSB3.0的串口来传送上位机发送的控制端口信息 ，包括数据通路的读和写指令（注：这里只需要通过BULK读取数据通路的数据，不需要通过BULK向数据通路写数据）；通过CYUSB3.0的串口来传送下位机FPGA的状态信息指令给上位机。（由于采用的是URAT，所以有FIFO缓存和数据发送接收状态控制操作） 5. 数据通路的信息： 这里通过上位机的读写指令来将数据存储到FIFO中，这里默认发送的是0X00指令，一直读取AD采集到的数据。并且采用的是BULK的Xfer->read的同步传输，一直要等到指定数目数据（4096*300）采集完才结束采集。 2.2.2 USB3.0模块 1. 这里首先要进行存储划分和寄存器映射，一般汇编或者其他CMD格式，然后编写BOOTLOAD汇编，最后中断跳转处理（汇编）。 2. 这里主要配置GPIF的异步串口参数和读写操作。 3. 这里需要给出CTL端口和BULK端口的配置和读写。 2.3 上位机软件 这里主要完成算法的处理和界面的显示和控制。 关于算法部分需要后面补充，目前没有完全消化。 处理流程： 1. 初始化USB，然后上位机通过控制端点发送写命令控制字（不加帧头命令）下位机未处理，开启监视工作线程循环，主要内容是：通过控制端点发送读命令控制字，通过控制端点读回串口信息，用来验证设备是否启动握手成功（0X55）。 2. 启动成功后引发响应的启动触发方法。启动触发方法中，先要延时大于0.36s，如果选中check_box，则使用存储的测试数据，若未选中，通过控制端点发送写start命令，开启bulk端口读循环线程，最后每次测量发送一次读bulk数据消息到消息队列。 3. 在bulk端口读循环线程中引发响应的bulk读方法，在bulk读方法中，主要调用底层的USB3.0的bulkin读方法，数据读上来后，post一个getData消息，交由绑定的函数来处理数据。 4. 数据处理包括二独立部分，一部分是原始数据产生MotionMOdel信息 ,一部分是原始数据产生剪切波速度和杨氏模量信息。
20	2	0	3 years ago	FpChip8/314	FPGA implementation of CHIP-8 using VHDL.
20	4	1	3 years ago	ym2608/315	VHDL clone of YM2608 (OPNA) sound chip
19	4	1	2 years ago	fpgaNES/316	None
19	5	0	8 years ago	multicomp/317	Simple custom computer on a FPGA
19	6	1	6 years ago	ArtyEtherentTX/318	Sending raw data from the Digilent Arty FPGA board
20	2	0	2 years ago	VHDLBoy/319	VHDL Gameboy implementation
19	3	0	2 years ago	skrach-synth/320	An FPGA synthesizer with MIDI support
23	5	0	2 months ago	riscv-fpu/321	IEEE 754 standard floating point unit fpu single double precision verilog vhdl riscv
18	4	0	5 years ago	Mips54/322	None
19	4	1	9 months ago	360-NAND-X/323	Clone of the NAND-X
19	23	9	3 months ago	Arcade-Pacman_MiSTer/324	Arcade: Pacman for MiSTer
19	6	2	9 years ago	dso-quad-usb-analyzer/325	USB Full-Speed (12Mbps) protocol analyzer for the DSO Quad
19	8	0	9 years ago	lemberg/326	Lemberg is a time-predictable VLIW processor optimized for performance.
19	9	6	7 years ago	SimpleSDHC/327	A basic SD Card SPI interface in VHDL, supports SD V1, V2 and SDHC
19	13	0	9 years ago	grlib/328	None
19	3	1	1 year, 2 months ago	RedPitaya_Acquisition/329	Transform the Red Pitaya in an acquisition card
19	4	0	5 years ago	neuron-vhdl/330	Implementation of a neuron and 2 neuronal networks in vhdl
19	6	1	2 years ago	WonderMadeleine/331	WonderMadeleine is a Bandai 2001/2003 clone chip
19	7	0	3 years ago	light52/332	Yet another free 8051 FPGA core
19	5	0	5 years ago	MIPS/333	VHDL implementation of a MIPS processor for Spartan-6 FPGA
19	11	1	7 years ago	axi_custom_ip_tb/334	A testbench for an axi lite custom IP
19	11	3	1 year, 2 months ago	pauloBlaze/335	A plain VHDL implementation of a small microprocessor fully compatible with the ISA of the well known PicoBlaze by Ken Chapman.
18	1	1	5 years ago	NISC/336	A single instruction set processor architecture
18	10	0	9 months ago	c64pla/337	C64 PLA implementation in VHDL
18	11	1	2 years ago	camera-filters/338	Colorspace conversion, gamma correction, and more -- all integrated within a MIPI-to-HDMI pipeline in FPGA.
18	12	2	2 months ago	BBCMicro_MiSTer/339	BBC Micro B and Master 128K for MiSTer
20	5	4	4 years ago	cv2PYNQ-The-project-behind-the-library/340	This project describes how the cv2PYNQ python library was built
18	9	0	4 months ago	EP2C5-Cyclone-II-Mini-Board/341	EP2C5 Cyclone II Mini Board
18	7	0	4 years ago	revCtrl/342	Revision Control Labs and Materials
18	10	1	10 years ago	Network-on-Chip-in-VHDL/343	None
19	8	0	3 months ago	MIMORPH/344	None
18	0	0	8 months ago	wb_spi_bridge/345	🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
18	4	1	8 years ago	BBot/346	BBot! An open source, wireless beer serving robot reference design featuring a C++ program running on a BeagleBone Black, a .Net WPF control GUI and even low level FPGA integration!
18	19	1	6 years ago	StickIt/347	StickIt! board and modules that support the XuLA FPGA board.
19	2	0	4 years ago	cosmac/348	RCA COSMAC CDP1802 functional equivalent CPU core in VHDL
18	1	9	2 years ago	vhdeps/349	VHDL dependency analyzer
18	3	0	4 years ago	vm2413/350	A YM2413 clone module written in VHDL.
18	0	0	2 years ago	ArtyS7/351	Where Arty S7 projects are kept. MIT License unless file headers state otherwise.
19	14	3	3 years ago	VHDL-JESD204b/352	JESD204b modules in VHDL
18	28	2	8 years ago	AD/353	Altium Desinger
19	16	0	6 years ago	miilink/354	Connecting FPGA and MCU using Ethernet RMII
18	3	4	6 years ago	tusSAT/355	A SAT solver implementation in VHDL, team tussle
18	11	0	5 years ago	aes-over-pcie/356	A VHDL implementation of 128 bit AES encryption with a PCIe interface.
18	10	5	2 years ago	cnn_vhdl_generator/357	AUTOMATIC VHDL GENERATION FOR CNN MODELS
18	7	2	27 days ago	ZXNext_MISTer/358	None
18	3	0	8 days ago	ustc_course_plus/359	可作为ustc课程资源的补充，包括一些秘密的真题和ppt
18	6	0	2 years ago	Altera-Cyclone-II-EP2C5T144-blink/360	A very junior "Hello World" for the low price Altera Cypress II EP2C5T144 FPGA Mini dev board from amazon/ebay
17	7	1	23 hours ago	neorv32-setups/361	📁 NEORV32 projects and exemplary setups for various FPGAs, boards and toolchains.
17	6	5	2 years ago	rygar-fpga/362	A FPGA core for the arcade game, Rygar (1986).
17	16	5	2 years ago	PothosZynq/363	DMA source and sink blocks for Xilinx Zynq FPGAs
17	3	0	1 year, 10 months ago	ZXNext_Mister/364	ZX Next core for Mister
18	6	0	2 years ago	FPGA-Audio-IIR/365	None
17	3	10	2 months ago	spartan-edge-accelerator-graphical-system/366	WIP Graphics layer and inter IC communication for the Spartan Edge Accelerator fpga/mcu hybrid board
17	10	0	3 years ago	Arty-A7-35-GPIO/367	None
18	8	2	5 years ago	netv2-fpga-basic-overlay/368	Vivado design for basic NeTV2 FPGA with chroma-based overlay
17	1	1	2 years ago	fppa-pdk-emulator-vhdl/369	VHDL simulation model for PADAUK PDK microcontrollers
17	9	2	25 days ago	DeMiSTify/370	Code to support porting MiST cores to other boards.
17	4	0	4 years ago	Z-turn-examples/371	The repository with my simple Z-turn examples, to be used as templates for more serious project
20	15	0	2 years ago	LMAC_CORE3/372	Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
17	3	0	10 months ago	R-JTOP/373	Open source implementation of CB fusecheck glitch
17	0	0	2 years ago	VHDL6526/374	None
17	0	0	1 year, 2 months ago	C88/375	C88 is Homebrew CPU that has a ram that is only 8x8 Bits in size. It'll fit on a papilio one 500k which has enough pins for all the switches you need too.
17	11	8	2 months ago	Amstrad_MiSTer/376	Amstrad CPC 6128 for MiSTer
17	2	0	8 years ago	myhdl_simple_uart/377	A very simple UART implementation in MyHDL
16	3	0	4 years ago	THU-MIPS16-CPU/378	Tsinghua University Computer Composition Principle Experiment
21	12	0	1 year, 8 months ago	scopy-fpga/379	Application software for Scopy MVP: FPGA PS, PL, and microcontroller firmware
18	8	1	5 years ago	zybo_petalinux_video_hls/380	Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output.
17	13	0	2 years ago	Hardware-Implementation-of-AES-VHDL/381	Hardware Implementation of Advanced Encryption Standard Algorithm in VHDL
17	11	1	9 years ago	hashvoodoo-fpga-bitcoin-miner/382	HashVoodoo FPGA Bitcoin Miner
16	20	0	5 years ago	Nexys4DDR/383	None
16	11	6	6 months ago	TI-99_4A_MiSTer/384	Texas Instrument 99/4A Home Computer
16	8	0	1 year, 11 months ago	Getting-to-Know-Vivado/385	Source files for Getting to Know Vivado course
19	9	0	12 years ago	MIPS-Lite/386	A pipelined MIPS-Lite CPU implementation
17	6	1	2 years ago	jcore-soc/387	J-Core SoC Base Platfrom. Top level for FPGA platforms, pulls in CPU, BootROM and various IP blocks.
16	2	1	3 years ago	light8080/388	Synthesizable i8080-compatible CPU core.
16	8	1	5 years ago	Nexys4/389	None
16	6	2	a month ago	rfsoc_ofdm/390	PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
16	8	0	4 years ago	EM070_New-FPGA-family-for-CNN-architectures-High-Speed-Soft-Neuron-Design/391	Who doesn’t dream of a new FPGA family that can provide embedded hard neurons in its silicon architecture fabric instead of the conventional DSP and multiplier blocks? The optimized hard neuron design will allow all the software and hardware designers to create or test different deep learning network architectures, especially the convolutional neural networks (CNN), more easily and faster in comparing to any previous FPGA family in the market nowadays. The revolutionary idea about this project is to open the gate of creativity for a precise-tailored new generation of FPGA families that can solve the problems of wasting logic resources and/or unneeded buses width as in the conventional DSP blocks nowadays. The project focusing on the anchor point of the any deep learning architecture, which is to design an optimized high-speed neuron block which should replace the conventional DSP blocks to avoid the drawbacks that designers face while trying to fit the CNN architecture design to it. The design of the proposed neuron also takes the parallelism operation concept as it’s primary keystone, beside the minimization of logic elements usage to construct the proposed neuron cell. The targeted neuron design resource usage is not to exceeds 500 ALM and the expected maximum operating frequency of 834.03 MHz for each neuron. In this project, ultra-fast, adaptive, and parallel modules are designed as soft blocks using VHDL code such as parallel Multipliers-Accumulators (MACs), RELU activation function that will contribute to open a new horizon for all the FPGA designers to build their own Convolutional Neural Networks (CNN). We couldn’t stop imagining INTEL ALTERA to lead the market by converting the proposed designed CNN block and to be a part of their new FPGA architecture fabrics in a separated new Logic Family so soon. The users of such proposed CNN blocks will be amazed from the high-speed operation per seconds that it can provide to them while they are trying to design their own CNN architectures. For instance, and according to the first coding trial, the initial speed of just one MAC unit can reach 3.5 Giga Operations per Second (GOPS) and has the ability to multiply up to 4 different inputs beside a common weight value, which will lead to a revolution in the FPGA capabilities for adopting the era of deep learning algorithms especially if we take in our consideration that also the blocks can work in parallel mode which can lead to increasing the data throughput of the proposed project to about 16 Tera Operations per Second (TOPS). Finally, we believe that this proposed CNN block for FPGA is just the first step that will leave no areas for competitions with the conventional CPUs and GPUs due to the massive speed that it can provide and its flexible scalability that it can be achieved from the parallelism concept of operation of such FPGA-based CNN blocks.
16	5	0	2 years ago	Handwritten-Digit-Recognition-Painter/392	A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.
17	8	0	4 years ago	S2NN-HLS/393	Spiking neural network for Zynq devices with Vivado HLS
17	8	2	5 years ago	PYNQ_PR_Overlay/394	Adding PR to the PYNQ Overlay
16	4	0	5 years ago	Cache/395	Simple implementation of cache using VHDL
16	23	10	3 months ago	Arcade-DonkeyKong_MiSTer/396	Arcade: Donkey Kong for MiSTer
16	3	0	7 years ago	GAIA3/397	GAIA Processor
16	12	0	9 hours ago	dsd/398	Digital System Design
17	12	1	5 years ago	ZedBoard-OLED/399	Driving the OLED display on the ZedBoard
17	7	0	1 year, 11 months ago	getting-started-FV/400	None
16	2	1	a month ago	fsva/401	FuseSoc Verification Automation
16	12	0	3 years ago	AX7035/402	None
16	7	0	4 years ago	FPGA-shared-mem/403	Exploring Shared Virtual Memory Abstractions in OpenCL Tools for FPGAs
20	13	0	2 years ago	FPGA-Vision/404	Learn about image processing with an FPGA. Video lectures explain algorithm and implementation of lane detection for automotive driving. Real hardware is available as a remote lab.
15	2	0	3 years ago	deocmpldcv/405	This project is a port of the 1chipMSX to DEOCM + DE0-CV including modification of OCM-PLD.
15	4	0	3 years ago	ultra96_design/406	Repository of HW design and SW for Ultra96 board + MIPI board
15	10	3	5 months ago	TRS-80_MiSTer/407	Tandy TRS-80 Model I (port of HT1080Z to MiSTer)
17	4	0	3 years ago	vgg16-on-Zynq/408	Simulating implement of vgg16 network on Zynq-7020 FPGA
14	6	0	3 years ago	REAPR/409	REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications such as regular expressions. REAPR is currently only compatible with SDAccel-capable Xilinx FPGA boards.
15	4	0	9 days ago	super-reu/410	An advanced FPGA-based ram expansion module for C64/C128
18	2	0	3 months ago	atari_system1_fpga/411	FPGA implementation of Atari System 1 LSI arcade
15	10	0	8 years ago	VHDL-Pong/412	Straightforward Pong Game written in VHDL. Scoring and Multiplayer
15	3	1	6 years ago	6502/413	VHDL description of 6502 processor with FPGA synthesis support.
17	6	0	3 years ago	LeNet-on-Zynq/414	Simulating implement of LeNet network on Zynq-7020 FPGA
15	0	0	4 years ago	k1208-cpld/415	K1208 A1200 fastmem board CPLD logic
15	6	1	4 months ago	fmh_gpib_core/416	GPIB IEEE 488.1 core
15	4	0	1 year, 5 months ago	SM4-FPGA/417	SM4 is a block encryption algorithm
17	4	0	1 year, 10 months ago	Homebrew-65C02-Computer/418	A homebrew 65C02 based computer with PS/2 Keyboard, Serial & Parallel IO + 3 Expansion slots
15	8	0	1 year, 6 months ago	Demo_project/419	None
17	8	2	4 years ago	Sha256_Hw_Accelerator/420	SHA256 hardware accelerator, synthesized for and mapped on the Zynq core of the Zybo board by Digilent
17	6	0	3 months ago	fpga_cores/421	None
15	3	0	15 days ago	Digital-Design/422	Digital design circuits
16	4	0	2 years ago	Nexys-A7-100T-OOB/423	None
15	3	0	2 years ago	probe-scope-fpga/424	FPGA Software for the Probe-Scope
14	9	1	8 years ago	cmake-verilog-vhdl-fpga-template/425	CMake template for Verilog and VHDL project and Altera/Xilinx FPGA target
16	11	0	6 years ago	zybo_petalinux/426	Small projects intended to run on the Digilent Zybo development board, utilizing PetaLinux on the Zynq's ARM processor.
17	5	1	2 years ago	maestro/427	A 5 stage-pipeline RV32I implementation in VHDL
15	4	1	1 year, 7 months ago	agc_monitor/428	Modern implementation of the AGC Monitor, for use with a real Apollo Guidance Computer
15	5	1	1 year, 5 months ago	DirectNVM/429	An open-source RTL NVMe controller IP for Xilinx FPGA.
15	3	5	6 months ago	RANC/430	None
15	28	0	1 year, 5 months ago	hostmot2-firmware/431	HostMot2 FPGA firmware
14	5	0	4 years ago	OSXA/432	The OSXA repository contains the design files for an LPC flash addon to the original xbox video game console.
15	14	0	5 years ago	Hardware-Neural-Network/433	Embedded hardware accelerator of multilayer perceptrons for lightweight machine learning
16	3	0	1 year, 2 months ago	RISC-CPU/434	A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
14	4	0	4 years ago	OSXANF/435	The OSXA repository contains the design files for a NOR flash addon to the original xbox video game console.
14	0	1	2 years ago	seqpu/436	A bit-serial CPU
16	3	0	2 years ago	j-core-ice40/437	J-core SOC for ice40 FPGA
16	5	1	3 years ago	Shouji/438	Shouji is fast and accurate pre-alignment filter for banded sequence alignment calculation. Described in the Bioinformatics journal paper (2019) by Alser et al. at https://academic.oup.com/bioinformatics/advance-article-pdf/doi/10.1093/bioinformatics/btz234/28533771/btz234.pdf
15	5	1	8 years ago	snes-flash/439	None
14	4	2	8 years ago	vhdl-csv-file-reader/440	VHDL package for reading formatted data from comma-separated-values (CSV) files
14	14	3	2 years ago	Arcade-Arkanoid_MISTer/441	None
14	1	0	7 years ago	siphash/442	A VHDL implementation of SipHash
14	2	0	8 days ago	GBADVI/443	None
15	4	0	3 years ago	antDev/444	Agile Network Tester with FPGA & multi-cores
14	0	0	a month ago	RGH1.2-V2-Phat/445	RGH1.2 V2, Phat Version, improvements over the old one
14	9	0	3 months ago	FPGAandGames/446	FPGA实现各种小游戏，学习并快乐着
14	4	0	13 years ago	zpu/447	ZPU - the worlds smallest 32 bit CPU with GCC toolchain
14	3	0	5 years ago	subleq-machine-vhdl/448	The final code of a two-hour challenge to simulate and implement a SUBLEQ SISC machine
20	8	1	3 years ago	UniversalPPU/449	An FPGA replacement for the graphics chip used in the NES and related systems
14	4	0	3 years ago	BoostDSP/450	VHDL Library for implementing common DSP functionality.
14	1	0	6 years ago	YM2612/451	VHDL description and documentation of architecture and undocumented features in Yamaha YM2203 (OPN) and YM2612 (OPN2)
14	5	0	4 years ago	SMSMapper/452	Sega Master System Homebrew Flash Cart
17	6	1	8 months ago	CryptoHDL/453	A list of VHDL codes implementing cryptographic algorithms
14	3	0	3 years ago	prjtrellis-dvi/454	DVI video out example for prjtrellis
14	4	0	8 years ago	uart-vhdl/455	An RS232 communication controller implemented in VHDL
15	1	0	2 years ago	synthowheel/456	Polyphonic additive wheeltone synthesizer core
14	5	1	7 days ago	LMAC_CORE1/457	LMAC Core1 - Ethernet 1G/100M/10M
14	10	0	3 years ago	Basys-3-GPIO/458	None
14	2	0	5 years ago	patmos_HLS/459	Hardware Accelerators (HwAs) constructed in Vivado HLS
14	6	0	5 years ago	absenc/460	Absolute encoder VHDL core
14	0	0	2 years ago	UK101onFPGA/461	Fork of the emulator for Compukit UK101 on FPGA
14	5	0	3 years ago	RealTimeVideo/462	High-speed real time streaming video on Zybo Z7-10
14	2	0	3 years ago	Xilinx-Deep-Learning-Nexys4/463	Implemented Darius IP (originally target PYNQ) of convolution and maxpool on Xilinx FPGA with SDK
14	15	3	a month ago	psi_common/464	Common elements for FPGA Design (FIFOs, RAMs, etc.)
14	3	0	4 years ago	adpll/465	All digital PLL
14	12	1	8 years ago	SpaceWireCODECIP_100MHz/466	None
14	2	0	1 year, 11 months ago	FPGA-X68k-DE0CV/467	None
14	0	0	1 year, 3 months ago	simple-riscv/468	A simple three-stage RISC-V CPU
14	12	0	5 years ago	16-bit-HDLC-using-VHDL/469	High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.
13	2	0	6 years ago	vhdl_sincos_gen/470	Sine / cosine function core in VHDL
13	4	0	3 years ago	s4noc/471	A Statically-scheduled TDM Network-on-Chip for Real-Time Systems
16	8	0	3 years ago	SidewinderFPGA/472	Sidewinder FPGA
13	5	5	1 year, 2 months ago	pocket-cnn/473	CNN-to-FPGA-framework for small CNN, written in VHDL and Python
15	2	0	2 years ago	cod19grp4/474	奋战一学期 造台联网计算机（MIPS32 CPU + 硬件 RIP 路由器）
13	3	2	6 years ago	aes-fpga/475	AES implementation on FPGA
13	13	1	3 years ago	cnn-fpga-rtl/476	The CNN architecture elements implemented with RTL approach in VHDL.
14	2	0	1 year, 10 months ago	VGA-6502/477	A VGA card for my homebrew 65C02 based computer
13	5	1	6 years ago	RSA-Encryption/478	VHDL implementation of RSA encryption/decryption using Montgomery modular multipliers
14	11	0	3 months ago	fpga_ip/479	OscillatorIMP ecosystem FPGA IP sources
13	0	0	1 year, 5 months ago	CRYSTALS-Kyber/480	None
13	5	0	3 years ago	DES-cracker/481	DES cracking machine on FPGA
16	9	1	3 years ago	LimeSDR_DVBSGateware/482	Optimised gateware for lime sdr mini
13	2	0	8 years ago	myhdl-examples/483	None
14	0	1	7 months ago	spu-mark-ii/484	CPU and home computer project
13	5	0	7 years ago	FIRFilter/485	This project is a High and Low pass filter designer written in Octave to design and calculate the filter coefficients for a windows sinc filter. The coefficients can be used in the vhdl code for signal processing.
13	11	0	1 year, 2 months ago	FPGAandLAN/486	FPGAandLAN
13	2	1	10 months ago	Brutzelkarte_FPGA/487	The Brutzelkarte FPGA description code in VHDL
13	5	0	2 years ago	vhdl-digital-design/488	VHDL code examples for a digital design course
13	3	0	3 years ago	Pixblasters-MicroDemo/489	Create video LED displays by RGB LED strips
13	1	0	5 years ago	gimli/490	Reference implementations of the GIMLI permutation
13	5	1	4 years ago	capi-streaming-framework/491	AFU framework for streaming applications with CAPI.
13	0	0	3 days ago	ocm-pld-dev/492	Official firmware under devolpement for MSX++ computers and compatibles: 1chipMSX, Zemmix Neo (KR/BR), SX-1 (regular, Mini, Mini+), SM-X and SX-2.
13	6	0	2 months ago	UVVM_Light/493	This repository is a subset of UVVM with Utility library and BFMs, and is intended as a UVVM starting platform for thos who only need the Utility Library and BFMs. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
13	0	0	1 year, 5 months ago	hitsz-eie-codes/494	哈工大深圳 电信学院 通信工程 部分实验课程代码仓库
13	0	0	8 years ago	xentral/495	XENTRAL is a simple Harvard Architecture CPU.
14	2	0	4 years ago	VIIRF/496	Hardware description (VHDL) and configuration scripts (Python) of a versatile IIR Filter implemented as cascaded SOS/biquads. No vendor-specific hardware constructs used.
14	6	0	6 years ago	Zynq_Project/497	Zynq project to interface OV2640 camera module
12	2	0	4 years ago	AnalogCPU/498	8位模型机（数字电子课程设计）
13	10	1	1 year, 10 months ago	OpenHT/499	Hybrid Threading Tool Set
13	6	0	a month ago	TJCS-Courses/500	TJCS-Courses
13	7	0	7 days ago	PU-RISCV/501	Processing Unit with RISCV-32 / RISCV-64 / RISCV-128
14	6	1	4 years ago	ASP-SoC/502	Audio Signal Processing SoC
13	11	0	10 years ago	VHDL-Mips-Pipeline-Microprocessor/503	VHDL-Mips-Pipeline-Microprocessor
12	2	0	4 months ago	VHDPlus_Libraries_and_Examples/504	This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with future updates.
15	17	0	9 years ago	LEON2/505	LEON2 SPARC CPU IP core LGPL by Gaisler Research
12	5	1	2 years ago	T-DLA/506	None
12	3	0	2 years ago	hardware-sort/507	Hardware-accelerated sorting algorithm
12	2	1	7 years ago	keyboard-ip/508	PS/2 Keyboard IP written in VHDL for Xilinx FPGA
14	8	0	7 months ago	VCS-1/509	VCS-1 system
13	8	0	4 years ago	pacedev/510	Programmable Arcade Circuit Emulation
12	2	0	9 months ago	SUSTech_Course/511	Courses in SUSTech
14	11	1	5 years ago	Arty-Z7-old/512	Board repository for the Arty Z7
13	1	1	1 year, 8 months ago	Sudoku-Solver/513	A brute force algorithm on hardware is used to solve a sudoku. When a valid fill is not found backtracking is done. Backtracking is repeated until last number is a valid guess i.e guess out of 1 to 9. Digital logic realised using priority encoders and multiplexers.
12	5	1	2 years ago	LPC2LCD/514	LCD adapter for the LPC bus of the OG xbox
12	2	0	2 months ago	MSI-VHDL/515	None
12	8	2	2 years ago	gigevision-xilinx/516	GigE Vision compatibe video streaming from MIPI-CSI camera with Zybo Z7-10 board
13	1	0	1 year, 5 months ago	Pynq-Accelerator/517	A easy general acc.
12	1	3	7 days ago	one-chip-msx-kai/518	1chipMSXをベースとした OCM改 の開発リポジトリです
12	7	1	5 years ago	tdc/519	A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.
12	2	1	2 years ago	sdram/520	Simple fixed-cycle SDRAM Controller
12	5	0	2 years ago	Genesys_ZU_MIPI_PCAM/521	Imaging application using MIPI and DisplayPort to process image
12	1	9	6 months ago	BebiChiken/522	None
12	4	0	3 years ago	GNSS-VHDL/523	VHDL codes to generate GPS L1 C/A and Galileo E1OS and E5 PRNs and dataless signals. Secondary codes not included.
12	7	0	7 years ago	Xilinx-GPIO-Interrupt/524	It is a GPIO interrupt example for xilinx ZYNQ FPGA.
12	3	0	2 months ago	spi-to-axi-bridge/525	An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
12	0	1	4 years ago	mips-cpu/526	None
12	38	0	a month ago	riscv-multicycle/527	RISC-V muticycle implementation in VHDL. Core supports multiple peripherals and interruptions using a simple local interrupt controller.
12	5	5	1 year, 8 months ago	cpu/528	MIPS CPU
14	9	0	3 years ago	GateKeeper/529	GateKeeper: Fast Alignment Filter for DNA Short Read Mapping
13	3	1	5 months ago	MSX1_MiSTer/530	None
12	11	0	27 days ago	general-cores/531	general-cores
12	6	0	7 years ago	fpga-led-matrix/532	HDMI decoder and LED matrix controller on a Spartan-6 FPGA
11	10	0	9 years ago	fpga-camera/533	FPGA digital camera controller and frame capture device in VHDL
12	16	1	8 months ago	Arcade-Galaga_MiSTer/534	Arcade: Galaga for MiSTer
12	0	0	5 years ago	SAYEH/535	SAYEH cpu-memory basic computer
12	6	2	2 years ago	DivGMX/536	Development Kit
12	3	1	4 months ago	FPGA-Notes-for-Scientists/537	None
13	3	0	2 months ago	FGPU/538	FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
12	16	0	1 year, 4 months ago	realtimeEMTP/539	FPGA and CPU-Based power system's simulator
12	7	0	8 years ago	aeshw/540	None
13	4	0	2 years ago	can-lite-vhdl/541	A lightweight Controller Area Network (CAN) controller in VHDL
11	1	0	2 years ago	DIYPOV/542	One POV Display to rule them all!
12	2	0	1 year, 8 months ago	16x16-bit-Dada-multiplication/543	Design a Dadda multiplier for unsigned 16x16 bit multiplication with a Brent Kung adder for the final addition in synthesizable VHDL.
11	0	0	4 months ago	Guitar-Pedal-Effects-on-FPGA/544	This is my bachelor's degree project. I have used a FPGA to modify audio signal and create different sounds, like distortion, overdrive, echo, reverb...
11	6	1	5 years ago	digital-storage-oscilloscope/545	An FPGA implementation of a digital storage oscilloscope.
11	2	0	10 months ago	build-cpu-within-20days/546	北京理工大学 2021小学期 计算机组成原理课程设计。硬件描述语言实现计算机系统
11	3	0	2 years ago	FPGA-SPI-Flash/547	Various projects of SPI loader module for xilinx fpga
11	1	0	5 months ago	openStreamHDL/548	VHDL Code for infrastructural blocks (designed for FPGA)
11	3	0	8 months ago	riscv-debug-dtm/549	🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
11	14	0	6 years ago	team_psx/550	18545 Repo
11	13	1	4 years ago	aws-fpga-miner/551	None
11	2	0	2 years ago	ImpeccableCircuits/552	Hardware designs for fault detection
13	5	1	5 months ago	kvm-ip-zynq/553	KVM over IP Gateway targeting Zynq-7000 SoC
12	3	0	3 months ago	Mini_System/554	Signal generator designed with Nexy4 FPGA
11	1	0	8 years ago	PSP-Display-Driver/555	VHDL code for driving a playstation portable display
11	2	1	5 years ago	tetris-vhdl/556	A bare-metal pure hardware implementation of the Tetris game for FPGA
12	5	7	2 years ago	fpgasdr/557	FPGA firmware for FPGA radio baseband board. Scroll down for README.
11	1	0	2 years ago	VHDL-FPGA-LAB_PROJECTS/558	My Lab Assigments from Bachelor Degree, This repo includes the projects for digital systems II Lecture (EEM334)
11	3	0	5 years ago	uCPUvhdl/559	An 8-bit soft processor in VHDL
13	3	2	1 year, 3 months ago	vunit_action/560	VUnit GitHub action
11	9	0	a month ago	rfsoc_radio/561	PYNQ example of using the RFSoC as a BPSK radio transceiver.
11	1	0	10 years ago	DCPU16-VHDL/562	An implementation of the DCPU-16 from 0x10c in VHDL.
11	2	0	4 years ago	vu_meter/563	FPGA-based FFT audio spectrum analyzer
10	3	2	4 years ago	reVISION-Zybo-Z7-20/564	None
12	1	0	1 year, 1 month ago	COD_2021Spring/565	Computer Organization and Design labs @USTC, 2021 Spring
11	2	0	4 years ago	VGA_mem_mapped/566	Memory-mapped VGA display for Xilinx/Zynq/Zedboard, with demo code for using it.
11	2	0	11 years ago	cpu_arm/567	An ARMv4 compatible CPU core. (INCOMPLETE)
13	2	0	8 months ago	wf68k30L/568	A pipelined 68030 softcore in VHDL
11	4	1	2 years ago	single-cycle-processor/569	An implementation of the simplest single cycle processor.
11	3	0	10 years ago	fpga-midi-synth/570	MIDI synthesizer written in VHDL
13	8	0	7 years ago	Cameralink-LPC-FMC-Module/571	None
11	9	0	7 years ago	VGA/572	VGA Tutorial for DE1
11	10	6	6 days ago	WonderSwan_MiSTer/573	WonderSwan Color for MiSTer
11	1	0	10 months ago	IC-Design-Contest-ARM-CUP/574	集成电路设计大赛ARM杯作品，目前华中赛区第一名
11	8	0	7 years ago	miniOV7670/575	Interfacing OV7670 Camera module to miniSpartan6+
11	0	3	10 years ago	Papilio-Master-System/576	None
11	3	1	1 year, 10 months ago	ulx3s-ghdl-examples/577	ulx3s ghdl examples
13	2	0	6 years ago	vhdl_verification/578	Examples and design pattern for VHDL verification
11	3	0	3 years ago	FISC-VHDL/579	FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64
11	3	1	19 days ago	vextproj/580	VEXTPROJ - the version control friendly system for creation of Vivado projects
11	2	3	30 days ago	karabas-pro/581	FPGA based retrocomputer with FDD and HDD controllers
11	1	0	a month ago	riscv-sfpu/582	IEEE 754 standard floating point unit fpu single precision verilog vhdl riscv
11	3	0	13 days ago	ReconROS/583	Easy to use framework for ROS2 FPGA-based hardware acceleration; Supports Pub/Sub communication, Actions and Services and costum ROS Messages
11	2	0	3 days ago	MiSTer2MEGA65/584	Framework to simplify porting MiSTer cores to the MEGA65
14	1	0	4 years ago	8_bit_cpu/585	ALINX ALTERA FPGA黑金开发学习板 CYCLONE IV 数电课设八位模型机
11	5	0	4 years ago	XilinxIP/586	Xilinx IP repository
12	3	1	4 years ago	CPU-Adelie/587	None
12	4	0	3 years ago	XNOR-net-Binary-connect/588	A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacement of vector-matrix multiplication to “XNOR + Popcount” operation
11	10	0	11 years ago	udp_ip__core/589	UDP/IP Core
10	6	0	2 years ago	COD-Resources-2017/590	中科大 2017 级数字电路实验/组成原理实验的同学经验和资料分享
11	1	0	2 years ago	naiverouter/591	A router IP written in Verilog.
10	6	1	2 years ago	vhdl/592	vhdl related contents
10	1	0	6 years ago	ADC_Sigma_Delta_VHDL/593	Sigma-Delta Analog to Digital Converter in FPGA (VHDL)
12	9	0	16 years ago	ofdm/594	OFDM modem
10	4	0	2 years ago	efficient_checksum-offload-engine/595	Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream interface.
10	3	0	4 years ago	Amiga600GALFirmware/596	Amiga 600 with Gayle 1: VHDL implementation of PAL16L8B (XU1) with Lattice GAL16V8
10	5	0	2 months ago	leon3-grlib-gpl-mirror/597	Git mirror of Gaisler's GRLIB/Leon3 releases
10	6	0	3 months ago	SIEAV/598	Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
10	1	0	7 months ago	VHDL-Guide/599	VHDL Guide
10	7	0	5 years ago	wireless-mac-processor/600	None
10	4	0	4 years ago	Aeon-Lite/601	Aeon Lite - Open Source Reconfigurable Computer
10	2	0	1 year, 10 months ago	cocotbExamples/602	None
10	8	0	7 years ago	SHA3-VHDL/603	Hardware implementation of cryptographic Hash function SHA-3 (keccak) using VHDL
10	1	1	25 days ago	ym2149_audio/604	YM-2149 / AY-3-8910 Complex Sound Generator FPGA core.
10	14	5	9 months ago	bel_projects/605	GSI Timing Gateware and Tools
10	0	0	2 years ago	32-bit-Brent-Kung-architecture/606	Brent Kung architecture for adding 32 bit operands.
10	3	0	1 year, 3 months ago	FPGA_ADC/607	An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
10	9	0	4 months ago	QL_MiSTer/608	Sinclair QL for MiSTer
11	1	0	a month ago	ArmedF/609	Nichibutsu Armed F / Terra Force WIP
10	5	0	4 years ago	SECURE_HASH/610	SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).
12	10	0	7 years ago	HLS-Axi-Master-on-Microzed-with-Yocto-Linux-device-driver/611	Creation of a AXI Master and Yocto device driver for Zynq, using High Level Synthesis (HLS) techniques.
10	3	0	9 years ago	fpgasynth/612	VHDL for an FPGA based MIDI music synthesizer
9	1	0	8 years ago	vsim/613	VHDL simulator in Haskell
10	1	8	2 years ago	Arcade-DonkeyKongJunior_MiSTer/614	Donkey Kong Junior arcade clone for MiSTer.
11	1	0	6 months ago	PipelinedRiskProcessor/615	This is a 5 staged Pipelined risk microprocessor ,implemented in VHDL language.
12	2	0	1 year, 9 months ago	VHDL/616	Příklady ke knize Data, čipy, procesory
10	1	0	1 year, 6 months ago	imagesensor_system/617	This document is a project of cmos image sensor system. The doc mainly includes LUPA4000 Cmos sensor driving, SDRAM storage, LVDS data readout etc. The code is written in VHDL.
10	4	0	4 years ago	srio_test/618	Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)
10	4	0	5 years ago	ImageCaptureSystem/619	A Xilinx IP Core and App for line scanner image capture and store
10	4	0	1 year, 8 months ago	MSHR-rich/620	A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency-insensitive hardware accelerators with irregular memory access patterns.
10	14	3	1 year, 2 months ago	Arcade-Tecmo_MiSTer/621	MiSTer arcade core for Tecmo arcade classics: Rygar (1986), Gemini Wing (1987), and Silkworm (1988).
10	5	0	2 days ago	zxuno/622	None
11	0	1	4 years ago	maplebus/623	Sega Dreamcast Maplebus Transceiver
10	2	1	4 years ago	argh2600/624	VHDL implementation of an Atari 2600
11	1	0	9 years ago	fp68060/625	PCB to plug FPGA softcore CPU into 68060 microprocessor socket
10	7	0	1 year, 8 months ago	UCAS-CS/626	Undergraduate 2017-2021
10	5	0	6 years ago	FPGA-LCD-Driver/627	FPGA LVDS LCD driver
10	0	1	6 years ago	vertcl/628	VHDL Tcl interpreter
12	5	1	2 years ago	pl-nvme/629	None
10	2	0	9 years ago	sdr/630	A software-defined radio.
10	8	2	4 years ago	Zybo-Z7-20-base-linux/631	None
10	1	2	9 years ago	AlteraMeatBoyHD/632	Quartus project files for an Altera DE2 Meat Boy game. Proper functionality not guaranteed.
10	14	5	11 months ago	Arcade-Galaxian_MiSTer/633	Arcade: Galaxian for MiSTer
10	3	0	8 years ago	gandalf-miner/634	bitcoin miner for the A3255-Q48 chip
10	2	0	2 years ago	hashpipe/635	SHA-256 Bitcoin hashing engine implemented as a systolic pipeline
10	13	1	6 years ago	zycap/636	Zynq PR Management
10	14	5	5 months ago	Vectrex_MiSTer/637	Vectrex for MiSTer
11	3	0	2 years ago	DSFPGA/638	DS on FPGA
10	6	0	8 months ago	FPGAandUSB3.0/639	None
10	4	0	2 years ago	Binocular-Stereo-Vision-PYNQ/640	None
10	8	2	11 months ago	zynq_tdc/641	A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
10	5	0	1 year, 6 months ago	TMS5220_FPGA/642	VHDL model of TMS5220 voice synthesizer processor
10	4	0	5 years ago	MQP/643	Electrical and Computer Engineering Capstone
11	6	0	3 years ago	cmips/644	All things related to cMIPS, a synthesizable VHDL model for the 5-stage pipeline, MIPS32r2 core.
10	4	0	3 years ago	acoustic-levitation/645	Acoustic levitation on SoC FPGA (DE0-Nano-SoC). Notice: this repository has moved to GitLab. All issues and pull requests should be created there.
11	3	7	4 months ago	R32V2020/646	My 32-bit RISC CPU for smallish FPGAs
10	8	1	7 years ago	BeMicro-CV/647	A "hello world" style designs for the Cyclone V based $49 Arrow BeMicro CV
10	1	0	5 years ago	1802-pico-basic/648	VHDL 1802 Core with TinyBASIC for the Lattice MachXO2 Pico board
10	7	0	5 years ago	multicore-architecture/649	Simple multicore processor implemented in VHDL
10	4	1	6 years ago	FPGA_Mandelbrot/650	A real-time Mandelbrot fractal viewer for FPGAs
10	6	0	11 years ago	image_processing_examples/651	Examples of image processing
11	5	0	5 years ago	2DImageProcessing/652	2d Images processing system with FPGA (Zynq 7k) from two dragster linescanner (DR-2k-7)
11	0	0	1 year, 7 months ago	OpenTDC/653	Time to Digital Converter (TDC)
10	2	0	8 years ago	zpu-lattice/654	ZPU Core for Lattice ICE40HX8K
10	8	2	8 years ago	VHDL-Project-16-bit-RISC-Processor/655	Designed a RISC processor with 16 bit instruction set, 4-stage pipeline and a non-pre-emptive interrupt handler. Implemented it in VHDL and tested it by simulating in ModelSim.
10	3	0	10 years ago	MIPS/656	A pipelined MIPS processor written in VHDL (Unicamp/MC542)
12	2	1	3 years ago	Tiffany/657	A scalable MachineForth for PCs, MCUs and FPGAs.
10	4	0	6 years ago	VGA_1.0/658	AXI memory-mapped VGA module originally designed for the Avent Zedboard
10	6	0	7 years ago	vhdl-project/659	Implementation in VHDL of the Sobel edge detection operator
10	6	0	5 years ago	vhdl2008c/660	VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl
10	5	0	7 days ago	axi-pcie-core/661	None
11	6	0	6 years ago	hdmi-audio/662	HDMI Audio/Video signal generation for HW emulators of retro comuters
11	13	0	4 years ago	AX7020/663	None
10	2	0	4 years ago	Ultrasound-Beamforming-/664	This project is basically ultrasound Beamformer prototype and FPGA is used to control all the modules of the Hardware.
10	12	0	3 years ago	AD9361_TX_GMSK/665	A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK
10	3	0	4 years ago	snickerdoodle-hls-data-mover/666	A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S defaults to 8 bits and AXI-MM to 64 bits)
10	0	0	4 years ago	VHDLMatrixMultiplier/667	VHDL implementation for a Matrix Multiplier
10	5	0	7 years ago	NfcEmu/668	SDR/FPGA-based NFC/RFID Emulator
10	5	0	2 years ago	de10-nano-examples/669	DE10 Nano Sample Cores
10	2	2	2 years ago	uvvm-tutorial/670	A little tutorial on how to use UVVM (Universal VHDL Verification Methodology).
11	4	1	4 months ago	AtariLynx_MiSTer/671	None
10	3	0	4 years ago	ip_cores/672	Verilog IP Cores & Tests
9	2	0	13 years ago	Pong/673	Pong for Spartan3 FPGA-Board written in VHDL
10	12	7	6 months ago	VIC20_MiSTer/674	Commodore VIC-20 for MiSTer
11	2	0	2 years ago	Zynq_HLS_DDR_Dataflow_kernel_2mm/675	This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
9	3	0	3 months ago	fpga-defender/676	A recreation of Williams Defender 1981 arcade game for DE10-Lite FPGA dev board, written in VHDL.
8	4	1	3 years ago	Nexys-4-DDR-GPIO/677	None
10	13	0	4 years ago	RTL-collection/678	a collection of open sourced VHDL for cryptography
16	5	0	8 months ago	acSLAM/679	FPGA Hardware Implementation for SLAM
9	0	19	28 days ago	universal-IRC-1/680	Universal Industrial Robot Controller. Based on using LinuxCNC in combination with Odrives to create a full control system.
9	0	3	8 months ago	SGen/681	SGen is a generator capable of producing efficient hardware designs operating on streaming datasets. “Streaming” means that the dataset is divided into several chunks that are processed during several cycles, thus allowing a reduced use of resources. The size of these chunks is referred as the streaming width. It outputs a Verilog file that can be used for FPGAs.
8	6	2	10 years ago	ethernet_mac/682	A VHDL implementation of an Ethernet MAC
9	1	0	5 years ago	16x2-LCD-Controller-VHDL/683	A little program I wrote to control the LCD on my FPGA
9	9	0	5 years ago	fpga/684	None
9	2	0	1 year, 6 months ago	PDP-11/685	💻 Simulation for the architecture of a processor inspired by the ideas of PDP-11 processor
9	5	0	6 years ago	pre-mipsfpga/686	Various Verilog examples to gain knowledge and basic skills before working with MIPSfpga
9	8	5	1 year, 6 months ago	dsp-cores/687	Repository containing the DSP gateware cores
9	5	1	5 years ago	Nexys-4-OOB/688	None
12	3	0	2 years ago	erbium/689	Business Rule Engine Hardware Accelerator
9	6	0	4 years ago	bce-fpga-dev-kit/690	bce-fpga-dev-kit
9	8	15	a month ago	PandABlocks-FPGA/691	VHDL functional blocks with their simulations and test sequences
9	4	1	a month ago	AWSteria_Infra/692	"Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)
9	0	0	7 years ago	macMonitor/693	Xilinx VHDL project to drive a Mac Classic CRT
9	1	0	4 years ago	Team-SDK-545/694	An FPGA design project by Kais Kudrolli, Sohil Shah, and DongJoon Park for 18-545 at Carnegie Mellon University.
9	6	3	5 years ago	Zybo-hdmi-in/695	None
9	2	1	1 year, 9 months ago	vhdl-cfg/696	Playground to explore and compare how configuration is handled by different tools for development of VHDL projects
9	2	0	7 years ago	ZPUino_miniSpartn6_plus/697	ZPUino for miniSpartan6+
10	4	0	6 years ago	SNN_vhdl/698	Implementation of an Artificial Neural Network (ANN) on FPGA using VHDL
9	4	0	11 years ago	coded_aperture_vhdl/699	vhdl code for simulating/synthesizing an FPGA backend of a coded aperture
10	5	5	3 years ago	CuckooHashingHLS/700	HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/
9	0	0	3 years ago	vhdllib/701	My own VHDL components library. Anything from a flip flop to an ALU.
9	4	0	7 years ago	rdsfpga/702	RDS FM modulator for FPGA
10	10	0	7 years ago	VHDL_IP-Cores/703	None
9	5	2	7 years ago	riffa/704	RIFFA (Reusable Integration Framework for FPGA Accelerators) is a framework developed in University of California, San Diego. This project utilises the RIFFA framework to define an interface to interact with a user's IP core on the FPGA to send and receive data to and from the PC. This particular project is being developed under Imperial College London.
10	3	0	4 years ago	Arty-Pmod-VGA/705	None
9	0	0	4 years ago	zlogan/706	High-througput logic analyzer for FPGA
10	0	1	3 years ago	PingPongGame_CAD_VGA/707	🏓 A Ping Pong game written in VHDL with VGA support
9	1	1	6 years ago	UART/708	Simple UART implementation in VHDL
9	2	1	4 years ago	FpgaMicrotubule/709	HPC Implementation of dynamic microtubules calculations on CPU, GPU and FPGA Platforms
9	13	0	5 years ago	SDSoC-platforms/710	SDSoC platforms for Digilent Zynq boards
9	0	4	7 years ago	tis100cpu/711	TIS-100 CPU in VHDL
9	6	17	8 years ago	ECE383/712	USAFA ECE383 course website.
8	3	0	3 years ago	robotter/713	Rob'Otter's code for Eurobot and the Coupe de France de robotique
9	1	0	3 years ago	DDS/714	A DDS core written in VHDL.
9	0	0	a month ago	RGH1.2-V2-Slim/715	RGH1.2 V2, Slim Version, using my new PLL point
9	1	0	4 years ago	MIST_C64/716	FPGA implementation of a Commodore 64
9	2	0	3 years ago	Nexys-A7-100T-GPIO/717	None
9	1	0	2 years ago	LSTM_FPGA/718	~ Implementation of LSTM ANN in FPGA with VHDL
8	1	0	1 year, 8 months ago	prjct_ComputerArchitecture/719	计算机系统结构实验
10	6	0	5 years ago	GBA/720	GameBoy Advance Zedboard Implementation
9	4	0	1 year, 5 months ago	CrowdSupplyWorkShop1/721	None
9	15	0	9 years ago	VinxFs/722	Small FAT16/FAT32 filesystem for ATMega8 (AVR / STM / PIC) with create/delete file
10	2	0	3 years ago	100cerebros/723	Resoluções de exercícios e guiões de diversas disciplinas de MIECT, na UA
9	2	0	9 years ago	vhdl-svf/724	SVF (Serial Vector Format) interpreter to control a JTAG TAP
9	2	0	3 years ago	Architecture-of-CPU-projects/725	VHDL , ModelSIM, Quartus, FPGA, Image Processing
9	3	1	3 years ago	DivMMC/726	The original DivMMC interface for the Sinclair ZX Spectrum
9	2	0	4 years ago	Bitmap-VHDL-Package/727	A vhdl package for reading and writing bitmap files.
9	1	2	a day ago	zest/728	Implementation of an Atari ST in VHDL for Xilinx-based FPGAs
9	2	0	2 years ago	udp_ip_stack/729	UDP IP stack example project from this VUnit getting started blog (https://www.linkedin.com/pulse/vunit-best-value-initial-effort-lars-asplund)
11	4	1	11 months ago	tdd-intro/730	Example of Test Driven Design with VUnit
12	6	0	5 months ago	LWC/731	Development Package for the Hardware API for Lightweight Cryptography
9	2	0	4 years ago	GNSS-VHDL/732	GNSS codes and signal generation for VHDL. GPS (L1 C/A, L5), Galileo (E1OS, E5). Includes Xilinx ISE testbench and wave configuration files.
9	0	0	4 years ago	courses/733	About university courses and homeworks ...
9	9	1	1 year, 7 months ago	go2uvm/734	Main repo for Go2UVM source code, examples and apps
9	5	0	10 years ago	simple-mips/735	Simple MIPS processor written in VHDL
9	8	0	6 years ago	wavelet-image-compression/736	Simple FPGA-based Wavelet Image Compression
10	5	1	4 years ago	ultrasonic-levitation-with-Xilinx-Zynq/737	This github contains the Vivado project, PCB schematic and control software for levitation framework at Bristol University
9	2	0	2 years ago	CycloneV_UnAmiga_v2/738	Cyclone V FPGA board for UnAmiga project with new addon 6 Buttons Megadrive Joystick
9	1	1	2 years ago	A-simple-MIPS-CPU/739	重庆大学2017级硬件综合设计，一个MIPS CPU的简单实现
9	2	3	2 years ago	SAMCoupe_MIST/740	SAM Coupe for MiST board
9	2	0	1 year, 3 months ago	b01lers-library/741	None
9	4	0	11 years ago	z80soc/742	Z80 System on Chip
9	8	1	2 years ago	capi2-bsp/743	CAPI 2.0 Board Support Package
9	3	0	5 years ago	msgpack-vhdl/744	MessagePack implementation for VHDL
11	8	11	9 months ago	Intv_MiSTer/745	Intellivision for MiSTer
9	0	0	6 months ago	ECP5_PCIE_Analyzer/746	None
9	0	1	2 years ago	vhsnunzip/747	Hardware Snappy decompressor
8	1	0	8 years ago	i2s-interface-vhdl/748	A simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.
9	1	0	3 years ago	I2S_sender/749	VHDL I2S transmitter
9	0	1	1 year, 4 months ago	t80/750	Configurable cpu core that supports Z80, 8080 and gameboy instruction sets.
8	2	0	3 months ago	NexysPsram/751	AXI PSRAM Controller IP for use with Digilent Nexys 4
8	2	0	5 years ago	SHA-256-HDL/752	An implementation of original SHA-256 hash function in (RTL) VHDL
8	8	1	3 years ago	mining-shell/753	Development shell repo for creation of fpga bitstreams
8	4	2	3 years ago	pim-vhdl/754	My VHDL code
8	0	0	3 years ago	adc_configurator/755	ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
8	0	0	3 years ago	Computer-Organization-and-Architecture-Course-Design/756	这是东南大学信息学院本科三年级开设的计算机组织与结构课程的后续配套实验课程，包含POC设计和简单CPU设计。以下是我与小组完成的POC与CPU的设计，采用vivado2018.2的设计环境。
8	8	0	8 years ago	FPGA_ADC/757	Interface the AD9057 with a cyclone III FPGA
7	4	0	5 years ago	ADC_LCD_FPGA/758	ADC & LCD Interfacing using Verilog & VHDL
7	2	0	8 years ago	vhdl-game-engine/759	A game engine implemented purely in hardware using the VHDL language
8	1	0	5 years ago	SimpleComputer/760	The design and implementation of simple computer by quartus.
10	4	0	2 years ago	vercolib_pcie/761	VHDL PCIe Transceiver
12	5	0	2 years ago	tk90x_ula/762	ULA do TK90X/TK95 clonada em CPLD
8	1	0	11 months ago	tictactoe/763	The tictactoe game made in VHDL.
8	3	0	a month ago	HCMUT_DD_Lab/764	My attempts at all assignments from HCMUT's Digital Design Laboratory course (EE2420) this year (K20)
8	3	1	3 days ago	rggen-sample-testbench/765	None
8	1	0	4 years ago	blake2/766	VHDL implementation of BLAKE2 cryptographic hash and message authentication code (MAC)
8	1	0	11 years ago	CPLD_USBHxCFloppyEmulator/767	CPLD USB HxC Floppy Emulator
8	2	0	6 months ago	blp/768	Blinking Led Project
8	5	0	7 years ago	1553-Firmware/769	Contains VHDL implementing an 8085, Holt HI-6130 1553 IC, and Memory. Also includes firmware used to demo the system.
8	4	1	6 years ago	ece5775-final/770	Voice Recognition using FPGA-Based Neural Networks
8	0	0	3 years ago	Arty-Z7-20-OOB/771	None
8	3	0	1 year, 6 months ago	chisel-study/772	ハードウェア構築言語Chiselでちょっとしたコードを書き溜めておくプロジェクト
8	0	2	2 years ago	big80/773	FPGA Implementation of a TRS-80 Model 1
8	1	0	2 years ago	snes_cic_fpga/774	snes cic implementation with FPGA FireAnt board
8	2	0	3 months ago	IPDBG/775	IPDBG
8	1	0	11 days ago	a2i/776	The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
8	1	0	1 year, 10 months ago	MasterThesis/777	VHDL implementation of a customizable CNN
9	2	0	2 years ago	vhdl-axis-uart/778	UART to AXI Stream interface written in VHDL
9	2	0	1 year, 11 months ago	A500-EXT-CFIDE/779	None
12	1	0	4 months ago	BMSTU/780	None
8	4	0	5 years ago	mips--/781	A dual core MIPS subset CPU written in behavioral, synthesizable VHDL
8	0	0	8 months ago	risc63/782	Custom 64-bit pipelined RISC processor
8	7	0	8 years ago	fpga-sdr-platform/783	FPGA SDR platform: AD9963 + XC6SLX9 + CY7C68013
8	3	0	6 months ago	VhdI2CSlave/784	I2C Slave Interface (Vhdl)
9	3	2	6 years ago	oram_fpga/785	FPGA related files for ORAM
8	3	0	1 year, 1 month ago	theremin/786	Open source digital FPGA based theremin project
9	6	0	2 years ago	MIPS-Processor-VHDL/787	Emulation of a 32-bit MIPS processor on Artix-7 FPGA using VHDL. The emulated MIPS processor is tested by executing RC5 encryption and decryption algorithms.
8	1	0	3 years ago	PIC16C6XX/788	Original Xbox SMC Power Glitching Attack (WIP)
8	6	0	7 years ago	montecarlo-fpga/789	Black-Scholes style options pricing using Monte Carlo methods. Written in VHDL for the Cyclone IV FPGA board.
8	1	0	7 years ago	PothosFPGA/790	Pothos FPGA computational offload and buffer integration support
8	8	2	10 months ago	Arcade-Defender_MiSTer/791	Arcade: Defender for MiSTer
8	0	1	2 years ago	posit_blas_hdl/792	Posit Arithmetic Accelerator interfacing with Apache Arrow & CAPI SNAP
8	0	0	2 years ago	tangnano_sample/793	Tang-nano LCD sample
8	11	0	5 years ago	WM8731-Audio-codec-on-DE10Standard-FPGA-board/794	None
8	2	1	9 years ago	gbcpu/795	A CPU and peripherals implementing the Gameboy (TM) instruction set and functionality
8	1	0	2 years ago	Minisys-1_CPU/796	东南大学-计算机系统综合设计 Minisys-1
8	1	2	2 months ago	ss/797	SparcStation
8	55	0	6 years ago	ORCA-risc-v/798	RISC-V by VectorBlox
8	0	0	1 year, 6 months ago	8-bit-Computer/799	Implementation of an 8-bit computer in VHDL, along with a minimal assembler
8	5	0	9 years ago	soc_leon3/800	System on Chip SPARC V8 using leon3 CPU by Gaisler. C++, vhdl, v files.
8	0	0	3 years ago	SoC-Nios/801	Building an example System on Chip (SoC) using Nios II processor.
10	12	2	2 years ago	SPI-FPGA-VHDL/802	SPI Master and Slave components to be used in all of FPGAs, written in VHDL.
9	1	0	7 years ago	AM2901/803	None
8	6	0	2 years ago	Zedboard-DMA/804	None
9	13	0	4 years ago	AX7015/805	AX7015
8	0	0	1 year, 7 months ago	2021_CQU_NSCSCC/806	2021_CQU_NSCSCC_RTL_CODE
8	8	5	2 months ago	aws-fpga-firesim/807	AWS Shell for FireSim
8	3	0	2 years ago	xdma_dsc_byp_cltr/808	VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe
8	4	1	4 days ago	CoreAmstrad/809	CoreAmstrad source code, a physical clone of Amstrad from JavaCPC Markus's emulator, currently running on a final FPGA end-user platform : MiST-board.
8	5	0	8 years ago	mbc5-clone/810	this is a clone of zakos mbcx found at https://gitorious.org/mbcx/mbcx. I'll try to make my own itteration of the mbcx.
8	14	0	3 years ago	GlobalCorrelator/811	Firmware for Level-1 Particle Reconstruction
8	3	0	2 years ago	Zybo-Linux/812	A complete Linux project for the ZYBO. This project helps me during my first steps with embedded Linux. You can find anything necessary to run your own embedded Linux on your ZYBO here.
8	11	2	a month ago	Arcade-Xevious_MiSTer/813	Arcade: Xevious for MiSTer
8	1	0	5 years ago	Template-Matching-FPGA/814	None
8	2	0	7 years ago	hls_stream/815	Xilinx HLS video library using hls::stream w/ Vivado 2014.4 or Later
8	0	0	9 years ago	rekonstrukt/816	FPGA based Forth development environment / Forth based FPGA development environment
9	2	0	5 years ago	ws2812b-vhdl/817	A controller for the WorldSemi WS2812B RGB LEDs written in plain VHDL.
8	16	1	2 years ago	KC705-AD9371/818	The implementation of AD9371 on KC705
8	0	0	2 years ago	MiSTer-Arcade-AtariTetris/819	FPGA implementation of ATARI's Tetris arcade game
8	0	0	2 years ago	nyfi64/820	A wireless N64 controller adapter.
8	15	0	6 years ago	xapp1026/821	LightWeight IP Application Examples for Xilinx FPGA
9	2	2	6 years ago	VHDL-FIR-filters/822	Synthesizable FIR filters in VHDL
8	1	0	5 years ago	bcomp/823	8-bit computer
8	0	0	4 months ago	MicroCodeCompiler/824	https://hackaday.io/project/172073-microcoding-for-fpgas
9	4	1	3 months ago	hdl_string_format/825	VHDL package to provide C-like string formatting
8	18	2	5 years ago	NexysVideo/826	None
9	4	0	7 years ago	AVR-Processor/827	VHDL implementation of an AVR processor.
8	2	0	7 years ago	dmkonst/828	An optimized pipelined MIPS CPU written in VHDL
8	4	0	6 years ago	zybo-examples/829	A series of examples on zybo board for my blog tutorials.
8	3	0	8 months ago	cjtag_bridge/830	🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
8	3	0	6 months ago	PC88_MiSTer/831	NEC PC8801 MKII SR For MiSTer
8	2	0	6 years ago	MT32_Rand_Gen/832	Mersenne Twister Pseudo Random Number Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).
8	1	0	6 years ago	65816_Interface_System/833	Soft Core of 65816 in VHDL
9	1	0	9 years ago	Mandelbrot-VHDL/834	Mandelbrot Set in VHDL targetting the Cyclone IVE found on a DE2-115 board.
8	3	0	4 years ago	FPGA_Harris_Corner/835	An efficient FPGA implementation of the Harris Corner feature detector
8	1	1	1 year, 8 months ago	vhlib/836	Package of miscellaneous VHDL libraries
10	5	0	2 years ago	UVVM_Community_VIPs/837	Repository for the UVVM community to share VIPs. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
8	0	0	2 years ago	CQU_Computer_Organization/838	重庆大学计组实验vivado工程文件+项目汇编语言
10	2	0	1 year, 10 months ago	xvcSupport/839	None
8	0	0	8 months ago	circuit/840	Some circuit homework VHDL shit code
8	4	0	6 years ago	vhdI2CMaster/841	I2C Master FSM (vhdl)
8	6	0	5 years ago	VHDL/842	Some VHDL code
8	1	1	3 years ago	pipemania-fpga-game/843	Pipe Mania - Game for FPGA written in VHDL
8	6	0	8 years ago	lzw_verilog/844	LZW Compressoion algorithm in verilog
8	7	0	8 years ago	SpaceWireRouterIP_6PortVersion/845	None
8	6	1	7 years ago	OLED_on_ZedBoard/846	OLED test code from Digilink modified to work on the Zedboard
8	11	4	11 months ago	Arcade-BombJack_MiSTer/847	Arcade: Bomb Jack for MiSTer
8	11	14	10 months ago	Arcade-IremM62_MiSTer/848	Irem62 from pace, and mist including Lode Runner, etc
8	5	0	4 years ago	8bit_sar_adc/849	Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC
8	0	4	2 years ago	fpga_lib/850	Library of utilities such as cores, procedures and functions, commonly shared between FPGA projects.
8	2	1	6 years ago	gpib/851	IEEE-488 (GP-IB, HP-IB) synthesizable core in VHDL
10	2	0	1 year, 27 days ago	log-arithmetic/852	This is a repository for logarithmic Functional Units
11	4	0	4 months ago	Async-Click-Library/853	None
8	2	0	4 years ago	CPU-ARM/854	Design and implementation of a complete ARM based CPU.
8	3	2	8 days ago	vhdl-linter/855	None
8	6	3	a day ago	Oric_Mist_48K/856	Oric Atmos Mist core
7	0	0	11 years ago	Brainfuck-Processor/857	A simple brainfuck processor implemented in VHDL.
7	2	0	5 years ago	USTC-tMIPS/858	None
7	4	0	3 years ago	Circuitos_Reconfiguraveis/859	Repositório da disciplina de Projeto com Circuitos Reconfiguráveis do curso de Engenharia Eletrônica da Faculdade UnB Gama.
7	6	0	2 years ago	pipelineCPU/860	Five-Stage Pipeline CPU Implemented by Verilog on FPGA Written By LI Shuai, it supports static and dynamic pipeline cpu. I am not maintaining this repo for years. If there are bugs when you try it, debug by youself! :)
8	0	0	7 months ago	demomachine/861	Simple architecture to make demos on a FPGA
7	12	0	2 years ago	fpga_cyclone4/862	正点原子开拓者&新起点FPGA开发板例程
7	4	0	3 years ago	Ultra96V2_DisplayPort/863	Bare Metal Display Port Example for the Ultra96 V2
7	4	0	7 months ago	Flo-Posit/864	Posit Arithmetic Cores generated with FloPoCo
7	0	0	4 days ago	GettingStarted_Examples/865	This repository contains a collection of reference designs and software application to get starter with Accelize Distribution Platform
7	0	0	7 years ago	TicksPicker/866	Tiny VHDL postbit length extractor
8	1	0	12 years ago	sdram_controller/867	Scratch DDR SDRAM Controller
8	0	0	5 years ago	VHDL/868	Everything related to VHDL design. Image Filters, PS/2 Keyboard Controller, VGA Controller...
7	3	1	3 years ago	Space-Invaders-for-MiSTer/869	None
8	1	0	4 years ago	MBCx/870	Gameboy MBC5 mapper chip clone in programmable logic.
7	2	0	5 months ago	PipeWork/871	Pipework components is VHDL library for NoC(Network on Chip).
8	3	0	2 years ago	rmii-firewall-fpga/872	RMII Firewall FPGA
7	2	0	29 days ago	DesignStartTrace/873	Adding trace to DesignStart for easier side-channel analysis on the CW305 target. Also supports PhyWhisperer.
6	3	0	9 years ago	Plong/874	Simple pong implementation in vhdl
7	2	0	6 years ago	FPGA_Flappy_Bird/875	🐦 a simple hardware-implementation of the viral game "Flappy Bird" built for use on the Digilent NEXYS 2 Development Board (XC3S500E-FG320)
7	2	0	11 years ago	usb11_phy_translation/876	USB 1.1 PHY (VHDL)
7	3	0	7 years ago	Stepper-Motor-Control/877	System on a Chip - Design for a stepper-motor-control with NIOS II/s µC on Cyclone IV/V FPGA
7	5	0	9 years ago	vhdl-examples/878	VHDL example code
7	8	0	5 years ago	beginning-fpga-programming-metal/879	Source code for 'Beginning FPGA: Programming Metal' by Aiken Pang and Peter Membrey
7	3	0	a month ago	ira/880	SISO vector decoder for IRA-LDPC codes in VHDL
6	2	0	9 years ago	sigma_delta_dac_dual_loop/881	2nd order Sigma-Delta DAC
7	3	0	9 years ago	FIX/882	FIX for (High Frequency Trading) HFT
7	0	0	5 years ago	UART_in_VHDL/883	My successful first experiment in VHDL - creating my own UART
7	5	0	4 years ago	ZYBO_IoT_Vivado/884	This is a Vivado project to create an IoT device with ZYBO (Zynq).
7	1	0	1 year, 3 months ago	sdram-tester-fpga/885	SDRAM Tester implemented in FPGA
9	4	0	1 year, 5 months ago	MIPS_0_to_54/886	Project for CS101016 and CS100160, Tongji University. Use Verilog HDL to build a CPU.
7	3	0	11 months ago	OCOWFC/887	Open-Channel Open-Way Flash Controller
7	8	2	9 days ago	c64/888	C64 core
8	9	0	6 years ago	Zynq-Configuration-Controller/889	A configuration controller solution allowing a Zynq device to configure downstream FPGAs
7	1	0	5 years ago	present-vhdl/890	Implementation of the PRESENT lightweight block cipher in VHDL.
7	0	0	5 years ago	SAYEH-Cache/891	implementing SAYEH cache using VHDL
7	4	1	7 years ago	mz80b_de0/892	MZ-80B/MZ-2000 series implementation for Altera DE0 board
8	1	1	3 years ago	fpga_mpu401/893	MPU-401 Implementation on FPGA. Based on the System68 CPU core by John E. Kent.
8	1	0	7 years ago	speccy-wxeda/894	Порт конфигурации Reverse u16_speccy на плату ZrTech WXEDA
7	3	0	4 months ago	mdsynth/895	FPGA-based synthesizer in VHDL for the Xilinx Spartan-3A and Spartan-3E Starter Kits
8	5	0	13 years ago	fpu_double/896	FPU Double VHDL
7	2	1	3 years ago	Bonfire/897	A implementation of a NoC router with credit based flow control
9	15	11	3 months ago	Arcade-Scramble_MiSTer/898	Arcade: Scramble for MiSTer
7	3	0	4 years ago	fpga-mmu/899	internship
7	2	0	2 years ago	ultrasonic-sensor/900	Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.
7	3	0	8 years ago	CPME48/901	Why CP-YOU? Let's CP-ME! 非常简单的8位CPU的VHDL实现，拥有精简的RISC式指令集。更有配套扩展指令集IR48*、汇编器DASM48、高级语言Cheme，你值得拥有。（课程作业，仅供交流，切勿抄袭！）
7	1	1	8 years ago	Guimauve2ooo/902	VGA output for Apple //c computers
8	8	0	2 years ago	SDAccel/903	SDAccel: Architecture to enable CPU/GPU developers to easily migrate their applications to FPGAs while maintaining and reusing their OpenCL, C, and C++ code in a familiar workflow.
7	4	0	4 years ago	reloc/904	Designing Relocatable FPGA Partitions with Vivado Design Suite
7	11	0	2 years ago	Amstrad_MiST/905	None
7	1	1	3 years ago	Basys3-Pulse-Generator/906	Pulse generator on Basys 3 FPGA board
7	1	1	1 year, 15 days ago	yaaes/907	Yet Another AES implementation in hardware.
7	2	0	7 years ago	simon_vhdl/908	VHDL implementations of various architectural designs of the SIMON 64/128 block cipher
7	2	0	3 years ago	128bit-prng/909	[128bit] PRNG Using LFSRs (Linear-feedback Shift Register)
7	2	0	2 years ago	Realtime-objects-remover-in-FullHD-videos/910	Project for Innovate FPGA 2019
9	7	0	7 years ago	minispartan6/911	Projects for the Scarab Minispartan6+ FPGA board
7	0	0	5 years ago	MyRISC/912	VHDL implementation of a 16-bit RISC processor targeting the BASYS3 FPGA
7	5	0	6 years ago	aes-dom/913	DOM Protected Hardware Implementation of AES
8	6	0	10 years ago	grlib/914	None
7	9	0	7 years ago	TE0720-GigaZee-Reference-Designs/915	Reference Projects for TE0720 ZYNQ module
7	5	0	2 years ago	Gr0estl-Miner/916	Gr0estl mining algo FPGA implementation by AtomMiner
8	1	0	1 year, 7 months ago	myCPU/917	make a simple mips CPU
7	4	1	3 years ago	FPGA_1942/918	FPGA 1942 arcade game
6	9	0	6 years ago	DE1-SoC-HPSFPGA/919	Image to column FPGA implementation (im2col by caffe)
7	4	0	10 years ago	umn_simaudio/920	Univ. of MN Simultaneous Audio Recording Interface Software and Firmware
7	4	2	5 years ago	C64_MIST/921	None
7	0	0	2 years ago	VHDL-LAB/922	Some basic electronic structures implemented in VHDL
7	0	0	9 months ago	design-for-mult-cycle-CPU-in-verilog/923	None
7	3	0	2 years ago	Image-Generator-for-FPGA-Evaluation-Board/924	Design of an image generator to represent a street scene. Can be used as a stand-alone design for image generator or as a test pattern generator for a lane detection circuit.
7	3	0	9 years ago	busblaster_v4/925	CPLD designs for the BusBlaster v4 from Dangerous Prototypes
7	1	2	9 years ago	S76D/926	Singing Very High Speed Integrated Circuit Hardware Description Language Board
7	2	0	4 years ago	fpga_fifo/927	Asynchronous FIFO for FPGAs
7	1	0	3 years ago	OscilloscopeBoom/928	Display something on an analog oscilloscope
7	3	2	3 years ago	fast-p2a/929	None
9	4	0	1 year, 6 months ago	apple2fpga/930	port of Stephen A. Edwards apple2fpga to ULX3S
8	4	0	9 months ago	CNNA/931	A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
7	3	0	2 years ago	Hardware-Course/932	All the verilog code I wrote in hardware Course
8	3	0	3 years ago	Arty-A7-100-GPIO/933	None
7	1	0	1 year, 3 months ago	8_bit_cpu/934	None
8	2	0	7 years ago	ghdl/935	A mirror of GHDL - a VHDL language front-end for GCC and LLVM
7	1	0	8 years ago	vhdl/936	This repository contains the codes for various type of circuits simulated in VHDL in Xilinx ISE Design.
7	2	0	6 years ago	ipxact/937	IP-XACT XML binding library
8	1	0	5 years ago	tinycomputer/938	Tiny 4-bit CPU using AMD2901 bit slice (https://github.com/Amrnasr/AM2901) and program memory initialized from a file
8	1	5	5 years ago	ProjectZ/939	Attempt to implement MultiLayer Perceptron in hardware descriptive language like VHDL.
7	2	0	8 months ago	Canvas/940	Graphical environment for Digital Signal Processing
8	2	3	6 months ago	stdcores/941	Standard and Curated cores, tested and working.
7	5	0	8 years ago	yac/942	YAC - Yet Another CORDIC Core
8	1	0	2 years ago	rc2014_fpga/943	A VHDL emulation of the RC2014 Z80 SBC
7	6	0	1 year, 7 months ago	mrf-openevr/944	Open source Event Receiver implementation
7	6	2	2 months ago	colecofpga/945	Colecovision FGPA port from old PACE project.
6	7	1	2 years ago	HDL/946	None
7	0	0	8 years ago	vhdl-simple-processor/947	Implementation of a simple processor using VHDL for logic synthesis in FPGA
7	0	0	10 years ago	BLOB-Detection/948	Blob Detection in HDL
7	4	0	7 years ago	hardware-traffic-generator/949	10 Gbit/s flexible and extensible Ethernet FPGA-based traffic generator
7	2	0	5 years ago	ftdi-async-fifo/950	FTDI FT2232H Asynchronous FIFO communication with FPGA over USB
7	4	1	5 years ago	6.111-Final-Project/951	None
7	14	6	2 months ago	ColecoVision_MiSTer/952	ColecoVision for MiSTer
7	4	5	a month ago	SharpMZ_MiSTer/953	Sharp MZ Series Personal/Business Computer Emulator for FPGA
7	4	1	6 years ago	Petalinux-on-Zedboard-camera-streaming/954	None
7	5	4	6 years ago	purisc/955	Pipelined Ultimate Reduced Instruction Set Computer
7	7	0	8 years ago	SpaceWireRMAPTargetIP/956	None
7	1	0	6 years ago	scanline-stereo-vision-FPGA/957	Implementazione VHDL dell’algoritmo Scanline
7	1	0	3 years ago	fp23_logic/958	Floating point FP23 core on VHDL. For Xilinx FPGAs. Include base converters and some math functions.
10	4	0	2 years ago	Verilog_Module/959	常用Verilog模块
7	0	0	7 months ago	VHDL-Verilog-Coding/960	None
10	1	0	5 months ago	ZynqMP-ACP-Adapter/961	Xilinx ZynqMP AXI-ACP Adapter
7	0	0	1 year, 8 months ago	VHDLExamples/962	VHDL examples.
7	2	1	3 years ago	CNN-for-modulation-recognition-based-on-FPGA/963	None
7	9	0	8 years ago	fpga/964	This repository holds all the projects and docs relating to our work with the Xilinx Zynq 7000 series FPGAs.
8	1	0	4 years ago	iir-audio-filter-fpga/965	Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA
7	0	0	2 years ago	Basic-Computer-design/966	A Computer description using VHDL and ModelSim software
8	4	0	5 years ago	parti-fpga/967	FPGA-based data partitioning
7	3	0	5 years ago	grlib/968	Files from http://www.gaisler.com/index.php/downloads/leongrlib
7	3	0	8 months ago	paranut/969	The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
7	6	0	7 years ago	Papilio-Schematic-Library/970	A library of Soft Processors and peripherals that can be used with Webpack schematic editor to build a custom SOC for the Papilio
8	7	0	2 years ago	SHA-256/971	An SHA-256 module implementation in VHDL. Based on NIST FIPS 180-4.
8	3	0	5 years ago	FPGADisplay-ipcore/972	FPGA VGA Display Handler - IP Core Repository
7	6	0	4 years ago	Kalman-Filter-verilog/973	Hey guys this the project where i have implemented the Kalman filter for MPPT for solar PV module
7	1	0	4 years ago	mastermind/974	FPGA implementation of the popular logic game using VHDL and Altera DE1
10	1	0	8 months ago	rv16poc/975	16 bit RISC-V proof of concept
8	7	1	2 years ago	LimeNET-Micro_GW/976	Intel MAX10 FPGA project for the LimeNet-Mini board
7	0	0	1 year, 7 months ago	MO_MiSTer/977	None
7	11	2	5 years ago	Zybo-hdmi-out/978	None
7	1	0	6 years ago	2D-Image-Filtering-on-FPGA/979	None
8	8	0	12 years ago	openjtag-project/980	Open JTAG project
8	0	0	9 years ago	kanto/981	Kanto Audio Player
7	3	0	8 years ago	altera_de1_labs/982	My solutions for the Altera DE1's labs in VHDL
7	2	0	4 years ago	POV/983	13113112bit 16FPS POV Display
9	0	0	11 months ago	multi-TB-progetto-Reti-PoliMi/984	Test bench di test automatico per la prova finale del corso di Reti Logiche al Politecnico di Milano, anno 2019/2020.
7	3	25	2 years ago	FPGA_MNIST/985	None
14	8	1	1 year, 3 months ago	Hardware-Zstd-Compression-Unit/986	None
7	7	3	5 months ago	psi_fix/987	Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
7	5	0	6 months ago	kvcordic/988	Multi-function, universal, fixed-point CORDIC
7	1	0	8 months ago	Gaussian-Filter-with-VHDL-to-Blur-Images/989	None
7	1	0	1 year, 7 months ago	Parallel-FIR-Filter/990	VHDL implementation of a parallel FIR filter
6	5	0	6 years ago	xilinx-zynq-zc702-linuxapplication/991	Linux application and Device driver porting on Xilinx Zynq ZC702 board
7	3	0	9 years ago	bf_cpu/992	Brainfuck microprocessor
8	5	0	3 years ago	ustogo-lsi/993	The repository includes two main directories; (i) "ustogo": for our complete ultrasound processing pipeline (Matlab-based), and (ii) "fpgabeamformer": for the single-FPGA 3D/2D ultrasound digital imager; hardware side (Vivado designs) and software side (Xilinx SDK applications + visual studio GUI).
6	26	3	6 years ago	vhdl-exercise/994	A little exercise for VHDL newbies
6	2	0	5 years ago	ECE368-Lab/995	ECE368
6	0	1	5 years ago	VDHL-SD-Library/996	A VHDL-Library for reading a SD-Card with a FPGA in a small test project
6	0	0	4 years ago	super-duper-nes/997	Super-duper NES project!
8	2	0	5 years ago	Rotary-encoder-VHDL-design/998	VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
6	0	6	3 years ago	OS2018spring-projects-g05/999	Dual-core MIPS CPU SoC
8	1	0	7 years ago	zx-ula-wxeda/1000	ZX Spectrum 48k with ULAPlus