README-Verilog.md

This is a most popular repository list for Verilog sorted by number of stars

STARS	FORKS	ISSUES	LAST COMMIT	NAME/PLACE	DESCRIPTION
2096	558	45	7 months ago	picorv32/1	PicoRV32 - A Size-Optimized RISC-V CPU
2096	910	33	1 year, 4 months ago	e200_opensource/2	Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
1582	520	20	7 months ago	wujian100_open/3	IC design and development should be faster，simpler and more reliable
1339	496	194	4 years ago	hw/4	RTL, Cmodel, and testbench for NVDLA
1218	418	64	29 days ago	verilog-ethernet/5	Verilog Ethernet components for FPGA implementation
1001	1265	24	a day ago	hdl/6	HDL libraries and projects
958	76	2	9 months ago	amiga2000-gfxcard/7	MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog
925	245	53	6 days ago	corundum/8	Open source FPGA-based NIC and platform for in-network compute
885	113	1	6 months ago	zipcpu/9	A small, light weight, RISC CPU soft core
838	254	31	a month ago	oh/10	Verilog library for ASIC and FPGA designers
800	125	13	15 days ago	serv/11	SERV - The SErial RISC-V CPU
757	209	10	4 years ago	miaow/12	An open source GPU based off of the AMD Southern Islands ISA.
755	214	0	25 days ago	basic_verilog/13	Must-have verilog systemverilog modules
716	367	9	3 years ago	ODriveHardware/14	High performance motor control
701	264	21	7 months ago	verilog-axi/15	Verilog AXI components for FPGA implementation
698	560	65	a month ago	uhd/16	The USRP™ Hardware Driver Repository
682	245	115	3 days ago	OpenLane/17	OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
635	171	13	22 days ago	openc910/18	OpenXuantie - OpenC910 Core
630	113	23	a month ago	vortex/19	None
604	215	122	2 hours ago	OpenROAD/20	OpenROAD's unified application implementing an RTL-to-GDS Flow
590	173	4	2 years ago	open-fpga-verilog-tutorial/21	Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
589	139	6	11 months ago	riscv/22	RISC-V CPU Core (RV32IM)
547	99	24	2 months ago	apio/23	🌱 Open source ecosystem for open FPGA boards
526	165	11	9 days ago	verilog-pcie/24	Verilog PCI express components
517	182	7	5 months ago	e203_hbirdv2/25	The Ultra-Low Power RISC-V Core
509	80	45	9 days ago	microwatt/26	A tiny Open POWER ISA softcore written in VHDL 2008
505	92	4	2 years ago	LeFlow/27	Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
485	240	40	5 years ago	riffa/28	The RIFFA development repository
485	103	54	1 year, 21 days ago	sd2snes/29	SD card based multi-purpose cartridge for the SNES
480	182	1	4 years ago	mips-cpu/30	MIPS CPU implemented in Verilog
433	81	13	11 months ago	biriscv/31	32-bit Superscalar RISC-V CPU
425	106	2	1 year, 20 days ago	step_into_mips/32	一步一步写MIPS CPU
424	160	3	1 year, 1 month ago	cores/33	Various HDL (Verilog) IP Cores
423	87	23	8 months ago	riscv-formal/34	RISC-V Formal Verification Framework
399	128	0	4 years ago	verilog/35	Repository for basic (and not so basic) Verilog blocks with high re-use potential
395	134	32	3 months ago	mor1kx/36	mor1kx - an OpenRISC 1000 processor IP core
393	155	3	2 months ago	openwifi-hw/37	open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
391	186	1	7 years ago	FPGA-Imaging-Library/38	An open source library for image processing on FPGA.
369	50	5	8 months ago	VerilogBoy/39	A Pi emulating a GameBoy sounds cheap. What about an FPGA?
363	17	5	11 days ago	graphics-gremlin/40	Open source retro ISA video card
344	29	69	5 months ago	ucr-eecs168-lab/41	The lab schedules for EECS168 at UC Riverside
337	122	47	24 days ago	OpenTimer/42	A High-performance Timing Analysis Tool for VLSI Systems
326	119	0	a month ago	Verilog-Practice/43	HDLBits website practices & solutions
317	141	16	10 years ago	netfpga/44	NetFPGA 1G infrastructure and gateware
313	69	13	a month ago	litepcie/45	Small footprint and configurable PCIe core
305	67	3	2 months ago	wb2axip/46	Bus bridges and other odds and ends
304	114	12	8 months ago	fpu/47	synthesiseable ieee 754 floating point library in verilog
302	122	19	4 years ago	convolution_network_on_FPGA/48	CNN acceleration on virtex-7 FPGA with verilog HDL
301	103	7	3 years ago	icezum/49	🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board
298	62	173	25 days ago	basejump_stl/50	BaseJump STL: A Standard Template Library for SystemVerilog
291	9	3	26 days ago	vroom/51	VRoom! RISC-V CPU
288	74	105	5 days ago	CFU-Playground/52	Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online workshop: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
279	117	4	1 year, 2 months ago	verilog-i2c/53	Verilog I2C interface for FPGA implementation
275	35	22	2 years ago	spispy/54	An open source SPI flash emulator and monitor
274	87	3	4 years ago	CNN-FPGA/55	使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用
270	125	8	8 years ago	FPGA-Litecoin-Miner/56	A litecoin scrypt miner implemented with FPGA on-chip memory.
261	41	9	1 year, 1 month ago	Project-Zipline/57	Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.
258	42	14	6 months ago	Piccolo/58	RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
257	80	1	6 months ago	verilog-6502/59	A Verilog HDL model of the MOS 6502 CPU
256	64	2	4 years ago	zet/60	Open source implementation of a x86 processor
252	38	1	a month ago	USB_C_Industrial_Camera_FPGA_USB3/61	Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
248	86	1	2 years ago	AccDNN/62	A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
241	95	7	1 year, 7 months ago	verilog-uart/63	Verilog UART
240	39	5	2 days ago	apicula/64	Project Apicula 🐝: bitstream documentation for Gowin FPGAs
231	68	11	3 months ago	icesugar/65	iCESugar FPGA Board (base on iCE40UP5k)
231	49	1	5 years ago	ridecore/66	RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
230	76	15	6 months ago	Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/67	Verilog Generator of Neural Net Digit Detector for FPGA
222	62	22	10 years ago	fpga_nes/68	FPGA-based Nintendo Entertainment System Emulator
221	77	1	6 months ago	sha256/69	Hardware implementation of the SHA-256 cryptographic hash function
219	125	8	5 days ago	openofdm/70	Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
242	22	0	1 year, 2 months ago	vdatp/71	Volumetric Display using an Acoustically Trapped Particle
212	82	1	5 years ago	sdram-controller/72	Verilog SDRAM memory controller
208	61	104	Unknown	f4pga-examples/73	Example designs showing different ways to use F4PGA toolchains.
207	79	7	4 months ago	SCALE-MAMBA/74	Repository for the SCALE-MAMBA MPC system
205	187	0	8 months ago	fpga/75	The USRP™ Hardware Driver FPGA Repository
205	96	0	5 months ago	aes/76	Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
204	50	3	1 year, 1 month ago	fpga_readings/77	Recipe for FPGA cooking
203	54	4	Unknown	nandland/78	All code found on nandland is here. underconstruction.gif
200	38	1	Unknown	ice40-playground/79	Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)
195	44	4	Unknown	raven-picorv32/80	Silicon-validated SoC implementation of the PicoSoc/PicoRV32
185	22	7	Unknown	twitchcore/81	It's a core. Made on Twitch.
185	33	7	Unknown	TinyFPGA-B-Series/82	Open source design files for the TinyFPGA B-Series boards.
180	50	6	Unknown	openc906/83	OpenXuantie - OpenC906 Core
178	44	18	Unknown	Cores-SweRVolf/84	FuseSoC-based SoC for SweRV EH1
177	44	0	1 year, 6 months ago	wbuart32/85	A simple, basic, formally verified UART controller
175	29	0	3 years ago	SimpleVOut/86	A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
175	10	1	Unknown	fpga-chip8/87	CHIP-8 console on FPGA
168	12	0	a month ago	fpg1/88	FPGA implementation of DEC PDP-1 computer (1959) in Verilog, with CRT, Teletype and Console.
168	20	0	8 years ago	ez8/89	The Easy 8-bit Processor
167	34	6	3 years ago	DisplayPort_Verilog/90	A Verilog implementation of DisplayPort protocol for FPGAs
159	95	4	9 years ago	uvm_axi/91	uvm AXI BFM(bus functional model)
159	57	5	3 years ago	Tang_E203_Mini/92	LicheeTang 蜂鸟E203 Core
157	41	1	Unknown	livehd/93	Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
155	60	0	Unknown	RePlAce/94	RePlAce global placement tool
154	40	0	5 months ago	Single_instruction_cycle_OpenMIPS/95	通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
152	51	42	a month ago	ao486_MiSTer/96	ao486 port for MiSTer
151	33	4	3 months ago	FPGA-peripherals/97	🌱 ❄️ Collection of open-source peripherals in Verilog
151	53	25	2 years ago	open-register-design-tool/98	Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
150	41	82	a month ago	bsg_manycore/99	Tile based architecture designed for computing efficiency, scalability and generality
149	5	7	9 days ago	Analogue_Pocket_Neogeo/100	Analogue Pocket Neogeo Core compatible with openFPGA
149	54	1	Unknown	schoolMIPS/101	CPU microarchitecture, step by step
144	34	3	Unknown	ZYNQ-NVDLA/102	NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
143	72	3	Unknown	FPGA_Based_CNN/103	FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
140	27	1	2 years ago	usbcorev/104	A full-speed device-side USB peripheral core written in Verilog.
139	81	0	2 years ago	AMBA_AXI_AHB_APB/105	AMBA bus lecture material
136	51	4	8 years ago	fpganes/106	NES in Verilog
136	40	0	8 years ago	milkymist/107	SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU
135	21	3	3 months ago	usb3_pipe/108	USB3 PIPE interface for Xilinx 7-Series
134	56	63	29 days ago	fomu-workshop/109	Support files for participating in a Fomu workshop
131	26	0	Unknown	archexp/110	浙江大学计算机体系结构课程实验
131	50	1	Unknown	core_ddr3_controller/111	A DDR3 memory controller in Verilog for various FPGAs
130	11	1	Unknown	fedar-f1-rv64im/112	5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.
130	25	1	4 months ago	a2o/113	None
130	58	0	Unknown	32-Verilog-Mini-Projects/114	Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
130	20	4	1 year, 1 month ago	DreamcastHDMI/115	Dreamcast HDMI
136	131	25	Unknown	caravel_mpw-one/116	Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
130	34	2	2 months ago	iceGDROM/117	An FPGA based GDROM emulator for the Sega Dreamcast
129	77	5	4 years ago	Hardware-CNN/118	A convolutional neural network implemented in hardware (verilog)
129	26	3	4 months ago	ice40_ultraplus_examples/119	Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
132	14	0	Unknown	vm80a/120	i8080 precise replica in Verilog, based on reverse engineering of real die
127	43	2	Unknown	HDL-Bits-Solutions/121	This is a repository containing solutions to the problem statements given in HDL Bits website.
126	44	4	2 years ago	h265-encoder-rtl/122	http://openasic.org/
126	29	0	Unknown	Colorlight-FPGA-Projects/123	current focus on Colorlight i5 and i9 module
125	22	1	2 years ago	display_controller/124	FPGA display controller with support for VGA, DVI, and HDMI.
123	33	0	4 years ago	mriscv/125	A 32-bit Microcontroller featuring a RISC-V core
121	78	14	4 years ago	orpsoc-cores/126	Core description files for FuseSoC
121	19	1	3 days ago	cpu11/127	Revengineered ancient PDP-11 CPUs, originals and clones
120	17	3	4 months ago	n64rgb/128	Everything around N64 and RGB
119	71	1	6 years ago	or1200/129	OpenRISC 1200 implementation
123	12	2	1 year, 16 days ago	icestation-32/130	Compact FPGA game console
117	18	2	2 years ago	lpc_sniffer_tpm/131	A low pin count sniffer for ICEStick - targeting TPM chips
113	19	3	1 year, 7 months ago	panologic-g2/132	Pano Logic G2 Reverse Engineering Project
111	26	4	7 months ago	Toooba/133	RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
110	48	0	1 year, 4 months ago	async_fifo/134	A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
110	43	9	Unknown	Tang_FPGA_Examples/135	LicheeTang FPGA Examples
111	49	1	10 years ago	fft-dit-fpga/136	Verilog module for calculation of FFT.
114	35	2	10 months ago	icebreaker-verilog-examples/137	This repository contains small example designs that can be used with the open source icestorm flow.
108	28	0	Unknown	mips32-cpu/138	奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
108	5	0	Unknown	RaspberryPiAtomicNixieClock/139	None
107	10	1	Unknown	antikernel/140	The Antikernel operating system project
114	84	0	Unknown	FPGA-CNN/141	FPGA implementation of Cellular Neural Network (CNN)
110	11	0	Unknown	vgasim/142	A Video display simulator
106	48	6	1 year, 5 months ago	vsdflow/143	VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
107	18	1	Unknown	oldland-cpu/144	Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
105	60	45	a month ago	Genesis_MiSTer/145	Sega Genesis for MiSTer
105	48	0	Unknown	ivtest/146	Regression test suite for Icarus Verilog. (OBSOLETE)
109	29	7	Unknown	tinyfpga_bx_usbserial/147	USB Serial on the TinyFPGA BX
104	41	56	a month ago	Minimig-AGA_MiSTer/148	None
104	5	0	Unknown	riskow/149	Learning how to make a RISC-V
104	19	4	1 year, 9 months ago	core_jpeg/150	High throughput JPEG decoder in Verilog for FPGA
104	36	1	7 months ago	DetectHumanFaces/151	Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
104	23	1	4 years ago	RISC-V-CPU/152	RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
104	31	2	2 years ago	apple-one/153	An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
103	60	33	11 days ago	NeoGeo_MiSTer/154	NeoGeo for MiSTer
102	35	1	1 year, 10 months ago	SM3_core/155	None
102	27	3	2 months ago	MobileNet-in-FPGA/156	Generator of verilog description for FPGA MobileNet implementation
102	21	5	7 years ago	NeoGeoHDMI/157	Verilog project that takes the digital video and audio from a Neo Geo MVS before going through the DACs and outputs the signals over HDMI
102	12	2	Unknown	jt12/158	FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10)
101	31	0	Unknown	cpu/159	A very primitive but hopefully self-educational CPU in Verilog
101	80	41	Unknown	OpenROAD-flow-scripts/160	None
98	15	5	Unknown	icesugar-pro/161	iCESugar series FPGA dev board
98	12	58	Unknown	spatial-lang/162	Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
97	76	1	1 year, 10 months ago	Practical-UVM-Step-By-Step/163	This is the main repository for all the examples for the book Practical UVM
97	39	1	4 years ago	clacc/164	Deep Learning Accelerator (Convolution Neural Networks)
96	12	0	6 years ago	PonyLink/165	A single-wire bi-directional chip-to-chip interface for FPGAs
105	32	7	7 months ago	corescore/166	CoreScore
97	32	0	Unknown	NaiveMIPS-HDL/167	Naïve MIPS32 SoC implementation
102	61	5	8 years ago	DSLogic-hdl/168	An open source FPGA design for DSLogic
95	40	6	4 days ago	libsystemctlm-soc/169	SystemC/TLM-2.0 Co-simulation framework
95	46	1	15 days ago	cdbus_ip/170	CDBUS Protocol and the IP Core for FPGA users
97	32	1	Unknown	kamikaze/171	Light-weight RISC-V RV32IMC microcontroller core.
95	27	2	17 days ago	aib-phy-hardware/172	Advanced Interface Bus (AIB) die-to-die hardware open source
95	13	1	4 years ago	iCE40/173	Lattice iCE40 FPGA experiments - Work in progress
95	23	0	2 years ago	openarty/174	An Open Source configuration of the Arty platform
94	12	0	6 years ago	cpus-caddr/175	FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs
93	23	2	Unknown	MIPS-pipeline-processor/176	A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
94	35	8	3 years ago	mipsfpga-plus/177	MIPSfpga+ allows loading programs via UART and has a switchable clock
92	17	0	3 months ago	agc_simulation/178	Verilog simulation files for a replica of the Apollo Guidance Computer
93	23	7	Unknown	ice40_examples/179	Public examples of ICE40 HX8K examples using Icestorm
90	8	2	Unknown	vt52-fpga/180	None
92	31	3	2 months ago	Haasoscope/181	Docs, design, firmware, and software for the Haasoscope
90	45	3	22 days ago	opene906/182	OpenXuantie - OpenE906 Core
91	32	2	9 years ago	Xilinx-Serial-Miner/183	Bitcoin miner for Xilinx FPGAs
89	25	5	Unknown	Reindeer/184	PulseRain Reindeer - RISCV RV32I[M] Soft CPU
88	66	4	25 days ago	iob-soc/185	RISC-V System on Chip Template
88	9	13	a day ago	breaks/186	Nintendo Entertainment System (NES) / Famicom / Dendy chip reversing
88	9	1	Unknown	Homotopy/187	Homotopy theory in Coq.
88	40	1	Unknown	verilog-lfsr/188	Fully parametrizable combinatorial parallel LFSR/CRC module
88	62	6	Unknown	Convolutional-Neural-Network/189	Implementation of CNN using Verilog
88	12	0	1 year, 10 days ago	NeoGeoFPGA-sim/190	Simulation only cartridge NeoGeo hardware definition
87	10	11	21 days ago	VGChips/191	Video Game custom chips reverse-engineered from silicon
93	24	1	Unknown	dspfilters/192	A collection of demonstration digital filters
90	40	0	Unknown	uart/193	Verilog UART
86	24	26	a month ago	caravel/194	Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
85	13	5	Unknown	amiga_replacement_project/195	This is an attempt to make clean Verilog sources for each chip on the Amiga.
88	27	0	Unknown	lm32/196	LatticeMico32 soft processor
83	21	2	25 days ago	iob-cache/197	Verilog configurable cache
86	27	1	4 years ago	SoftMC/198	SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf
83	12	3	5 years ago	fpgaboy/199	Implementation Nintendo's GameBoy console on an FPGA
83	37	3	2 years ago	neuralNetwork/200	None
82	40	2	Unknown	cnn_hardware_acclerator_for_fpga/201	This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs
84	58	2	1 year, 21 days ago	LimeSDR-USB_GW/202	Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board
81	35	1	8 months ago	FPGAandCNN/203	基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现
83	46	3	9 years ago	Icarus/204	DUAL Spartan6 Development Platform
80	32	0	Unknown	R8051/205	8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
81	24	15	Unknown	c65gs/206	FPGA-based C64 Accelerator / C65 like computer
79	40	1	Unknown	opene902/207	OpenXuantie - OpenE902 Core
79	11	4	Unknown	ice-chips-verilog/208	IceChips is a library of all common discrete logic devices in Verilog
79	36	9	Unknown	c5soc_opencl/209	DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.
78	26	1	Unknown	verilog_fixed_point_math_library/210	Fixed Point Math Library for Verilog
78	35	1	Unknown	zynq-axis/211	Hardware, Linux Driver and Library for the Zynq AXI DMA interface
78	16	8	5 days ago	FABulous/212	Fabric generator and CAD tools
77	39	3	a month ago	SD-card-controller/213	WISHBONE SD Card Controller IP Core
77	35	0	11 months ago	cdpga/214	FPGA core boards / evaluation boards based on CDCTL hardware
77	30	0	Unknown	mnist_fpga/215	using xilinx xc6slx45 to implement mnist net
79	9	8	1 year, 4 months ago	xcrypto/216	XCrypto: a cryptographic ISE for RISC-V
76	10	4	Unknown	jtgng/217	FPGA hardware compatible with some arcade systems. It covers Ghosts'n Goblins, 1942, 1943, Commando, Exed Exes, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter, Vulgus and The Speed Rumbler.
76	43	21	Unknown	Gameboy_MiSTer/218	Gameboy for MiSTer
75	211	32	Unknown	caravel_user_project/219	https://caravel-user-project.readthedocs.io
78	32	0	3 years ago	PASC/220	Parallel Array of Simple Cores. Multicore processor.
73	10	3	Unknown	ay-3-8910_reverse_engineered/221	The reverse-engineered AY-3-8910 chip. Transistor-level schematics, verilog model and a testbench with tools, that can render register dump files into .flac soundtrack.
72	52	0	7 years ago	IPCORE/222	None
72	13	0	1 year, 1 month ago	Fuxi/223	Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
71	43	4	6 months ago	spi-slave/224	SPI Slave for FPGA in Verilog and VHDL
71	16	0	1 year, 9 months ago	screen-pong/225	Pong game in a FPGA.
71	10	0	5 years ago	FPGA-TX/226	FPGA based transmitter
74	32	0	4 years ago	VidorFPGA/227	repository for Vidor FPGA IP blocks and projects
71	14	0	3 years ago	toygpu/228	A simple GPU on a TinyFPGA BX
70	14	0	3 years ago	MARLANN/229	Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
70	16	0	9 months ago	icebreaker-workshop/230	iCEBreaker Workshop
70	27	2	2 years ago	daisho/231	Test of the USB3 IP Core from Daisho on a Xilinx device
69	43	1	4 years ago	ethernet_10ge_mac_SV_UVM_tb/232	SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
79	30	0	7 years ago	Verilog-caches/233	Various caches written in Verilog-HDL
69	34	8	5 years ago	nysa-sata/234	None
69	13	0	4 months ago	introduction-to-fpga/235	None
68	16	1	a month ago	sdspi/236	SD-Card controller, using a SPI interface that is (optionally) shared
68	16	0	4 years ago	hyperram/237	Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
74	10	0	1 year, 8 months ago	mc6809/238	Cycle-Accurate MC6809/E implementation, Verilog
68	17	0	3 years ago	BUAA_CO/239	2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)
67	19	8	6 months ago	SOFA/240	SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
67	27	1	a month ago	benchmarks/241	EPFL logic synthesis benchmarks
67	12	2	a month ago	OpenCGRA/242	OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
71	16	0	3 years ago	riscv/243	Verilog implementation of a RISC-V core
70	16	3	10 years ago	ao68000/244	The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.
66	22	1	9 years ago	Multiplier16X16/245	Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
69	11	0	1 year, 9 months ago	rt/246	A Full Hardware Real-Time Ray-Tracer
66	4	1	3 hours ago	xenowing/247	"What comes next? Super Mario 128? Actually, that's what I want to do."
66	7	15	1 year, 6 months ago	hrm-cpu/248	Human Resource Machine - CPU Design #HRM
65	10	2	2 years ago	Riscy-SoC/249	Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
69	5	2	a month ago	fpga_pio/250	An attempt to recreate the RP2040 PIO in an FPGA
65	14	2	1 year, 2 months ago	up5k/251	Upduino v2 with the ice40 up5k FPGA demos
65	8	2	6 months ago	GottaGoFastRAM/252	8MB Autoconfig FastRAM for Amiga 500/1000/2000/CDTV
65	38	3	3 years ago	verilog-cam/253	Verilog Content Addressable Memory Module
64	16	0	7 months ago	UltraMIPS_NSCSCC/254	UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
74	25	0	4 years ago	NPU_on_FPGA/255	在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。
63	19	0	1 year, 1 month ago	dpll/256	A collection of phase locked loop (PLL) related projects
61	18	51	2 months ago	tapasco/257	The Task Parallel System Composer (TaPaSCo)
61	28	5	3 years ago	ODIN/258	ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.
61	20	3	10 years ago	ORGFXSoC/259	An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)
60	10	0	6 months ago	steel-core/260	Steel is a RISC-V processor core that implements the RV32I and Zicsr instruction sets of the RISC-V specifications.
59	17	2	5 months ago	sha3/261	None
59	32	2	5 years ago	h.265_encoder/262	None
59	22	1	4 years ago	ARM7/263	Implemetation of pipelined ARM7TDMI processor in Verilog
59	24	2	3 years ago	ARM-LEGv8/264	Verilog Implementation of an ARM LEGv8 CPU
59	23	0	a month ago	CNN_for_SLR/265	A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
58	14	4	4 months ago	OpenSERDES/266	Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
61	21	2	3 years ago	Verilog-Projects/267	This repository contains source code for past labs and projects involving FPGA and Verilog based designs
58	17	0	6 months ago	fpga-md5-cracker/268	A 64-stage pipelined MD5 implementation written in verliog. Runs reliably on a DE0-Nano at 100mhz, computing 100 million hashes per second.
58	13	1	3 years ago	Speech256/269	An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.
58	25	0	6 months ago	CNN-On-FPGA/270	FPGA
60	6	0	1 year, 6 months ago	wbscope/271	A wishbone controlled scope for FPGA's
60	9	1	4 years ago	lpc_sniffer/272	a low pin count sniffer for icestick
57	20	3	6 years ago	FPU/273	IEEE 754 floating point unit in Verilog
57	22	6	a month ago	LSOracle/274	IDEA project source files
57	22	0	4 years ago	MIPS/275	A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
58	35	38	6 years ago	minimig-mist/276	Minimig for the MiST board
61	9	1	2 years ago	panologic/277	PanoLogic Zero Client G1 reverse engineering info
57	16	0	2 years ago	hardenedlinux_profiles/278	It contains hardenedlinux community documentation.
62	12	0	10 months ago	OpenAmiga500FastRamExpansion/279	4/8 MB Fast RAM Expansion for the Commodore Amiga 500
56	33	28	a month ago	MegaCD_MiSTer/280	Mega CD for MiSTer
56	24	1	2 years ago	ethmac/281	Ethernet MAC 10/100 Mbps
56	21	7	2 years ago	i3c-slave-design/282	MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
56	13	1	2 years ago	fpga-sdft/283	sliding DFT for FPGA, targetting Lattice ICE40 1k
59	18	4	1 year, 8 months ago	basic-ecp5-pcb/284	Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs
56	26	1	4 years ago	TOE/285	TCP Offload Engine
61	22	0	2 years ago	drec-fpga-intro/286	Materials for "Introduction to FPGA and Verilog" at MIPT DREC
56	37	4	6 years ago	bch_verilog/287	Verilog based BCH encoder/decoder
56	25	0	1 year, 11 months ago	timetoexplore/288	Source code to accompany https://timetoexplore.net
57	5	1	2 years ago	flickerfixer/289	An open source flicker fixer for Amiga 500/2000
55	23	22	4 days ago	DFFRAM/290	Standard Cell Library based Memory Compiler using FF/Latch cells
56	14	0	3 years ago	VexRiscvSoftcoreContest2018/291	None
54	24	0	3 years ago	8-bits-RISC-CPU-Verilog/292	Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
54	5	0	a day ago	riscduino/293	Arduino compatible Risc-V Based SOC
54	14	0	2 years ago	XilinxUnisimLibrary/294	None
56	35	3	5 years ago	digital-servo/295	NIST digital servo: an FPGA based fast digital feedback controller
53	2	0	8 hours ago	PDP-1/296	None
54	17	1	2 years ago	aib-phy-hardware/297	None
53	0	0	11 months ago	MIPS-Microsystems/298	A computer system containing CPU, OS and Compiler under MIPS architecture.
53	19	13	2 years ago	alpha-release/299	Builds, flow and designs for the alpha release
54	2	0	3 years ago	soc/300	An experimental System-on-Chip with a custom compiler toolchain.
53	13	0	2 years ago	challenges-2020/301	Pwn2Win 2020 Challenges
56	26	1	19 years ago	8051/302	8051 core
52	20	2	2 years ago	freepdk-45nm/303	ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
52	20	3	4 years ago	Processor-UVM-Verification/304	System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
54	21	1	1 year, 3 months ago	opencpi/305	Open Component Portability Infrastructure
53	7	47	1 year, 11 months ago	rigel/306	Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
51	9	0	3 years ago	up5k_basic/307	A small 6502 system with MS BASIC in ROM
51	18	0	11 months ago	Solutions-to-HDLbits-Verilog-sets/308	Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).
51	19	1	1 year, 9 months ago	ARM_Cortex-M3/309	该项目依据全国大学生集成电路创新创业大赛“ARM杯”赛题要求，在FPGA上搭建Cortex-M3软核、图像协处理器，并通过OV5640摄像头采集车牌图像，实现对车牌的识别与结果显示。项目基于Altera DE1 FPGA搭载Cortex-M3软核，依据AHB-Lite总线协议，将LCD1602、RAM、图像协处理器等外设挂载至Cortex-M3。视频采集端，设计写FiFo模块、SDRAM存储与输出、读FiFo模块、灰度处理模块、二值化、VGA显示等模块。最终将400位宽的结果数据（对应20张车牌）存储在RAM中，输出至AHB总线，由Cortex-M3调用并显示识别结果。
51	9	0	3 years ago	fpga-odysseus/310	FPGA Odysseus with ULX3S
51	7	13	3 years ago	Neogeo_MiSTer_old/311	SNK NeoGeo core for the MiSTer platform
51	21	0	2 years ago	SIGMA/312	RTL implementation of Flex-DPE.
53	4	1	2 years ago	gameboy-fpga-cartridge/313	None
50	33	52	7 days ago	yosys-f4pga-plugins/314	Plugins for Yosys developed as part of the F4PGA project.
53	19	3	1 year, 5 months ago	verilog-math/315	Mathematical Functions in Verilog
53	20	0	5 years ago	caribou/316	Caribou: Distributed Smart Storage built with FPGAs
50	14	1	2 years ago	MIPS-Processor/317	5-stage pipelined 32-bit MIPS microprocessor in Verilog
51	33	1	7 years ago	mips32r1_xum/318	A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. This is a bare-metal CPU with no virtual memory. (Old University of Utah XUM archive)
51	7	1	2 years ago	iua/319	ice40 USB Analyzer
56	20	1	3 years ago	FPGA-Accelerator-for-AES-LeNet-VGG16/320	FPGA/AES/LeNet/VGG16
49	13	0	3 years ago	tiny-tpu/321	Small-scale Tensor Processing Unit built on an FPGA
49	20	0	6 years ago	stx_cookbook/322	Altera Advanced Synthesis Cookbook 11.0
52	11	1	3 months ago	verilog-65C02-microcode/323	65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface
49	6	2	5 years ago	Frix/324	IBM PC Compatible SoC for a commercially available FPGA board
55	8	0	1 year, 1 day ago	iCE40linux/325	Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker
49	12	2	2 hours ago	Bluster/326	CPLD Replacement for A2000 Buster
49	5	0	5 years ago	21FX/327	A bootloader for the SNES console
48	43	2	5 days ago	oc-accel/328	OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
48	31	7	a month ago	Template_MiSTer/329	Template with latest framework for MiSTer
48	16	2	4 years ago	chiphack/330	Repository and Wiki for Chip Hack events.
50	14	0	2 years ago	first-fpga-pcb/331	FPGA dev board based on Lattice iCE40 8k
50	19	0	5 years ago	ECE1373_2016_hft_on_fpga/332	High Frequency Trading using Vivado HLS
48	8	1	4 years ago	BAR-Tender/333	An FPGA I/O Device which services physical memory reads/writes via UMDF2 driver
49	14	0	6 years ago	sds7102/334	A port of Linux to the OWON SDS7102 scope
48	11	0	4 years ago	mips-cpu/335	A MIPS CPU implemented in Verilog
47	3	0	4 years ago	collection-iPxs/336	Icestudio Pixel Stream collection
47	19	3	a month ago	Basic-SIMD-Processor-Verilog-Tutorial/337	Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
47	18	1	2 years ago	Open_RegModel/338	🐥Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
50	34	3	4 years ago	prog_fpgas/339	The repository for the Verilog code examples and ISE projects that accompany the book Programming FPGAs: Getting Started with Verilog.
48	28	3	8 years ago	beagle/340	BeagleBone HW, SW, & FPGA Development
48	9	3	3 months ago	cnnhwpe/341	None
46	16	42	6 months ago	zx-evo/342	TS-Configuration for ZX Spectrum clone named ZX-Evolution
46	28	4	9 years ago	Atalanta/343	Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
46	29	1	3 years ago	GNSS_Firehose/344	Wideband front-end digitizer for GPS, GLONASS, Galileo, BeiDou
46	34	0	6 years ago	mojo-base-project/345	This is the base project for the Mojo. It should be used as the starting point for all projects.
45	15	1	2 years ago	DSP-RTL-Lib/346	RTL Verilog library for various DSP modules
45	7	6	1 year, 7 months ago	74xx-liberty/347	None
45	6	1	5 years ago	MAM65C02-Processor-Core/348	Microprogrammed 65C02-compatible FPGA Processor Core (Verilog-2001)
47	38	1	3 years ago	AlteraDE2Labs_Verilog/349	My solutions to Alteras example labs
45	13	0	3 years ago	HyperBUS/350	A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
45	21	3	3 years ago	riscv_soc/351	Basic RISC-V Test SoC
45	20	0	2 years ago	TPU-Tensor-Processing-Unit/352	IC implementation of TPU
47	6	1	3 years ago	engine-V/353	SoftCPU/SoC engine-V
50	13	0	1 year, 10 months ago	trng/354	True Random Number Generator core implemented in Verilog.
45	23	0	a month ago	NandFlashController/355	AXI Interface Nand Flash Controller (Sync mode)
48	9	0	2 years ago	core_dvi_framebuffer/356	Minimal DVI / HDMI Framebuffer
44	20	2	12 years ago	round_robin_arbiter/357	round robin arbiter
44	17	1	2 years ago	max1000-tutorial/358	Tutorial and example projects for the Arrow MAX1000 FPGA board
46	32	3	8 years ago	cordic/359	An implementation of the CORDIC algorithm in Verilog.
44	7	1	1 year, 1 month ago	openlogicbit/360	Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
44	12	3	1 year, 5 months ago	iceZ0mb1e/361	FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC
44	16	1	1 year, 6 months ago	fpga-ml-accelerator/362	This repository hosts the code for an FPGA based accelerator for convolutional neural networks
43	13	0	3 years ago	DIY_OpenMIPS/363	實作《自己動手寫CPU》書上的程式碼
43	11	6	1 year, 8 months ago	icestick-lpc-tpm-sniffer/364	FPGA-based LPC bus sniffing tool for Lattice iCEstick Evaluation Kit
43	6	0	15 days ago	A500_ACCEL_RAM_IDE-Rev-2/365	Improved design attempt for Amiga 500 in socket 68000 Accelerator, FastRAM and IDE Interface
43	3	10	3 months ago	circuitgraph/366	Tools for working with circuits as graphs in python
43	14	0	2 years ago	core_audio/367	Audio controller (I2S, SPDIF, DAC)
43	23	1	4 years ago	OV7670-Verilog/368	Verilog modules required to get the OV7670 camera working
43	9	0	2 years ago	moxie-cores/369	Moxie-compatible core repository
43	14	0	3 years ago	BeagleWire/370	This repository contains software for BeagleWire. It is a realization of my project for GSOC-2017
42	26	8	1 year, 1 month ago	Parser-Verilog/371	A Standalone Structural Verilog Parser
42	8	1	9 months ago	vga-clock/372	Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
47	10	0	4 years ago	Computer-Architecture-Task-2/373	Riscv32 CPU Project
42	20	1	6 years ago	nfmac10g/374	Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
46	17	0	4 years ago	robot-arm-v01/375	None
41	26	0	10 years ago	DDR2_Controller/376	DDR2 memory controller written in Verilog
41	7	6	a month ago	zerosoc/377	Demo SoC for SiliconCompiler.
41	5	10	3 months ago	snark-barker-mca/378	A Sound Blaster compatible sound card for Micro Channel bus computers
41	2	4	4 months ago	spokefpga/379	FPGA Tools and Library
42	7	0	3 years ago	tiny_usb_examples/380	Using the TinyFPGA BX USB code in user designs
41	9	3	6 months ago	VirtualTap/381	Mod kit for the Virtual Boy to make it output VGA or RGB video
41	19	0	3 years ago	de10nano_vgaHdmi_chip/382	Test for video output using the ADV7513 chip on a de10 nano board
41	24	0	5 years ago	H264/383	H264视频解码verilog实现
41	32	0	4 years ago	Examples-in-book-write-your-own-cpu/384	《自己动手写CPU》一书附带的文件
40	9	0	3 years ago	ctf/385	Stuff from CTF contests
46	4	0	1 year, 11 months ago	sdram-controller/386	Generic FPGA SDRAM controller, originally made for AS4C4M16SA
40	14	1	9 months ago	uart/387	A simple implementation of a UART modem in Verilog.
40	5	6	a month ago	rj32/388	A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.
40	13	0	1 year, 6 months ago	CNN-FPGA/389	Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
40	6	1	14 days ago	spam-1/390	Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu
40	27	2	1 year, 10 months ago	ARM9-compatible-soft-CPU-core/391	This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
40	4	0	10 hours ago	core-template/392	A template for getting started with FPGA core development
40	8	0	2 years ago	MIPS48PipelineCPU/393	5 stage pipelined MIPS-32 processor
39	12	0	6 years ago	yosys-bigsim/394	A collection of big designs to run post-synthesis simulations with yosys
39	8	0	2 months ago	difuzz-rtl/395	None
40	22	1	4 years ago	fpga_design/396	这是我所开发的两个项目，包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统
39	7	0	2 months ago	SiDi-FPGA/397	SiDi FPGA for retro systems.
39	9	2	5 years ago	ACC/398	Apollo CPU Core in Verilog. For learning and having fun with open FPGA
39	21	0	16 days ago	thinpad_top/399	Project template for Artix-7 based Thinpad board
39	21	1	1 year, 5 months ago	computer-organization-lab/400	中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU
39	10	0	6 months ago	2021_Spring_NCTU_ICLAB/401	NCTU 2021 Spring Integrated Circuit Design Laboratory
38	0	0	3 years ago	comparchitecture/402	Verilog and MIPS simple programs
38	9	1	6 years ago	oc_jpegencode/403	Fork of OpenCores jpegencode with Cocotb testbench
38	13	0	10 hours ago	SpinalHDL_CNN_Accelerator/404	CNN accelerator implemented with Spinal HDL
38	8	2	4 months ago	cpc_ram_expansion/405	A series of Amstrad CPC PCBs including a backplane, ROM and 512K and 1MByte RAM expansions.
38	3	3	2 years ago	observer/406	None
38	9	1	2 years ago	RISC-V-CPU/407	A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
38	21	0	11 years ago	sparc64soc/408	OpenSPARC-based SoC
38	13	0	2 years ago	LUTNet/409	None
38	10	1	2 years ago	picorv32_Xilinx/410	A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
40	4	0	4 years ago	RISC-processor/411	Simple single cycle RISC processor written in Verilog
38	18	1	2 days ago	jtframe/412	Common framework for MiST(er), SiDi, ZX-UNO/DOS and Unamiga core development. With special focus on arcade cores.
38	38	0	9 months ago	jtag_vpi/413	TCP/IP controlled VPI JTAG Interface.
39	4	0	2 months ago	reDIP-SID/414	MOS 6581 / 8580 SID FPGA emulation platform
38	10	0	3 years ago	PACoGen/415	PACoGen: Posit Arithmetic Core Generator
37	13	1	10 years ago	vSPI/416	Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter
46	28	0	11 years ago	dma_axi/417	AXI DMA 32 / 64 bits
39	22	0	3 years ago	huaweicloud-fpga/418	The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.
37	2	0	4 years ago	vga_to_ascii/419	Realtime VGA to ASCII Art converter
36	33	7	4 months ago	Menu_MiSTer/420	None
36	2	0	6 years ago	HaSKI/421	Cλash/Haskell FPGA-based SKI calculus evaluator
41	35	0	1 year, 14 days ago	risc-v-core/422	This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
36	10	2	3 years ago	Posit-HDL-Arithmetic/423	Universal number Posit HDL Arithmetic Architecture generator
36	31	0	1 year, 8 months ago	vsdstdcelldesign/424	This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.
43	6	0	1 year, 6 months ago	sdr/425	A basic Soft(Gate)ware Defined Radio architecture
39	13	0	2 years ago	spi_mem_programmer/426	Small (Q)SPI flash memory programmer in Verilog
36	11	0	1 year, 8 months ago	Image-Classification-using-CNN-on-FPGA/427	Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
36	8	0	10 years ago	dcpu16/428	Pipelined DCPU-16 Verilog Implementation
36	22	0	14 years ago	xge_mac/429	Ethernet 10GE MAC
36	3	1	3 years ago	icebreaker-candy/430	Eye candy from an iCEBreaker FPGA and a 64×64 LED panel
42	1	0	2 months ago	Quafu/431	A small SoC with a pipeline 32-bit RISC-V CPU.
38	17	6	6 months ago	xfcp/432	Extensible FPGA control platform
38	11	0	8 years ago	vj-uart/433	Virtual JTAG UART for Altera Devices
35	15	1	4 years ago	openmsp430/434	The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
35	10	2	a day ago	CPU/435	单周期 8指令 MIPS32CPU
35	34	0	8 years ago	FPGA_image_processing/436	Image capture, image filtering and image display (VGA) : picture in picture, edge detection, gray image and smooth image
39	6	0	7 years ago	gb/437	The Original Nintendo Gameboy in Verilog
38	9	39	4 months ago	mantle/438	mantle library
40	16	0	1 year, 3 months ago	sha1/439	Verilog implementation of the SHA-1 cryptgraphic hash function
39	14	1	1 year, 6 months ago	qspiflash/440	A set of Wishbone Controlled SPI Flash Controllers
35	10	0	5 days ago	jt49/441	Verilog clone of YM2149
37	7	0	2 years ago	icestick-glitcher/442	Simple voltage glitcher implementation for the Lattice iCEstick Evaluation Kit
40	18	3	4 months ago	minimig-de1/443	Minimig for the DE1 board
35	11	3	1 year, 2 months ago	mipi-demo/444	MIPI CSI-2 + MIPI CCS Demo
34	9	0	8 years ago	aoOCS/445	The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is not related in any way with Minimig - it is a new and independent Amiga OCS implementation.
34	5	1	1 year, 9 months ago	zbasic/446	A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
34	15	0	4 years ago	eddr3/447	mirror of https://git.elphel.com/Elphel/eddr3
34	29	2	2 years ago	block-nvdla-sifive/448	None
34	10	0	1 year, 3 months ago	core_usb_cdc/449	Basic USB-CDC device core (Verilog)
34	14	0	6 years ago	FPGA_Ultrasound/450	CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.
34	8	1	14 hours ago	xschem_sky130/451	XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
35	23	0	10 years ago	tdc-core/452	A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
34	14	0	9 years ago	fpganes/453	FPGA-based AI for Super Mario Bros. Designed for an Altera DE2
38	20	0	2 years ago	RISC-V-32I/454	体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
36	10	0	1 year, 2 months ago	MangoMIPS32/455	A softcore microprocessor of MIPS32 architecture.
36	18	0	7 years ago	verilog-utils/456	native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
33	20	0	5 years ago	fast/457	FAST
35	1	1	7 months ago	cxxrtl_eval/458	Experiments with Yosys cxxrtl backend
33	8	0	1 year, 1 month ago	no2bootloader/459	USB DFU bootloader gateware / firmware for FPGAs
37	6	3	6 months ago	SF500/460	Spitfire 500, A low-end 14 MHz Accelerator with IDE and 4/8 MB fast RAM for the Amiga 500.
33	22	0	12 years ago	jpegencode/461	JPEG Encoder Verilog
33	9	0	1 year, 3 months ago	Fixed-Floating-Point-Adder-Multiplier/462	16-bit Adder Multiplier hardware on Digilent Basys 3
33	7	2	3 years ago	iCEstick-UART-Demo/463	This is a simple UART echo test for the iCEstick Evaluation Kit
33	6	1	1 year, 10 months ago	INT_FP_MAC/464	INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
35	15	2	4 years ago	CNN_VGG19_verilog/465	Convolution Neural Network of vgg19 model in verilog
33	19	0	1 year, 3 months ago	ARM_AMBA_Design/466	Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
31	2	0	3 years ago	riscv-megaproject/467	A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones
32	8	0	6 months ago	ReckOn/468	ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.
32	9	0	9 years ago	lsasim/469	Educational load/store instruction set architecture processor simulator
34	17	0	1 year, 8 months ago	vsdmixedsignalflow/470	This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools.
37	5	1	9 months ago	SQRL_quickstart/471	Basic loadout for SQRL Acorn CLE 215/215+ board. Blinks all LEDs, outputs square waves on all 12 GPIO outputs
32	5	0	4 years ago	OpenFPGA/472	OpenFPGA
32	19	0	4 years ago	usb2_dev/473	USB 2.0 Device IP Core
32	18	0	10 years ago	verilog-sha256/474	Implementation of the SHA256 Algorithm in Verilog
31	11	0	3 years ago	csirx/475	Open-source CSI-2 receiver for Xilinx UltraScale parts
32	10	0	8 years ago	LVDS-7-to-1-Serializer/476	An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.
31	3	9	1 year, 5 months ago	QuokkaEvaluation/477	Example projects for Quokka FPGA toolkit
32	5	0	a day ago	Hazard3/478	3-stage RV32IMACZb* processor with debug
32	6	0	5 years ago	wiki/479	None
32	9	0	24 days ago	jelly/480	Original FPGA platform
32	9	1	1 year, 9 months ago	OpenPhySyn/481	EDA physical synthesis optimization kit
32	4	0	2 years ago	cisco-hwic-3g-cdma/482	Reverse Engineering of the Cisco HWIC-3G-CDMA PCB
32	26	0	7 years ago	Open-Source-Network-on-Chip-Router-RTL/483	None
31	8	1	1 year, 2 months ago	HPS2FPGAmapping/484	SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
31	16	2	16 years ago	can/485	CAN Protocol Controller
32	10	0	2 years ago	RDF-2019/486	DATC RDF
33	4	0	4 years ago	s6soc/487	CMod-S6 SoC
31	4	0	2 years ago	Colorlight-5A-75B/488	Notes for Colorlight-5A-75B.
31	14	0	2 years ago	fpga-gpu/489	A basic GPU for altera FPGAs
31	19	1	2 years ago	fifo/490	Generic FIFO implementation with optional FWFT
30	14	0	1 year, 11 months ago	Booth_Multipliers/491	Parameterized Booth Multiplier in Verilog 2001
33	4	0	2 years ago	CNNAF-CNN-Accelerator_init/492	CNN-Accelerator based on FPGA developed by verilog HDL.
31	6	2	2 years ago	datc_robust_design_flow/493	DATC Robust Design Flow.
35	20	0	5 years ago	ee260_lab/494	EE 260 Winter 2017: Advanced VLSI Design
31	19	1	3 years ago	GnuRadar/495	Open-source software defined radar based on the USRP 1 hardware.
31	7	0	1 year, 26 days ago	FPGA_Book_Experiments/496	My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
31	14	1	1 year, 7 months ago	FAST9-Accelerator/497	FAST-9 Accelerator for Corner Detection
31	27	0	6 years ago	AES-FPGA/498	AES加密解密算法的Verilog实现
31	14	0	8 years ago	MIPS-Processor-in-Verilog/499	Processor repo
31	6	0	1 year, 5 months ago	CPU_start_from_0/500	从零开始设计一个CPU (Verilog)
30	8	1	2 years ago	core_soc/501	Basic Peripheral SoC (SPI, GPIO, Timer, UART)
30	8	0	9 days ago	enxor-logic-analyzer/502	FPGA Logic Analyzer and GUI
30	10	1	2 years ago	SDR-Micron/503	SDR Micron USB receiver
30	6	2	26 days ago	OpenIRV/504	Open-source thermal camera project
32	7	0	2 years ago	HDMI-to-FPGA-to-APA102-Pixels/505	Final Project written in Lucid (verilog) for the Mojo FPGA development board. Reads pixels from HDMI and sends pixel data to 22,000 APA102 LEDs over SPI.
31	19	1	6 years ago	Propeller_1_Design/506	Propeller 1 design and example files to be run on FPGA boards.
32	18	20	5 years ago	RetroCade_Synth/507	RetroCade Synth - C64 SID, YM2149, and POKEY audio chips with MIDI interface.
30	10	0	2 years ago	HW-Syn-Lab/508	⚙Hardware Synthesis Laboratory Using Verilog
30	4	0	1 year, 2 months ago	CNN-Accelerator-VLSI/509	Convolutional accelerator kernel, target ASIC & FPGA
31	3	0	8 years ago	CPU32/510	Tiny MIPS for Terasic DE0
32	6	1	3 years ago	snes_dejitter/511	NES/SNES 240p de-jitter mod
29	8	0	a month ago	fpga/512	Collection of projects for various FPGA development boards
30	15	0	5 years ago	HitchHike/513	None
30	26	4	5 years ago	Hardware-Implementation-of-AES-Verilog/514	Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
32	28	0	3 years ago	Ethernet-design-verilog/515	Gigabit Ethernet UDP communication driver
29	0	0	14 hours ago	hrt/516	Hot Reconfiguration Technology demo
29	23	3	2 months ago	ZX-Spectrum_MISTer/517	None
30	12	0	5 years ago	SVM-Gaussian-Classification-FPGA/518	SVM Gaussian Classifier of 30x30 greyscale image on Verilog
29	7	0	1 year, 2 months ago	Vision-FPGA-SoM/519	tinyVision.ai Vision & Sensor FPGA System on Module
29	3	0	2 years ago	CNN-Accelerator-Implementation-based-on-Eyerissv2/520	None
29	22	1	4 months ago	DDLM/521	Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
29	19	0	3 years ago	x393/522	mirror of https://git.elphel.com/Elphel/x393
30	0	4	3 years ago	HDL-deflate/523	FPGA implementation of deflate (de)compress RFC 1950/1951
29	3	1	6 years ago	RISCV_Piccolo_v1/524	Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
30	13	0	5 years ago	book-examples/525	None
33	7	0	1 year, 1 month ago	core_uriscv/526	Another tiny RISC-V implementation
30	8	0	12 years ago	osdvu/527	None
29	6	0	a month ago	NTHU-ICLAB/528	清華大學
30	23	0	9 years ago	opensketch/529	simulation and netfpga code
30	8	0	2 years ago	iverilog-tutorial/530	Quickstart guide on Icarus Verilog.
29	15	0	10 months ago	FPGA_NTP_SERVER/531	A FPGA implementation of the NTP and NTS protocols
29	10	0	3 years ago	verilog-mini-demo/532	Verilog极简教程
29	10	0	9 months ago	FPGA-Build/533	A novel architectural design for stitching video streams in real-time on an FPGA.
29	12	0	28 days ago	evoapproxlib/534	Library of approximate arithmetic circuits
29	5	1	3 years ago	Lichee-Tang/535	Lichee Tang FPGA board examples
28	10	0	7 months ago	Cookabarra/536	a training-target implementation of rv32im, designed to be simple and easy to understand
28	22	1	2 years ago	LimeSDR-PCIe_GW/537	Altera Cyclone IV FPGA project for the PCIe LimeSDR board
30	18	1	1 year, 5 months ago	Icarus_Verilog/538	This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum
28	2	4	2 years ago	quark/539	Stack CPU 🚧 Work In Progress 🚧
28	6	3	3 years ago	v-regex/540	A simple regex library for V
28	28	2	9 months ago	VexRiscv-verilog/541	Using VexRiscv without installing Scala
30	14	2	3 years ago	buffets/542	Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
28	15	1	5 years ago	polyphase_filter_prj/543	哈工大软件无线电课设：多相滤波器的原理、实现及其应用，从采样率变换、多相滤波器结构到信道化收发机应用都有matlab介绍和FPGA仿真结果，含答辩PPT、学习笔记和个人总结。
28	17	0	2 years ago	verilog-arbiter/544	A look ahead, round-robing parametrized arbiter written in Verilog.
28	11	0	1 year, 3 months ago	chacha/545	Verilog 2001 implementation of the ChaCha stream cipher.
28	17	0	9 years ago	rfid-verilog/546	RFID tag and tester in Verilog
28	9	0	3 years ago	Open-FPGA/547	Devotes to open source FPGA
29	7	2	3 months ago	MiSTery/548	Atari ST/STe core for MiST
27	4	0	8 months ago	Computer-Organization-BUAA-2020/549	北航6系CO课 BUAA CO
27	12	0	2 years ago	fpga_image_processing/550	IP operations in verilog (simulation and implementation on ice40)
28	19	1	7 months ago	schoolWorks/551	Repository of NCKU class slides,exams, and homeworks
29	9	0	4 years ago	LeNet_RTL/552	An LeNet RTL implement onto FPGA
27	10	1	1 year, 4 months ago	riscv-soc-cores/553	None
27	9	0	1 year, 1 month ago	fpga-bpf/554	A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark
31	37	0	4 years ago	sata3_host_controller/555	It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
29	8	0	4 years ago	Spartan-Mini-NES/556	An FPGA based handheld NES system built around the Spartan 6 and the Spartan Mini development board.
27	3	0	2 years ago	nintendo-switch-i2s-to-spdif/557	I2S to S/PDIF conversion on SiPeed Tang Nano (GOWIN GW1N-LV1) which aims to convert Nintendo Switch's internal I2S signal.
27	19	1	2 months ago	apio-examples/558	🌱 Apio examples
27	16	0	1 year, 3 months ago	Video-and-Image-Processing-Design-Using-FPGAs/559	Video and Image Processing
28	3	0	2 years ago	EDSAC/560	FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope
27	6	0	5 years ago	Yoshis-Nightmare/561	FPGA Based Platformer Video Game
27	3	0	1 year, 8 months ago	PCI2Nano-PCB/562	An FPGA/PCI Device Reference Platform
27	8	0	1 year, 6 months ago	srgh-matrix-trinity/563	XBOX 360 advanced glitching - Reverse Engineered using a logic analyzer.
27	20	3	7 years ago	CAN-Bus-Controller/564	An CAN bus Controller implemented in Verilog
29	18	0	3 years ago	Open-CryptoNight-ASIC/565	Open source hardware implementation of classic CryptoNight
28	11	0	2 years ago	Uranus/566	Uranus MIPS processor by MaxXing & USTB NSCSCC team
27	10	0	2 years ago	USTC-ComputerArchitecture-2020S/567	Code for "Computer Architecture" in 2020 Spring.
27	19	1	4 years ago	Design-and-Verification-of-LDPC-Decoder/568	- Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab.
26	7	0	1 year, 3 months ago	fftdemo/569	A demonstration showing how several components can be compsed to build a simulated spectrogram
26	11	0	10 years ago	Pong/570	Pong game on an FPGA in Verilog.
26	5	0	2 days ago	jtopl/571	Verilog module compatible with Yamaha OPL chips
26	11	2	8 months ago	ThymesisFlow/572	Memory Disaggregation on POWER9 with OpenCAPI 3.0 M1 & C1
26	8	0	8 months ago	wbi2c/573	Wishbone controlled I2C controllers
26	6	0	2 years ago	hackaday_supercon_2019_logic_noise_FPGA_workshop/574	Hackaday Supercon 2019 Logic Noise Badge Workshop
26	5	0	1 year, 8 months ago	Async-Karin/575	Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.
26	8	0	a day ago	myslides/576	Collection of my presentations
26	14	0	3 years ago	Verilog-FIR/577	FIR implemention with Verilog
26	13	0	4 years ago	workshops/578	❄️ 🌟 Workshops with Icestudio and the IceZUM Alhambra board
26	2	2	11 months ago	no2muacm/579	Drop In USB CDC ACM core for iCE40 FPGA
26	5	1	7 years ago	Y86-CPU/580	A pipeline CPU in Verilog for the Y86 instruction set.
27	15	0	6 years ago	ethernet_10ge_mac_SV_tb/581	SystemVerilog testbench for an Ethernet 10GE MAC core
28	11	3	10 months ago	Nitro-Parts-lib-Xilinx/582	This is mainly a simulation library of xilinx primitives that are verilator compatible.
26	10	0	2 years ago	Azure-SDR/583	SW SDR
26	10	0	7 years ago	CPU/584	Verilog实现的简单五级流水线CPU，开发平台：Nexys3
28	13	2	7 years ago	8051/585	FPGA implementation of the 8051 Microcontroller (Verilog)
26	17	0	1 year, 1 month ago	sha512/586	Verilog implementation of the SHA-512 hash function.
25	2	0	6 years ago	literate-broccoli/587	An open source FPGA architecture
25	6	1	2 years ago	UART/588	ARM中通过APB总线连接的UART模块
26	17	0	7 years ago	yafpgatetris/589	Yet Another Tetris on FPGA Implementation
27	18	0	11 years ago	dma_ahb/590	AHB DMA 32 / 64 bits
25	13	1	1 year, 10 months ago	polyphony/591	3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.
25	15	1	4 years ago	Viterbi-Decoder-in-Verilog/592	An efficient implementation of the Viterbi decoding algorithm in Verilog
26	3	0	1 year, 1 month ago	up5k_osc/593	None
25	13	0	4 years ago	NoC-Verilog/594	A verilog implementation for Network-on-Chip
25	3	2	1 year, 2 months ago	xyloni/595	This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
25	12	1	3 years ago	trainwreck/596	Original RISC-V 1.0 implementation. Not supported.
28	19	1	6 years ago	Nitro-Parts-lib-SPI/597	Verilog SPI master and slave
25	6	2	1 year, 8 months ago	SoC_Automation/598	SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.
25	20	3	4 years ago	Cosmos-OpenSSD/599	None
25	1	0	3 months ago	ulx3s_examples/600	Example Verilog code for Ulx3s
25	1	0	1 year, 7 months ago	Hardware_Design/601	None
32	8	0	2 years ago	Computer-Experiment-on-the-principle-of-computer-composition/602	杭电计算机学院-《计算机组成原理》上机实验代码工程文件
26	8	1	6 years ago	mipscpu/603	Fully pipelined MIPS CPU in Verilog/SystemVerilog with advanced branch prediction, register renaming, and value prediction
32	13	0	3 years ago	Convolution-using-systolic-arrays/604	None
25	14	0	6 years ago	peridot/605	'PERIDOT' - Simple & Compact FPGA board
25	9	0	10 years ago	tinycpu/606	Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.
25	4	0	3 months ago	riscv-formal/607	RISC-V Formal Verification Framework
28	7	0	1 year, 6 months ago	interpolation/608	Digital Interpolation Techniques Applied to Digital Signal Processing
27	16	1	4 months ago	ce2020labs/609	ChipEXPO 2020 Digital Design School Labs
25	13	1	8 years ago	ddk-fpga/610	FPGA HDL Sources.
25	7	1	1 year, 2 months ago	VGA1306/611	VGA1306 (VGA-out for DIY Arduboys implemented on an FPGA!)
25	2	0	20 hours ago	RISu64/612	Toy RV64 processor for fun & learning
25	15	1	2 years ago	Pepino/613	None
25	12	0	10 months ago	Chisel-FFT-generator/614	FFT generator using Chisel
24	6	1	2 days ago	jt89/615	sn76489an compatible Verilog core, with emphasis on FPGA implementation and Megadrive/Master System compatibility
25	9	1	5 years ago	ocpi/616	Semi-private RTL development upstream of OpenCPI - this is not the OpenCPI repo!
26	16	1	9 years ago	turbo8051/617	turbo 8051
24	0	0	a month ago	ddr3-controller/618	A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
24	5	0	4 years ago	bapi-rv32i/619	A extremely size-optimized RV32I soft processor for FPGA.
26	22	7	7 years ago	MM/620	Miner Manager
27	9	0	1 year, 9 months ago	INSIDER-System/621	An FPGA-based full-stack in-storage computing system.
24	7	0	9 months ago	MIDI-Stepper-Synth-V2/622	Virginia Tech AMP Lab Version of the MIDI Stepper Synth. Uses FPGA and 32 Stepper Motors.
24	9	1	7 years ago	ws2812-verilog/623	This is a Verilog module to interface with WS2812-based LED strips.
24	3	0	1 year, 7 months ago	PCI2Nano-RTL/624	An open source FPGA PCI core & 8250-Compatible PCI UART core
24	4	1	5 months ago	AMSGateArray/625	Prototype boards and verilog for development of Xilinx CPLD replacements for the Amstrad 40010 and 40007 gate array chips.
24	14	0	2 months ago	OpenTSN2.0/626	an opensource project to enable TSN research, including distributed and centralized version.
24	8	0	2 years ago	usb2sniffer/627	USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
26	23	0	9 years ago	RSA4096/628	4096bit RSA project, with verilog code, python test code, etc
24	3	3	3 years ago	time-sleuth/629	Time Sleuth - Open Source Lag Tester
30	13	0	5 years ago	4-way-set-associative-cache-verilog/630	Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
24	16	2	3 months ago	iob-mem/631	Verilog behavioral description of various memories
24	3	0	5 years ago	Hardware-Accelerated-SNN/632	Architecture for Spiking Neural Network
24	5	0	a month ago	notary/633	Notary: A Device for Secure Transaction Approval 📟
22	13	0	1 year, 9 months ago	verilog-osx/634	Barerbones OSX based Verilog simulation toolchain.
23	10	2	9 months ago	tonic/635	A Programmable Hardware Architecture for Network Transport Logic
23	1	0	5 months ago	iic-audiodac-v1/636	Delta-sigma audio DAC (16b, 48kHz), intended for tape-out on MPW-5, SKY130 technology.
23	8	1	2 years ago	Low-Cost-and-Programmable-CRC/637	Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
23	11	12	2 years ago	nanorv32/638	A small 32-bit implementation of the RISC-V architecture
24	0	1	4 years ago	mera400f/639	MERA-400 in an FPGA
27	7	0	5 years ago	Verilog_Calculator_Matrix_Multiplication/640	This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
24	16	0	1 year, 8 months ago	verilog-starter-tutorials/641	Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
23	4	0	1 year, 11 months ago	serv_soc/642	SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
23	3	0	2 years ago	EI332/643	SJTU EI332 CPU完整实验代码及报告
26	12	0	2 years ago	DA_PUF_Library/644	Defense/Attack PUF Library (DA PUF Library)
23	2	0	3 years ago	enigmaFPGA/645	Enigma in FPGA
23	10	0	3 years ago	verilog-divider/646	a super-simple pipelined verilog divider. flexible to define stages
27	8	1	8 years ago	azpr_cpu/647	用Altera FPGA芯片自制CPU
23	22	0	5 years ago	SIMD-architecture/648	Overall multi-core SIMD microarchitecture
23	5	0	3 years ago	redpid/649	migen + misoc + redpitaya = digital servo
23	7	0	10 years ago	aemb/650	Multi-threaded 32-bit embedded core family.
24	6	0	2 years ago	de10-nano-riscv/651	A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano
23	20	2	1 year, 10 months ago	blake2/652	Hardware implementation of the blake2 hash function
23	1	0	11 hours ago	LunaPnR/653	LunaPnR is a place and router for integrated circuits
23	5	0	2 years ago	RISC-V/654	A simple RISC-V CPU written in Verilog.
23	11	0	1 year, 11 months ago	USB3_MIPI_CSI2_RX_V2_Crosslink_NX/655	MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX with Hard MIPI PHY. Gbps UVC Video Stream Over USB 3.0 with Cypress FX3, Currently WIP
24	17	1	4 years ago	nysa-verilog/656	Verilog Repository for GIT
23	6	0	11 months ago	mpsoc_example/657	None
23	6	0	3 years ago	MIPS-Verilog/658	MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.
23	7	1	1 year, 9 months ago	litex_vexriscv_smp_test/659	VexRiscv-SMP integration test with LiteX.
23	14	0	3 years ago	Interface-Protocol-in-Verilog/660	Interface Protocol in Verilog
23	14	0	2 years ago	x393_sata/661	mirror of https://git.elphel.com/Elphel/x393_sata
23	10	0	2 months ago	Delta-sigma-ADC-verilog/662	Delta-sigma ADC,PDM audio FPGA Implementation
22	10	1	5 years ago	arty-glitcher/663	FPGA-based glitcher for the Digilent Arty FPGA development board.
23	9	1	3 years ago	ComputerArchitectureLab/664	This repository is used to release the Labs of Computer Architecture Course from USTC
23	10	0	3 years ago	verilog-doc/665	All About HDL
22	6	0	11 months ago	public/666	None
22	9	3	6 days ago	MiSTer_DB9/667	Unofficial cores with DB9 support
22	9	1	10 months ago	NetFPGA-PLUS/668	None
22	7	0	9 years ago	riscv-invicta/669	A simple RISC-V core, described with Verilog
22	7	2	8 months ago	rodinia/670	AGM bitstream utilities and decoded files from Supra
24	15	0	5 years ago	FFT_Verilog/671	FFT implement by verilog_测试验证已通过
24	3	0	3 years ago	thunderclap-fpga-arria10/672	Thunderclap hardware for Intel Arria 10 FPGA
22	1	0	10 months ago	verilog-coding-standard/673	Recommended coding standard of Verilog and SystemVerilog.
24	5	0	3 years ago	fpga-examples/674	FPGA examples for 8bitworkshop.com
22	8	0	4 years ago	pciebench-netfpga/675	pcie-bench code for NetFPGA/VCU709 cards
22	10	0	2 years ago	00_Image_Rotate/676	视频旋转（2019FPGA大赛）
22	6	4	9 hours ago	VossII/677	The source code to the Voss II Hardware Verification Suite
22	5	1	4 years ago	Verilog-VGA-game/678	A simple game written in Verilog HDL language and display on the VGA screen.
22	2	0	3 years ago	gameduino-fpga-mods/679	Mods of the FPGA code from @jamesbowman's Gameduino file repository
22	9	1	9 years ago	fpgaminer-vanitygen/680	Open Source Bitcoin Vanity Address Generation on FPGAs
22	7	0	9 months ago	wb_intercon/681	Wishbone interconnect utilities
22	10	3	3 years ago	s7_mini_fpga/682	Example designs for the Spartan7 "S7 Mini" FPGA board
23	4	0	3 years ago	USB/683	FPGA USB 1.1 Low-Speed Implementation
24	14	1	2 years ago	matrix-creator-fpga/684	Reference HDL code for the MATRIX Creator's Spartan 6 FPGA
22	11	2	3 years ago	Zeus/685	NVDLA small config implementation on Zynq ZCU104 (evaluation)
29	18	0	1 year, 7 months ago	DSX_KCXG/686	个人资料，合肥工业大学宣城校区2019年-2020年第二学期（大三下学期），与物联网工程专业的课程有关资料，含课件、实验报告、课设报告等
22	6	0	1 year, 1 month ago	core_dbg_bridge/687	UART -> AXI Bridge
22	4	0	2 months ago	menshen/688	None
23	4	0	1 year, 8 months ago	caravel_fpga250/689	FPGA250 aboard the eFabless Caravel
25	10	0	6 years ago	2-way-Set-Associative-Cache-Controller/690	Synthesizable and Parameterized Cache Controller in Verilog
22	9	1	7 months ago	usb-de2-fpga/691	Hardware interface for USB controller on DE2 FPGA Platform
22	12	0	4 years ago	SHA256Hasher/692	SHA-256 IP core for ZedBoard (Zynq SoC)
28	15	1	4 years ago	FPGA-SM3-HASH/693	Description of Chinese SM3 Hash algorithm with Verilog HDL
22	3	1	3 years ago	fpga-virtual-graf/694	None
21	4	0	11 years ago	pdfparser/695	None
21	12	0	2 years ago	8bit_MicroComputer_Verilog/696	This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This was developed for the Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
21	3	0	1 year, 4 months ago	SpGEMM/697	None
21	12	0	10 months ago	ysyxSoC/698	None
22	10	0	6 years ago	Make-FPGA/699	Repository of Verilog code for Make:FPGA book Chapters 2 & 3.
21	4	2	3 years ago	recon/700	The RECON project creates library for Nios II Microcontroller System and Tool chain. The library includes a collection of hardware configurations and Arduino-style software APIs.
23	14	0	3 years ago	face_detect_open/701	A Voila-Jones face detector hardware implementation
21	14	1	9 years ago	ASIC/702	EE 287 2012 Fall
21	6	0	2 days ago	Bedrock/703	LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
22	9	1	4 years ago	JPEG-Decoder/704	Verilog Code for a JPEG Decoder
22	14	0	3 years ago	AD9361_TX_MSK/705	A project demonstrate how to config ad9361 to TX mode and how to transmit MSK
21	7	3	6 months ago	OpenHBMC/706	Open-source high performance AXI4-based HyperRAM memory controller
21	6	1	1 year, 9 months ago	nand2tetris-iverilog/707	A 16-bit Hack CPU from scratch on FPGA.
21	4	0	2 months ago	icesid/708	A C64 SID Chip recreation in FPGA
21	1	0	8 days ago	ucisc/709	None
21	7	0	6 years ago	CoCo3FPGA/710	FPGA implementation of the TRS-80 Color Computer 3 in Verilog, by Gary Becker et al.
21	11	1	8 years ago	neural-hardware/711	Verilog library for implementing neural networks.
21	3	0	11 months ago	xiaohaizi_cpu/712	None
21	3	1	2 years ago	core_usb_fs_phy/713	USB Full Speed PHY
22	21	1	2 years ago	FPGA_CryptoNight_V7/714	FPGA CryptoNight V7 Minner
25	11	3	9 months ago	nica/715	An infrastructure for inline acceleration of network applications
21	14	0	3 years ago	Zynq-7000-DPU-TRD/716	Zynq-7000 DPU TRD
21	0	0	2 days ago	NuBusFPGA/717	Stuff to put a FPGA in a NuBus Macintosh
22	16	1	4 years ago	c64-dodgypla/718	Commodore 64 PLA replacement
22	17	2	4 years ago	up5k-demos/719	ice40 UltraPlus demos
22	7	3	2 years ago	UPduino-v2.1/720	UPduino
22	10	0	5 years ago	Centaur/721	Centaur, a framework for hybrid CPU-FPGA databases
21	4	0	2 years ago	mips-cpu/722	💻 A 5-stage pipeline MIPS CPU implementation in Verilog.
20	5	34	a month ago	TART/723	Transient Array Radio Telescope
21	9	0	3 years ago	arm_vhdl/724	Portable FPGA project based on the ARM DesignStart bundle with ARM Cortex-M3 processor
22	6	7	6 years ago	vector06cc/725	Вектор-06ц в ПЛИС / Vector-06c in FPGA
21	18	1	2 years ago	gemac/726	Gigabit MAC + UDP/TCP/IP offload Engine
22	0	0	1 year, 6 months ago	MIPS54SP-Lifesaver/727	None
20	4	3	8 months ago	StereoCensus/728	Verilog Implementation of the Census Transform Stereo Vision algorithm
20	16	0	1 year, 6 months ago	FPGA_DevKit_HX1006A/729	None
20	9	0	2 years ago	CyNAPSEv11/730	The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
20	11	8	5 years ago	pars/731	None
20	13	9	6 months ago	Archie_MiSTer/732	Acorn Archimedes for MiSTer
23	14	2	1 year, 11 months ago	KWS-SoC/733	This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.
20	12	0	9 years ago	ovs-hw/734	An open source hardware engine for Open vSwitch on FPGA
21	4	0	3 years ago	verifla/735	Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm
21	2	0	1 year, 1 month ago	SmolDVI/736	Low-area DVI experiment for iCE40 UP5k and HX1k FPGAs
22	4	0	5 years ago	MesaBusProtocol/737	Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
21	5	1	4 years ago	anlogic-picorv32/738	Optimized picorv32 core for anlogic FPGA
20	7	0	6 months ago	DigitalLogic-Autumn2020/739	复旦大学 数字逻辑与部件设计实验 2020秋
20	10	0	2 years ago	XCryptCore/740	Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
21	2	0	6 years ago	QuickSilverNEO/741	None
21	6	0	5 years ago	computer-systems-ucas/742	中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
20	7	0	2 years ago	aes/743	Advanced encryption standard implementation in verilog.
20	2	1	6 years ago	icestick-vga-test/744	Test of ICEstick PLL usage with Yosys/Arachne-PNR/Icetools
21	1	0	2 years ago	BusPirateUltraHDL/745	Verilog for the Bus Pirate Ultra FPGA
20	9	7	6 years ago	pifo-hardware/746	None
20	11	0	2 years ago	FPGA_DOCS/747	None
20	14	7	5 months ago	rp_lock-in_pid/748	Lock-in and PID application for RedPitaya enviroment
20	0	0	2 hours ago	analogue-pong/749	FPGA Pong implementation, specifically for the Analogue Pocket
20	16	10	2 years ago	UHD-Fairwaves/750	Fairwaves version of the UHD drivers, tweaked to support Fairwaves UmTRX.
20	1	0	2 years ago	Life_MiSTer/751	Conway's Game of Life in FPGA
20	4	0	1 year, 10 months ago	3DORGB/752	RGB Project for most 3DO consoles.
20	6	0	2 years ago	bitcoin_mining/753	Simple test fpga bitcoin miner
24	9	0	11 years ago	video_stream_scaler/754	Video Stream Scaler
20	1	0	4 years ago	UART2NAND/755	Interface for exposing raw NAND i/o over UART to enable pc-side modification.
20	11	0	1 year, 8 months ago	Reindeer_Step/756	Reindeer Soft CPU for Step CYC10 FPGA board
20	0	0	2 months ago	c128-verilog/757	Verilog code for C128 custom chips
20	6	0	2 years ago	Digital_Front_End_Verilog/758	None
20	2	0	5 years ago	RiverRaidFPGA/759	River Raid game on FPGA
20	6	1	1 year, 4 months ago	k1801/760	1801 series ULA reverse engineering
19	6	1	4 years ago	UPDuino-OV7670-Camera/761	Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module
19	3	0	4 years ago	fpga-sram/762	mystorm sram test
19	13	0	5 years ago	axi-ddr3/763	学习AXI接口，以及xilinx DDR3 IP使用
19	3	1	14 days ago	Home-Brew-Computer/764	SystemOT, yet another home brew cpu.
19	6	4	3 years ago	fLaCPGA/765	Implementation of fLaC encoder/decoder for FPGA
19	7	0	3 years ago	FPGA_SYNC_ASYNC_FIFO/766	FPGA 同步FIFO与异步FIFO
19	1	0	1 year, 4 months ago	biggateboy/767	WIP Big FPGA Gameboy
19	1	0	4 years ago	VerilogCommon/768	A repo of basic Verilog/SystemVerilog modules useful in other circuits.
22	9	1	1 year, 7 months ago	qemu-hdl-cosim/769	VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
22	5	0	11 years ago	opengg/770	OpenGL-like graphics pipeline on a Xilinx FPGA
21	12	0	6 years ago	Hardware_circular_buffer_controller/771	This is a circular buffer controller used in FPGA.
19	8	6	1 year, 2 months ago	shapool-core/772	FPGA core for SHA256d mining targeting Lattice iCE40 devices.
20	7	0	9 years ago	mcs-4/773	4004 CPU and MCS-4 family chips
20	7	0	1 year, 3 months ago	ps-fpga/774	The PS-FPGA project (top level)
23	3	0	4 years ago	8bit-computer/775	Simple 8-bit computer build in Verilog
21	3	0	7 months ago	dbgbus/776	A collection of debugging busses developed and presented at zipcpu.com
20	2	2	2 months ago	gateware/777	IP submodules, formatted for easier CI integration
24	1	0	5 months ago	usb_cdc/778	Full Speed USB interface for FPGA and ASIC designs
19	12	1	7 years ago	AHB_Bus_Matrix/779	None
19	10	0	18 years ago	jtag/780	JTAG Test Access Port (TAP)
19	7	0	4 years ago	Autonomous-Drone-Design/781	Design real-time image processing, object recognition and PID control for Autonomous Drone.
19	16	0	3 years ago	gameduino/782	My own version of the @JamesBowman's Gameduino file repository
19	2	0	7 years ago	BCOpenMIPS/783	跟着《自己动手写 CPU》书上写的 OpenMIPS CPU。
19	3	0	5 years ago	OpenMIPS/784	OpenMIPS——《自己动手写CPU》处理器部分
21	10	1	8 years ago	apbi2c/785	APB to I2C
19	13	1	5 years ago	lisnoc/786	LIS Network-on-Chip Implementation
19	2	2	1 year, 9 months ago	raiden/787	Raiden project
19	6	0	1 year, 4 months ago	RiftCore/788	RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
19	1	0	7 months ago	ARMLEG/789	Multi-cycle pipelined ARM-LEGv8 CPU with Forwarding and Hazard Detection.
21	3	0	6 years ago	verilog_tutorials_BB/790	verilog tutorials for iCE40HX8K Breakout Board
23	13	0	2 years ago	Verilog-Adders/791	Implementing Different Adder Structures in Verilog
20	2	0	9 months ago	ws2812-core/792	verilog core for ws2812 leds
22	5	0	1 year, 8 months ago	NeoChips/793	Replacement "chips" for NeoGeo systems
19	2	28	7 months ago	rapcores/794	Robotic Application Processor
19	5	4	12 days ago	MacroPlacement/795	Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source
18	4	0	10 years ago	verilog-vga-controller/796	A very simple VGA controller written in verilog
17	2	0	5 years ago	PitchShifter/797	Change the pitch of your voice in real-time!
21	5	1	2 years ago	max2-audio-dac/798	24-bit Stereo Audio DAC for Raspberry Pi
17	0	1	2 years ago	TurboMaster/799	Reverse Engineering of the Schnedler Systems 4MHz TurboMaster accelerator cartridge for the Commodore 64
19	2	0	3 months ago	Silixel/800	Exploring gate level simulation
18	3	0	3 years ago	flapga-mario/801	FlaPGA Mario - A flappy-bird like video game implemented in Verilog for Basys3
18	4	1	5 years ago	handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/802	None
18	3	0	7 months ago	libfpga/803	Reusable Verilog 2005 components for FPGA designs
18	7	0	6 years ago	PCIE_AXI_BRIDGE/804	Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
18	5	9	10 years ago	hdl_devel/805	A new CASPER toolflow based on an HDL primitives library
19	13	3	1 year, 6 months ago	MemTest_MiSTer/806	None
18	3	1	3 months ago	DDR/807	A simple DDR3 memory controller
23	4	1	1 year, 3 months ago	subservient/808	Small SERV-based SoC primarily for OpenMPW tapeout
18	9	4	2 years ago	verilog-uart/809	Simple 8-bit UART realization on Verilog HDL.
18	4	0	2 months ago	General-Slow-DDR3-Interface/810	A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
19	6	0	2 years ago	RePLIA/811	FPGA Based lock in amplifier
18	0	0	2 years ago	risc-v/812	RISC-VのCPU作った
20	6	0	3 years ago	OV7670_NEXYS4_Verilog/813	This code is used to connect the OV7670 Camera to a NEXYS4 and then display the image on a monitor in Verilog
18	1	0	3 years ago	spi_tb/814	CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys
18	1	0	2 months ago	BubbleDrive8/815	Konami Bubble System Bubble Memory Cartridge FBM-#101 Emulator
18	9	0	3 years ago	FIFO_-asynchronous/816	异步FIFO的内部实现
18	1	0	1 year, 7 months ago	ics-adpcm/817	Programmable multichannel ADPCM decoder for FPGA
18	7	0	5 years ago	riffa2/818	Full duplex version of KastnerRG/riffa#30
20	10	0	1 year, 3 months ago	vivado-ip-cores/819	IP Cores that can be used within Vivado
21	4	1	2 months ago	DFB/820	David's Falcon Booster
18	10	0	1 year, 2 months ago	eFPGA---RTL-to-GDS-with-SKY130/821	This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
18	0	0	6 months ago	Five-stage-pipeline-CPU/822	A CPU with 52 instructions implemented by Verilog
18	9	0	2 years ago	FFT_ChipDesign/823	A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
25	16	0	4 years ago	FPGA_SM4/824	FPGA implementation of Chinese SM4 encryption algorithm.
18	3	1	1 year, 6 months ago	UltiMem64/825	Commodore 64 Internal RAM Expansion with integrated MMU
18	14	0	5 years ago	AXI_BFM/826	AXI4 BFM in Verilog
22	11	0	4 years ago	posture_recognition_CNN/827	To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different responses to all kinds of human's postures. But the process is very difficult as well, because usually it is very slow and power-consuming, and requires a very large memory space. Here we focus on real-time posture recognition, and try to make the machine "know" what posture we make. The posture recognition system is consisted of DE10-Nano SoC FPGA Kit, a camera, and an HDMI monitor. SoC FPGA captures video streams from the camera, recognizes human postures with a CNN model, and finally shows the original video and classification result (standing, walking, waving, etc.) via HDMI interface.
18	3	5	2 years ago	MiSTer-Arcade-SEGASYS1/828	FPGA implementation of SEGA SYSTEM 1 arcade board
21	6	1	9 months ago	SortingNetwork/829	Implement a bitonic sorting network on FPGA
18	9	0	3 years ago	A-Single-Path-Delay-32-Point-FFT-Processor/830	A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.
19	15	0	2 years ago	digital_lab/831	Laboratory works for digital electronics course in Kyiv Polytechnic Institute, Department of Design of Electronic Digital Equipment, Electronics faculty
19	0	0	3 years ago	gameboy-sound-chip/832	None
18	6	0	4 months ago	Systolic-array-implementation-in-RTL-for-TPU/833	IC implementation of Systolic Array for TPU
18	4	0	2 years ago	riscv_sbc/834	A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
19	6	0	3 years ago	tinyfpga-bx-game-soc/835	A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games
18	9	1	2 years ago	DRUM/836	The Verilog source code for DRUM approximate multiplier.
19	2	1	10 months ago	risc8/837	Mostly AVR compatible FPGA soft-core
17	11	0	3 years ago	wb_sdram_ctrl/838	SDRAM controller with multiple wishbone slave ports
17	12	0	6 years ago	Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM/839	Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
17	5	1	6 years ago	mips/840	Mips处理器仿真设计
17	9	0	9 months ago	zuma-fpga/841	Fine Grain FPGA Overlay Architecture and Tools
18	5	0	2 years ago	Jaguar_MiSTer_new/842	None
21	3	0	3 months ago	cpld-6502/843	6502 CPU in 4 small CPLDs
17	3	0	3 months ago	UETRV_ESoC/844	None
17	6	0	a month ago	verilog-65C02-fsm/845	None
17	4	1	5 years ago	Menu_MIST/846	Dummy FPGA core to display menu at startup
21	2	0	6 months ago	NoobsCpu-8bit/847	A simple 8bit CPU.
18	7	1	5 years ago	iir-bandstop-filter/848	Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic
17	2	0	3 years ago	pinky8bitcpu/849	Pinky (8-bit CPU) written in Verilog and an Assembler written in Python 3
23	11	0	13 years ago	verilog_cordic_core/850	configurable cordic core in verilog
17	7	5	5 years ago	polaris/851	RISC-V RV64IS-compatible processor for the Kestrel-3
19	68	10	a month ago	caravel_user_project_analog/852	None
18	4	2	6 years ago	icestickPWM/853	Simple USB to PWM Peripheral using Lattice iCEStick (Hackaday demo)
17	0	0	4 years ago	sdaccel_chisel_integration/854	Chisel Project for Integrating RTL code into SDAccel
17	0	0	2 months ago	DSTB/855	David's ST Booster
17	14	0	8 years ago	logi-pong-chu-examples/856	example code for the logi-boards from pong chu HDL book
18	4	0	3 years ago	Flappy-Bird/857	FPGA program :VGA-GAME
17	6	4	2 years ago	yosys-bench/858	Benchmarks for Yosys development
20	6	1	7 years ago	nes_mappers/859	NES mappers
18	13	14	8 months ago	sancus-core/860	Minimal OpenMSP430 hardware extensions for isolation and attestation
17	2	5	2 years ago	fluent10g/861	Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet
18	0	0	4 months ago	TwoWireDebug/862	Yet Another Debug Transport
17	3	0	1 year, 4 months ago	sub-25-ns-nasdaq-itch-fpga-parser/863	None
19	2	1	1 year, 8 months ago	legv8/864	LEGv8 CPU implementation and some tools like a LEGv8 assembler
20	5	0	4 months ago	CortexM0_SoC_Task/865	Step by step tutorial for building CortexM0 SoC
18	6	0	3 years ago	HDLBits_Practice_verilog/866	This is a practice of verilog coding
18	12	0	6 years ago	heterosim/867	HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design space exploration is enabled by a wide range of system configurations. A complete simulation flow with compiler support is provided so that a full system simulation can be performed with various performance metrics returned.
17	3	0	7 months ago	nano-cpu32k/868	Superscalar out-of-order RISC core (with Cache& MMU) and SoC, supporting GNU toolchain & Linux 4.20 kernel, having been verified on Xilinx Kintex-7 FPGA.
17	12	0	3 years ago	32-bit-MIPS-Processor/869	A 32-bit MIPS processor used Altera Quartus II with Verilog.
17	4	0	10 years ago	oc-i2c/870	I2C controller core from Opencores.org
17	6	0	8 years ago	FPGA_Stereo_Depth_Map/871	None
17	1	0	10 months ago	Verilaptor/872	None
18	10	1	7 years ago	i2s/873	i2s core, with support for both transmit and receive
17	6	2	3 years ago	TDC/874	Verilog implementation of a tapped delay line TDC
17	4	0	10 years ago	amber_samples/875	None
17	6	2	1 year, 5 months ago	Simulator_CPU/876	Pipeline CPU of MIPS architecture with L1 Data Cache by Verilog
18	6	0	4 years ago	Nexys-4-DDR-Ethernet-Mac/877	Ethernet MAC for the Digilent Nexys 4 DDR FPGA.
17	5	0	4 years ago	DSITx/878	FPGA implementation of DSITx (single lane) used in conjunction with ipod nano 7th gen display
17	4	0	1 year, 3 months ago	arrowzip/879	A ZipCPU based demonstration of the MAX1000 FPGA board
17	10	0	5 years ago	Curso-Electronica-Digital-para-makers-con-FPGAs-Libres/880	Curso de 35h sobre el diseño de sistemas digitales usando FPGAs libres, orientado para makers
17	0	1	1 year, 1 month ago	plaid-bib-cpld/881	A replica of the Ad Lib MCA sound card, now with a CPLD instead of the bus interface chip
17	10	1	4 years ago	FPGA-Mnist/882	Hand written number classification done in hardware (De1-SoC board) using neural networks
17	3	1	9 years ago	uart_dpi/883	DPI module for UART-based console interaction with Verilator simulations
18	14	0	2 years ago	matrix-voice-fpga/884	HDL code for the MATRIX Voice's Spartan 6 FPGA http://voice.matrix.one
17	2	1	4 years ago	mikrobus-upduino/885	Dual MikroBUS board for Upduino 2 FPGA
16	5	0	3 years ago	FPGA_Vending_Machine/886	东南大学信息学院大三短学期FPGA课程设计——售货机
16	3	0	7 years ago	parallel-processor-design/887	Super scalar Processor design
17	0	1	1 year, 3 months ago	Deep-DarkFantasy/888	Global Dark Mode for ALL apps on ANY platforms.
17	5	0	2 years ago	systolic-array-matrix-multiplier/889	A systolic array matrix multiplier
18	14	0	4 years ago	single-cycle-CPU/890	单周期CPU设计与实现
16	8	0	7 years ago	Multiported-RAM/891	Modular Multi-ported SRAM-based Memory
16	5	1	2 years ago	pipeline-mips-verilog/892	A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall
17	4	0	7 years ago	Computer-Architecture/893	A pipelined MIPS CPU supporting 31 MIPS instructions, interrupt and cache.
20	5	0	6 years ago	cpus-pdp8/894	FPGA based PDP-8/i clone in verilog. Includes several TSS/8 sources and utiltities to build from source
17	6	2	7 years ago	Modular-Exponentiation/895	Verilog Implementation of modular exponentiation using Montgomery multiplication
16	4	0	2 years ago	noop-lo/896	A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
16	3	1	10 months ago	chad/897	A self-hosting Forth for J1-style CPUs
17	5	0	6 years ago	icestick/898	Simple demo for Lattice iCEstick board as seen on Hackaday
18	3	0	6 years ago	FPGA/899	computer hardware system including ps2/vga with tank war game in verilog and mips
16	2	0	7 years ago	WitnessProtection/900	in FPGA
17	9	0	4 years ago	TinyFPGA-SoC/901	Opensource building blocks for TinyFPGA microcontrollers and retro computers.
15	21	1	4 years ago	moneroasic/902	Cryptonight Monero Verilog code for ASIC
16	8	0	8 years ago	OpenProjects/903	None
16	9	0	2 months ago	dma-bench/904	None
17	16	0	6 years ago	Asynchronous-FIFO/905	Asynchronous fifo in verilog
17	11	1	8 months ago	Radix-2-FFT/906	Verilog code for a circuit implementation of Radix-2 FFT
16	2	0	3 months ago	N-GO/907	None
16	9	0	3 years ago	DigitalAlarmClock/908	njtech digital design. a fpga digital alarm system with Nexys A7 100T
16	5	0	7 years ago	orgexp/909	Computer Organization Experiment, Shi Qingsong, Zhejiang University.
17	10	0	4 years ago	FFTVisualizer/910	This project demonstrates DSP capabilities of Terasic DE2-115
18	9	0	3 years ago	Computer-Organization-and-Architecture-LAB/911	Solution to COA LAB Assgn, IIT Kharagpur
16	3	0	4 years ago	bextdep/912	Reference Hardware Implementations of Bit Extract/Deposit Instructions
16	14	1	3 years ago	digital-design-lab-manual/913	Digital Design Labs
16	0	0	2 years ago	wbfmtx/914	A wishbone controlled FM transmitter hack
17	3	0	2 years ago	Nu6509/915	Emulate a 6509 with a 6502
16	5	0	11 months ago	mdu/916	M-extension for RISC-V cores.
16	1	0	2 months ago	verilog/917	None
16	7	0	2 years ago	aq_mipi_csi2rx_ultrascaleplus/918	None
16	14	1	5 years ago	fpga-nn/919	NN on FPGA
16	3	0	a month ago	Arcade-TMNT_MiSTer/920	None
16	7	1	6 years ago	dnn-sim/921	None
18	14	1	3 years ago	FPGA_rtime_HDR_video/922	We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.
19	5	0	1 year, 2 months ago	core_usb_bridge/923	USB -> AXI Debug Bridge
16	6	0	3 years ago	cdsAsync/924	cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
15	6	1	2 years ago	ZBC---The-Zero-Board-Computer/925	Based heavily on zet.aluzina.org and Terasic DE0
16	4	0	8 years ago	magukara/926	FPGA-based open-source network tester
16	3	1	2 years ago	TMR/927	Triple Modular Redundancy
17	5	1	8 months ago	saxonsoc-ulx3s-bin/928	The binaries for SaxonSoc Linux and other configurations
17	2	0	2 years ago	color3/929	Information about eeColor Color3 HDMI FPGA board
16	4	0	4 years ago	crap-o-scope/930	crap-o-scope scope implementation for icestick
16	9	0	8 years ago	Verilog-I2C-Slave/931	Verilog I2C Slave
16	1	0	1 year, 11 months ago	core_mmc/932	MMC (and derivative standards) host controller
16	15	1	10 years ago	MIPS-in-Verilog/933	An implementation of MIPS single cycle datapath in Verilog.
16	4	2	3 years ago	PDP1_MiSTer/934	PDP-1 for MiSTer
17	2	0	6 months ago	litespih4x/935	SPI flash MITM and emulation (QSPI is a WIP)
16	3	0	4 months ago	tee-hardware/936	TEE hardware - based on the chipyard repository - hardware to accelerate TEE
16	9	0	5 years ago	ice40-stm32-sdram/937	Test code to talk from STM32 MCU over FSMC to SDRAM on ICE40 FPGA
16	3	0	1 year, 5 months ago	hello-verilog/938	Hello Verilog by Mac + VSCode
17	2	0	2 years ago	ice40_8bitworkshop/939	"Designing Video Game Hardware in Verilog" in iCE40HX8K Breakout Board.
16	8	0	8 months ago	ADC-lvds/940	Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
16	10	0	1 year, 10 months ago	sha3/941	FIPS 202 compliant SHA-3 core in Verilog
20	13	1	6 years ago	i2c-master/942	An i2c master controller implemented in Verilog
16	6	0	10 years ago	openmsp430/943	openMSP430 CPU core (from OpenCores)
16	7	0	3 years ago	up5k_vga/944	A complete 65C02 computer with VGA output on a Lattice Ultra Plus FPGA
16	1	0	1 year, 3 months ago	arty-videocap/945	Repeat and capture the video signal with Digilent Arty-A7 and a video extender board.
16	5	1	1 year, 8 months ago	tcam/946	TCAM ( Ternary Content-Addressable Memory) on Verilog
16	14	0	4 years ago	riscvv/947	an open source uvm verification platform for e200 (riscv)
19	6	0	3 months ago	HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine/948	HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx Kintex Ultra Plus brand FPGAs and embedded RISC-V as trainer.
16	2	0	a month ago	STEPFPGA-MXO2Core/949	The codes accompanied with STEPFPGA tutorial book
15	1	0	11 years ago	Oberwolfach-explorations/950	collaboration on work in progress
15	15	1	7 months ago	fpga-sdk-prj/951	FPGA-based SDK projects for SCRx cores
16	22	2	4 years ago	FPGA-Keccak-Miner/952	None
16	1	0	2 years ago	FPGAGameBoy/953	an implementation of the GameBoy in Verilog
19	6	0	1 year, 6 months ago	caravel_amsat_txrx_ic/954	None
17	6	0	8 years ago	80211scrambler/955	Tools for working with the 802.11B scrambler when writing Packet-in-Packet exploits.
15	19	0	3 years ago	2FSK-2PSK-2DPSK-QPSK-code-and-decode/956	用Verilog语言编写，实现2FSK，2PSK, 2DPSK, QPSK调制解调
15	1	0	4 years ago	UPduino-Mecrisp-Ice-15kB/957	Mecrisp-Ice Forth running on 16bit j1a processor (iCE40UP5k based UPduino board) with full 15kB of bram and 48bit Floating Point Library.
16	4	0	1 year, 5 months ago	bitmips2019/958	None
14	5	0	1 year, 2 months ago	LittleChip/959	Little RISC-V 3-stage Pipeline CPU
15	3	15	15 days ago	simbricks/960	Main Repository for the SimBricks Modular Full-System Simulation Framework.
15	4	1	6 years ago	dyract/961	DyRACT Open Source Repository
19	11	2	4 years ago	HLS_Legup/962	None
17	4	1	1 year, 1 month ago	ecp5_jtag/963	Use ECP5 JTAG port to interact with user design
15	3	0	9 months ago	rotfpga/964	A reconfigurable logic circuit made of identical rotatable tiles.
16	2	0	3 years ago	fpga_1943/965	Verilog re-implementation of the famous CAPCOM arcade game
14	10	0	7 years ago	uart/966	Verilog uart receiver and transmitter modules for De0 Nano
15	1	0	29 days ago	MiSTerFPGA_YC_Encoder/967	All work releated to the YC / NTSC & PAL Encoder for MiSTerFPGA
15	3	0	1 year, 3 months ago	core_axi_cache/968	128KB AXI cache (32-bit in, 256-bit out)
16	14	0	5 months ago	Pmod-I2S2/969	None
15	2	0	3 years ago	Conways-Game-of-Life-with-Vlang/970	Conway's life game in V
15	6	0	1 year, 3 months ago	ethernet-fmc-processorless/971	Example designs for using Ethernet FMC without a processor (ie. state machine based)
16	5	1	5 years ago	fpga-wpa-psk-bruteforcer/972	WPA-PSK cracking for FPGA devices
15	2	0	3 years ago	CNN-Based-FPGA/973	CNN implementation based FPGA
15	9	4	1 year, 6 months ago	Arcade-GnG_MiSTer/974	Arcade Ghosts'n Goblins for MiSTer
16	9	0	1 year, 5 months ago	DVP_to_UDP/975	Uncompressed video uver UDP using 1000BASE-T Ethernet on Cyclone IV FPGA
15	3	1	3 years ago	Arty-A7-35-XADC/976	None
17	16	1	12 years ago	dvb_s2_ldpc_decoder/977	DVB-S2 LDPC Decoder
15	4	0	1 year, 3 months ago	icozip/978	A ZipCPU demonstration port for the icoboard
18	2	0	2 years ago	Nu6510/979	65(C)02 to 6510/8500 converter
17	5	1	2 years ago	core_usb_uart/980	USB serial device (CDC-ACM)
15	6	0	5 years ago	My_Opensource_AZPR_SOC/981	根据最近看的一本书编写的对应RTL以及Testbench
15	1	0	4 months ago	fromthetransistor/982	From the Transistor to the Web Browser, a rough outline for a 12 week course.
16	4	0	10 years ago	bfcpu2/983	A pipelined brainfuck softcore in Verilog
15	3	1	2 years ago	tv80/984	TV80 Z80-compatible microprocessor
15	225	0	5 years ago	ece4750-tut4-verilog/985	ECE 4750 Tutorial 4: Verilog Hardware Description Language
15	2	34	a day ago	yosys-systemverilog/986	SystemVerilog support for Yosys
16	6	0	6 years ago	gng/987	Gaussian noise generator Verilog IP core
15	4	2	2 years ago	SNKVerilog/988	Verilog definitions of custom SNK chips, for repairs and preservation.
15	1	0	5 years ago	iCEstick-hacks/989	iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter
15	3	1	8 years ago	descrypt-ztex-bruteforcer/990	descrypt-ztex-bruteforcer
15	0	0	4 years ago	RISCV-CPU/991	SJTU Computer Architecture(1) Hw
15	4	0	4 years ago	RSAonVerilog/992	Implementation of RSA algorithm on FPGA using Verilog
15	5	0	3 years ago	yoloRISC/993	A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
17	10	2	1 year, 2 months ago	alice5/994	SPIR-V fragment shader GPU core based on RISC-V
15	6	1	15 hours ago	jtdd/995	Double Dragon FPGA core
15	10	0	7 years ago	NetFPGA-10G-UPB-OpenFlow/996	An OpenFlow implementation for the NetFPGA-10G card
17	10	0	3 years ago	RISC-Processor/997	32-bit RISC processor
17	6	1	2 years ago	net2axis/998	Verilog network module. Models network traffic from pcap to AXI-Stream
15	6	2	7 years ago	Pano-Logic-Zero-Client-G2-FPGA-Demo/999	Constraints file and Verilog demo code for the Pano Logic Zero Client G2
15	22	0	1 year, 2 months ago	CE202-LC-Lab-Manual/1000	Manual and Template Sources of Logic Circuit Laboratory (Verilog Templates)