forked from tonioni/WinUAE
-
Notifications
You must be signed in to change notification settings - Fork 0
/
ar.cpp
2227 lines (2021 loc) · 58.2 KB
/
ar.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* UAE Action Replay 1/2/3/1200 and HRTMon support
*
* (c) 2000-2006 Toni Wilen <twilen@arabuusimiehet.com>
* (c) 2003 Mark Cox <markcox@email.com>
*
* Action Replay 1200 (basically old version of HRTMon):
*
* 256k ROM at 0x800000
* 64k RAM at 0x880000
* status register at 0x8c0000 (bit 3 = freeze button, bit 4 = hide)
* custom register writes stored at 0x88f000
* CIA-A at 0x88e000
* CIA-B at 0x88d000
* freeze button = bus error + rom mapped at 0x0
*
* 14.06.2006 first implementation
*
* Action Replay 2/3:
*
* Tested with AR3 ROM version 3.09 (10/13/91) and AR2 2.12 (12/24/90)
*
* Found to work for the following roms by Mark Cox:
* (Yes the date format is inconsistent, i just copied it straight from the rom)
* 1.15
* 2.14 22/02/91 dd/mm/yy
* 3.09 10/13/91 mm/dd/yy
* 3.17 12/17/91 mm/dd/yy
*
* This patch also makes AR3 compatible with KickStart's other than 1.3
* (ROM checksum error is normal with KS != 1.3)
* NOTE: AR has problems with 68020+ processors.
* For maximum compatibility select 68000/68010 and A500 speed from UAE
* options.
*
* How to rip Action Replay 1/2/3 ROM:
*
* Find A500 with AR1/2/3, press 'freeze'-button
*
* type following:
*
* AR1:
* lord olaf<RETURN>
*
* AR2 or AR3:
* may<RETURN>
* the<RETURN>
* force<RETURN>
* be<RETURN>
* with<RETURN>
* you<RETURN>
* new<RETURN> (AR3 only)
*
* AR1: 64K ROM is visible at 0xf00000-0xf0ffff
* and 16K RAM at 0x9fc000-0x9fffff
* AR2: 128K ROM is visible at 0x400000-0x41ffff
* AR3: 256K ROM is visible at 0x400000-0x43ffff
* and 64K RAM at 0x440000-0x44ffff
*
* following command writes ROM to disk:
*
* AR1: sm ar1.rom,f00000 f10000
* AR2: sm ar2.rom,400000 420000
* AR3: sm ar3.rom,400000 440000
*
* NOTE: I (mark) could not get the action replay 1 dump to work as above.
* (also, it will only dump to the action replay special disk format)
* To dump the rom i had to :
* 1. Boot the a500 and start a monitor (e.g. cmon).
* 2. Use the monitor to allocate 64k memory.
* 3. Enter the action replay.
* 4. Enter sysop mode.
* 5. Copy the rom into the address the monitor allocated.
* 6. Exit the action replay.
* 7. Save the ram from the monitor to disk.
*
* I DO NOT REPLY MAILS ASKING FOR ACTION REPLAY ROMS!
*
* AR2/3 hardware notes (not 100% correct..)
*
* first 8 bytes of ROM are not really ROM, they are
* used to read/write cartridge's hardware state
*
* 0x400000: hides cartridge ROM/RAM when written
* 0x400001: read/write HW state
* 3 = reset (read-only)
* 2 = sets HW to activate when breakpoint condition is detected
* 1 = ???
* 0 = freeze pressed
* 0x400002/0x400003: mirrors 0x400000/0x400001
* 0x400006/0x400007: when written to, turns chip-ram overlay off
*
* breakpoint condition is detected when CPU first accesses
* chip memory below 1024 bytes and then reads CIA register
* $BFE001.
*
* cartridge hardware also snoops CPU accesses to custom chip
* registers (DFF000-DFF1FE). All CPU custom chip accesses are
* saved to RAM at 0x44f000-0x44f1ff. Note that emulated AR3 also
* saves copper's custom chip accesses. This fix stops programs
* that try to trick AR by using copper to update write-only
* custom registers.
*
* 30.04.2001 - added AR2 support
* 21.07.2001 - patch updated
* 29.07.2002 - added AR1 support
* 11.03.2003 - added AR1 breakpoint support, checksum support and fixes. (Mark Cox)
*
*/
/* AR2/3 'NORES' info.
* On ar2 there is a 'nores' command,
* on ar3, it is accessible using the mouse.
* This command will not work using the current infrastructure,
* so don't use it 8).
*/
/* AR1 Breakpoint info.
* 1.15 If a breakpoint occurred. Its address is stored at 9fe048.
* The 5 breakpoint entries each consisting of 6 bytes are stored at 9fe23e.
* Each entry contains the breakpoint long word followed by 2 bytes of the original contents of memory
* that is replaced by a trap instruction in mem.
* So the table finishes at 9fe25c.
*/
/* How AR1 is entered on reset:
* In the kickstart (1.3) there is the following code:
* I have marked the important lines:
*
* fc00e6 lea f00000,a1 ; address where AR1 rom is located.
* fc00ec cmpa.l a1,a0
* fc00ee beq fc00fe.s
* fc00f0 lea C(pc), a5
* fc00f4 cmpi.w #1111,(a1) ; The first word of the AR1 rom is set to 1111.
* fc00f8 bne fc00fe.s
* fc00fa jmp 2(a1) ; This is the entry point of the rom.
*/
/* Flag info:
* AR3:'ARON'. This is unset initially. It is set the first time you enter the AR via a freeze.
* It enables you to keep the keyboard buffer and such.
* If this flag is unset, the keyboard buffer is cleared, the breakpoints are deleted and ... */
/* AR3:'PRIN'. This flag is unset initially. It is set at some point and when you switch to the 2nd screen
* for the first time it displays all the familiar text. Then unsets 'PRIN'.
*/
/* Super IV:
*
* Possible "ROM" addresses ("ROM" is loaded from disk to Amiga memory)
* - 0xd00000
* - 0xc00000
* - 0x080000
*
* CIA-A: 0xb40000 (0x000, 0x100,...)
* CIA-B: 0xb40001 (0x001, 0x101,...)
* Custom: 0xe40000
*
* NOTE: emulation also supports 0xd00000 relocated "rom"-images
*/
/* X-Power 500:
*
* ROM: 0xe20000 (128k)
* RAM: 0xf20000 (64k)
* CIA-A: 0xf2fc00 (00,02,04,...)
* CIA-B: 0xf2fc01 (01,03,05,...)
* Custom: 0xf2fc00 (from 0x20->)
*/
/* Nordic Power:
*
* ROM: 0xf00000 (64k, mirrored at 0xf10000)
* RAM: 0xf40000 (32k, mirrored at 0xf48000 - 0xf5ffff)
* CIA-A: 0xf43c00 (00,02,04,...)
* CIA-B: 0xf43c01 (01,03,05,...)
* Custom: 0xf43c00 (from 0x20->)
* addresses 0 to 1023: 0xf40000 (weird feature..)
*/
/* X-Power and Nordic Power ROM scrambling
*
* Data lines are swapped.
* Address lines are XOR'd (0x817F) and swapped.
*
* Even (middle) ROM
*
* Data: 0-3,1-6,2-0,3-4,4-7,5-5,6-1,7-2
* Addr: 0-7,1-1,2-2,3-11,4-12,5-0,6-13,7-14,8-8,9-3,10-5,11-6,12-4,13-10,14-9,15-15
*
* Odd (corner) ROM
*
* Data: 0-2,1-3,2-4,3-5,4-6,5-7,6-0,7-1
* Addr: 0-3,1-6,2-5,3-7,4-9,5-12,6-14,7-13,8-8,9-11,10-10,11-1,12-0,13-4,14-2,15-15
*
*/
#include "sysconfig.h"
#include "sysdeps.h"
#include "options.h"
#include "uae.h"
#include "memory.h"
#include "rommgr.h"
#include "custom.h"
#include "newcpu.h"
#include "zfile.h"
#include "ar.h"
#include "savestate.h"
#include "crc32.h"
#include "akiko.h"
#define DEBUG
#ifdef DEBUG
#define write_log_debug write_log
#else
#define write_log_debug
#endif
static TCHAR *cart_memnames[] = { NULL, L"hrtmon", L"arhrtmon", L"superiv" };
#define ARMODE_FREEZE 0 /* AR2/3 The action replay 'freeze' button has been pressed. */
#define ARMODE_BREAKPOINT_AR2 2 /* AR2: The action replay is activated via a breakpoint. */
#define ARMODE_BREAKPOINT_ACTIVATED 1
#define ARMODE_BREAKPOINT_AR3_RESET_AR2 3 /* AR2: The action replay is activated after a reset. */
/* AR3: The action replay is activated by a breakpoint. */
#define CART_AR 0
#define CART_HRTMON 1
#define CART_AR1200 2
#define CART_SUPER4 3
uae_u8 ar_custom[2*256];
uae_u8 ar_ciaa[16], ar_ciab[16];
static int hrtmon_ciadiv = 256;
int hrtmon_flag = ACTION_REPLAY_INACTIVE;
static int cart_type;
static uae_u8 *hrtmemory = 0, *hrtmemory2 = 0, *hrtmemory3 = 0;
static uae_u8 *armemory_rom = 0, *armemory_ram = 0;
static uae_u32 hrtmem_mask, hrtmem2_mask, hrtmem3_mask;
static uae_u8 *hrtmon_custom, *hrtmon_ciaa, *hrtmon_ciab, *hrtmon_zeropage;
uae_u32 hrtmem_start, hrtmem2_start, hrtmem3_start, hrtmem_size, hrtmem2_size, hrtmem2_size2, hrtmem3_size;
uae_u32 hrtmem_end, hrtmem2_end;
static int hrtmem_rom;
static int triggered_once;
static void hrtmon_unmap_banks (void);
void check_prefs_changed_carts (int in_memory_reset);
int action_replay_unload (int in_memory_reset);
static int stored_picasso_on = -1;
static void cartridge_enter (void)
{
#ifdef PICASSO96
stored_picasso_on = picasso_on;
picasso_requested_on = 0;
#endif
}
static void cartridge_exit (void)
{
#ifdef PICASSO96
if (stored_picasso_on >= 0)
picasso_requested_on = stored_picasso_on != 0;
stored_picasso_on = -1;
#endif
}
static uae_u32 REGPARAM2 hrtmem3_bget (uaecptr addr)
{
addr -= hrtmem3_start & hrtmem3_mask;
addr &= hrtmem3_mask;
return hrtmemory3[addr];
}
static uae_u32 REGPARAM2 hrtmem3_wget (uaecptr addr)
{
return (hrtmem3_bget (addr) << 8) | hrtmem3_bget (addr + 1);
}
static uae_u32 REGPARAM2 hrtmem3_lget (uaecptr addr)
{
return (hrtmem3_wget (addr) << 16) | hrtmem3_wget (addr + 2);
}
static void REGPARAM2 hrtmem3_lput (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr -= hrtmem3_start & hrtmem3_mask;
addr &= hrtmem3_mask;
m = (uae_u32 *)(hrtmemory3 + addr);
do_put_mem_long (m, l);
}
static void REGPARAM2 hrtmem3_wput (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr -= hrtmem3_start & hrtmem3_mask;
addr &= hrtmem3_mask;
m = (uae_u16 *)(hrtmemory3 + addr);
do_put_mem_word (m, (uae_u16)w);
}
static void REGPARAM2 hrtmem3_bput (uaecptr addr, uae_u32 b)
{
addr -= hrtmem3_start & hrtmem3_mask;
addr &= hrtmem3_mask;
hrtmemory3[addr] = b;
}
static int REGPARAM2 hrtmem3_check (uaecptr addr, uae_u32 size)
{
addr -= hrtmem3_start & hrtmem3_mask;
addr &= hrtmem3_mask;
return (addr + size) <= hrtmem3_size;
}
static uae_u8 *REGPARAM2 hrtmem3_xlate (uaecptr addr)
{
addr -= hrtmem3_start & hrtmem3_mask;
addr &= hrtmem3_mask;
return hrtmemory3 + addr;
}
static uae_u32 REGPARAM2 hrtmem2_bget (uaecptr addr)
{
if (addr == 0xb8007c && cart_type == CART_SUPER4) {
static int cnt = 60;
cnt--;
if (cnt == 0)
uae_reset(0);
}
addr -= hrtmem2_start & hrtmem2_mask;
addr &= hrtmem2_mask;
return hrtmemory2[addr];
}
static uae_u32 REGPARAM2 hrtmem2_wget (uaecptr addr)
{
return (hrtmem2_bget (addr) << 8) | hrtmem2_bget (addr + 1);
}
static uae_u32 REGPARAM2 hrtmem2_lget (uaecptr addr)
{
return (hrtmem2_wget (addr) << 16) | hrtmem2_wget (addr + 2);
}
static void REGPARAM2 hrtmem2_lput (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr -= hrtmem2_start & hrtmem2_mask;
addr &= hrtmem2_mask;
m = (uae_u32 *)(hrtmemory2 + addr);
do_put_mem_long (m, l);
}
static void REGPARAM2 hrtmem2_wput (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr -= hrtmem2_start & hrtmem2_mask;
addr &= hrtmem2_mask;
m = (uae_u16 *)(hrtmemory2 + addr);
do_put_mem_word (m, (uae_u16)w);
}
static void REGPARAM2 hrtmem2_bput (uaecptr addr, uae_u32 b)
{
addr -= hrtmem2_start & hrtmem2_mask;
addr &= hrtmem2_mask;
hrtmemory2[addr] = b;
}
static int REGPARAM2 hrtmem2_check (uaecptr addr, uae_u32 size)
{
addr -= hrtmem2_start & hrtmem2_mask;
addr &= hrtmem2_mask;
return (addr + size) <= hrtmem2_size;
}
static uae_u8 *REGPARAM2 hrtmem2_xlate (uaecptr addr)
{
addr -= hrtmem2_start & hrtmem2_mask;
addr &= hrtmem2_mask;
return hrtmemory2 + addr;
}
static uae_u32 REGPARAM2 hrtmem_lget (uaecptr addr)
{
uae_u32 *m;
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
m = (uae_u32 *)(hrtmemory + addr);
return do_get_mem_long (m);
}
static uae_u32 REGPARAM2 hrtmem_wget (uaecptr addr)
{
uae_u16 *m;
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
m = (uae_u16 *)(hrtmemory + addr);
return do_get_mem_word (m);
}
static uae_u32 REGPARAM2 hrtmem_bget (uaecptr addr)
{
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
return hrtmemory[addr];
}
static void REGPARAM2 hrtmem_lput (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
if (cart_type == CART_AR1200 && addr < 0x80000)
return;
if (hrtmem_rom)
return;
m = (uae_u32 *)(hrtmemory + addr);
do_put_mem_long (m, l);
}
static void REGPARAM2 hrtmem_wput (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
if (cart_type == CART_AR1200 && addr < 0x80000)
return;
if (hrtmem_rom)
return;
m = (uae_u16 *)(hrtmemory + addr);
do_put_mem_word (m, (uae_u16)w);
}
static void REGPARAM2 hrtmem_bput (uaecptr addr, uae_u32 b)
{
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
if (cart_type == CART_AR1200 && addr < 0x80000)
return;
if (hrtmem_rom)
return;
hrtmemory[addr] = b;
}
static int REGPARAM2 hrtmem_check (uaecptr addr, uae_u32 size)
{
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
return (addr + size) <= hrtmem_size;
}
static uae_u8 *REGPARAM2 hrtmem_xlate (uaecptr addr)
{
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
return hrtmemory + addr;
}
static addrbank hrtmem_bank = {
hrtmem_lget, hrtmem_wget, hrtmem_bget,
hrtmem_lput, hrtmem_wput, hrtmem_bput,
hrtmem_xlate, hrtmem_check, NULL, L"Cartridge Bank",
hrtmem_lget, hrtmem_wget, ABFLAG_RAM
};
static addrbank hrtmem2_bank = {
hrtmem2_lget, hrtmem2_wget, hrtmem2_bget,
hrtmem2_lput, hrtmem2_wput, hrtmem2_bput,
hrtmem2_xlate, hrtmem2_check, NULL, L"Cartridge Bank 2",
hrtmem2_lget, hrtmem2_wget, ABFLAG_RAM
};
static addrbank hrtmem3_bank = {
hrtmem3_lget, hrtmem3_wget, hrtmem3_bget,
hrtmem3_lput, hrtmem3_wput, hrtmem3_bput,
hrtmem3_xlate, hrtmem3_check, NULL, L"Cartridge Bank 3",
hrtmem3_lget, hrtmem3_wget, ABFLAG_RAM
};
static void copyfromamiga (uae_u8 *dst, uaecptr src, int len)
{
while (len--) {
*dst++ = get_byte (src);
src++;
}
}
static void copytoamiga (uaecptr dst, uae_u8 *src, int len)
{
while (len--) {
put_byte (dst, *src++);
dst++;
}
}
int action_replay_flag = ACTION_REPLAY_INACTIVE;
static int ar_rom_file_size;
/* Use this for relocating AR? */
static int ar_rom_location;
/*static*/ int armodel;
static uae_u8 artemp[4]; /* Space to store the 'real' level 7 interrupt */
static uae_u8 armode;
static uae_u32 arrom_start, arrom_size, arrom_mask;
static uae_u32 arram_start, arram_size, arram_mask;
static int ar_wait_pop = 0; /* bool used by AR1 when waiting for the program counter to exit it's ram. */
uaecptr wait_for_pc = 0; /* The program counter that we wait for. */
/* returns true if the Program counter is currently in the AR rom. */
int is_ar_pc_in_rom (void)
{
uaecptr pc = m68k_getpc () & 0xFFFFFF;
return pc >= arrom_start && pc < arrom_start+arrom_size;
}
/* returns true if the Program counter is currently in the AR RAM. */
int is_ar_pc_in_ram (void)
{
uaecptr pc = m68k_getpc () & 0xFFFFFF;
return pc >= arram_start && pc < arram_start+arram_size;
}
/* flag writing == 1 for writing memory, 0 for reading from memory. */
STATIC_INLINE int ar3a (uaecptr addr, uae_u8 b, int writing)
{
uaecptr pc;
/* if (addr < 8) //|| writing ) */
/* { */
/* if (writing) */
/* write_log_debug("ARSTATUS armode:%d, Writing %d to address %p, PC=%p\n", armode, b, addr, m68k_getpc ()); */
/* else */
/* write_log_debug("ARSTATUS armode:%d, Reading %d from address %p, PC=%p\n", armode, armemory_rom[addr], addr, m68k_getpc ()); */
/* } */
if (armodel == 1) /* With AR1. It is always a read. Actually, it is a strobe on exit of the AR.
* but, it is also read during the checksum routine. */
{
if (addr < 2) {
if (is_ar_pc_in_rom()) {
if (ar_wait_pop) {
action_replay_flag = ACTION_REPLAY_WAIT_PC;
/* write_log_debug ("SP %p\n", m68k_areg (regs, 7)); */
/* write_log_debug ("SP+2 %p\n", m68k_areg (regs, 7) + 2); */
/* write_log_debug ("(SP+2) %p\n", longget (m68k_areg (regs, 7) + 2)); */
ar_wait_pop = 0;
/* We get (SP+2) here, as the first word on the stack is the status register. */
/* We want the following long, which is the return program counter. */
wait_for_pc = longget (m68k_areg (regs, 7) + 2); /* Get (SP+2) */
set_special (SPCFLAG_ACTION_REPLAY);
pc = m68k_getpc ();
/* write_log_debug ("Action Replay marked as ACTION_REPLAY_WAIT_PC, PC=%p\n",pc);*/
}
else
{
uaecptr pc = m68k_getpc ();
/* write_log_debug ("Action Replay marked as IDLE, PC=%p\n",pc);*/
action_replay_flag = ACTION_REPLAY_IDLE;
}
}
}
/* This probably violates the hide_banks thing except ar1 doesn't use that yet .*/
return armemory_rom[addr];
}
#ifdef ACTION_REPLAY_HIDE_CARTRIDGE
if (addr >= 8)
return armemory_rom[addr];
if (action_replay_flag != ACTION_REPLAY_ACTIVE)
return 0;
#endif
if (!writing) /* reading */
{
if (addr == 1 || addr == 3) /* This is necessary because we don't update rom location 0 every time we change armode */
return armode | (regs.irc & ~3);
else if (addr < 4)
return (addr & 1) ? regs.irc : regs.irc >> 8;
else
return armemory_rom[addr];
}
/* else, we are writing */
else if (addr == 1) {
armode = b;
if (armode >= 2) {
if (armode == ARMODE_BREAKPOINT_AR2) {
write_log (L"AR2: exit with breakpoint(s) active\n"); /* Correct for AR2 */
} else if (armode == ARMODE_BREAKPOINT_AR3_RESET_AR2 )
write_log (L"AR3: exit waiting for breakpoint.\n"); /* Correct for AR3 (waiting for breakpoint)*/
else
write_log (L"AR2/3: mode(%d) > 3 this shouldn't happen.\n", armode);
} else
write_log (L"AR: exit with armode(%d)\n", armode);
set_special (SPCFLAG_ACTION_REPLAY);
action_replay_flag = ACTION_REPLAY_HIDE;
} else if (addr == 6) {
copytoamiga (regs.vbr + 0x7c, artemp, 4);
write_log (L"AR: chipmem returned\n");
}
return 0;
}
static void action_replay_chipwrite (void);
void REGPARAM2 chipmem_lput_actionreplay1 (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
if (addr == 0x60 && !is_ar_pc_in_rom())
action_replay_chipwrite ();
m = (uae_u32 *)(chipmemory + addr);
do_put_mem_long (m, l);
}
void REGPARAM2 chipmem_wput_actionreplay1 (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
if (addr == 0x60 && !is_ar_pc_in_rom())
action_replay_chipwrite ();
m = (uae_u16 *)(chipmemory + addr);
do_put_mem_word (m, w);
}
void REGPARAM2 chipmem_bput_actionreplay1 (uaecptr addr, uae_u32 b)
{
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
if (addr >= 0x60 && addr <= 0x63 && !is_ar_pc_in_rom())
action_replay_chipwrite();
chipmemory[addr] = b;
}
void REGPARAM2 chipmem_lput_actionreplay23 (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
m = (uae_u32 *)(chipmemory + addr);
do_put_mem_long (m, l);
if (addr >= 0x40 && addr < 0x200 && action_replay_flag == ACTION_REPLAY_WAITRESET)
action_replay_chipwrite();
}
void REGPARAM2 chipmem_wput_actionreplay23 (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
m = (uae_u16 *)(chipmemory + addr);
do_put_mem_word (m, w);
if (addr >= 0x40 && addr < 0x200 && action_replay_flag == ACTION_REPLAY_WAITRESET)
action_replay_chipwrite();
}
static uae_u32 REGPARAM3 arram_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 arram_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 arram_bget (uaecptr) REGPARAM;
static void REGPARAM3 arram_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 arram_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 arram_bput (uaecptr, uae_u32) REGPARAM;
static int REGPARAM3 arram_check (uaecptr addr, uae_u32 size) REGPARAM;
static uae_u8 *REGPARAM3 arram_xlate (uaecptr addr) REGPARAM;
static uae_u32 REGPARAM3 arrom_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 arrom_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 arrom_bget (uaecptr) REGPARAM;
static void REGPARAM3 arrom_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 arrom_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 arrom_bput (uaecptr, uae_u32) REGPARAM;
static int REGPARAM3 arrom_check (uaecptr addr, uae_u32 size) REGPARAM;
static uae_u8 *REGPARAM3 arrom_xlate (uaecptr addr) REGPARAM;
static void action_replay_unmap_banks (void);
static uae_u32 action_replay_calculate_checksum(void);
static uae_u8* get_checksum_location(void);
static void disable_rom_test(void);
static uae_u32 REGPARAM2 arram_lget (uaecptr addr)
{
uae_u32 *m;
#ifdef JIT
special_mem |= S_READ;
#endif
addr -= arram_start;
addr &= arram_mask;
m = (uae_u32 *)(armemory_ram + addr);
if (strncmp ("T8", (char*)m, 2) == 0)
write_log_debug (L"Reading T8 from addr %08x PC=%p\n", addr, m68k_getpc ());
if (strncmp ("LAME", (char*)m, 4) == 0)
write_log_debug (L"Reading LAME from addr %08x PC=%p\n", addr, m68k_getpc ());
if (strncmp ("RES1", (char*)m, 4) == 0)
write_log_debug (L"Reading RES1 from addr %08x PC=%p\n", addr, m68k_getpc ());
if (strncmp ("ARON", (char*)m, 4) == 0)
write_log_debug (L"Reading ARON from addr %08x PC=%p\n", addr, m68k_getpc ());
if (strncmp ("KILL", (char*)m, 4) == 0)
write_log_debug (L"Reading KILL from addr %08x PC=%p\n", addr, m68k_getpc ());
if (strncmp ("BRON", (char*)m, 4) == 0)
write_log_debug (L"Reading BRON from addr %08x PC=%p\n", addr, m68k_getpc ());
if (strncmp ("PRIN", (char*)m, 4) == 0)
write_log_debug (L"Reading PRIN from addr %08x PC=%p\n", addr, m68k_getpc ());
return do_get_mem_long (m);
}
static uae_u32 REGPARAM2 arram_wget (uaecptr addr)
{
uae_u16 *m;
#ifdef JIT
special_mem |= S_READ;
#endif
addr -= arram_start;
addr &= arram_mask;
m = (uae_u16 *)(armemory_ram + addr);
return do_get_mem_word (m);
}
static uae_u32 REGPARAM2 arram_bget (uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
addr -= arram_start;
addr &= arram_mask;
return armemory_ram[addr];
}
void REGPARAM2 arram_lput (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
#ifdef JIT
special_mem |= S_WRITE;
#endif
addr -= arram_start;
addr &= arram_mask;
m = (uae_u32 *)(armemory_ram + addr);
if (strncmp ("T8", (char*)m, 2) == 0)
write_log_debug (L"Writing T8 to addr %08x PC=%p\n", addr, m68k_getpc ());
if (strncmp ("LAME", (char*)m, 4) == 0)
write_log_debug (L"Writing LAME to addr %08x PC=%p\n", addr, m68k_getpc ());
if (strncmp ("RES1", (char*)m, 4) == 0)
write_log_debug (L"Writing RES1 to addr %08x PC=%p\n", addr, m68k_getpc ());
if (strncmp ("ARON", (char*)m, 4) == 0)
write_log_debug (L"Writing ARON to addr %08x PC=%p\n", addr, m68k_getpc ());
if (strncmp ("KILL", (char*)m, 4) == 0)
write_log_debug (L"Writing KILL to addr %08x PC=%p\n", addr, m68k_getpc ());
if (strncmp ("BRON", (char*)m, 4) == 0)
write_log_debug (L"Writing BRON to addr %08x PC=%p\n", addr, m68k_getpc ());
if (strncmp ("PRIN", (char*)m, 4) == 0)
write_log_debug (L"Writing PRIN to addr %08x PC=%p\n", addr, m68k_getpc ());
do_put_mem_long (m, l);
}
void REGPARAM2 arram_wput (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
#ifdef JIT
special_mem |= S_WRITE;
#endif
addr -= arram_start;
addr &= arram_mask;
m = (uae_u16 *)(armemory_ram + addr);
do_put_mem_word (m, w);
}
void REGPARAM2 arram_bput (uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
addr -= arram_start;
addr &= arram_mask;
armemory_ram[addr] = b;
}
static int REGPARAM2 arram_check (uaecptr addr, uae_u32 size)
{
addr -= arram_start;
addr &= arram_mask;
return (addr + size) <= arram_size;
}
static uae_u8 *REGPARAM2 arram_xlate (uaecptr addr)
{
addr -= arram_start;
addr &= arram_mask;
return armemory_ram + addr;
}
static uae_u32 REGPARAM2 arrom_lget (uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
addr -= arrom_start;
addr &= arrom_mask;
return (ar3a (addr, 0, 0) << 24) | (ar3a (addr + 1, 0, 0) << 16) | (ar3a (addr + 2, 0, 0) << 8) | ar3a (addr + 3, 0, 0);
}
static uae_u32 REGPARAM2 arrom_wget (uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
addr -= arrom_start;
addr &= arrom_mask;
return (ar3a (addr, 0, 0) << 8) | ar3a (addr + 1, 0, 0);
}
static uae_u32 REGPARAM2 arrom_bget (uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
addr -= arrom_start;
addr &= arrom_mask;
return ar3a (addr, 0, 0);
}
static void REGPARAM2 arrom_lput (uaecptr addr, uae_u32 l)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
addr -= arrom_start;
addr &= arrom_mask;
ar3a (addr + 0,(uae_u8)(l >> 24), 1);
ar3a (addr + 1,(uae_u8)(l >> 16), 1);
ar3a (addr + 2,(uae_u8)(l >> 8), 1);
ar3a (addr + 3,(uae_u8)(l >> 0), 1);
}
static void REGPARAM2 arrom_wput (uaecptr addr, uae_u32 w)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
addr -= arrom_start;
addr &= arrom_mask;
ar3a (addr + 0,(uae_u8)(w >> 8), 1);
ar3a (addr + 1,(uae_u8)(w >> 0), 1);
}
static void REGPARAM2 arrom_bput (uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
addr -= arrom_start;
addr &= arrom_mask;
ar3a (addr, b, 1);
}
static int REGPARAM2 arrom_check (uaecptr addr, uae_u32 size)
{
addr -= arrom_start;
addr &= arrom_mask;
return (addr + size) <= arrom_size;
}
static uae_u8 *REGPARAM2 arrom_xlate (uaecptr addr)
{
addr -= arrom_start;
addr &= arrom_mask;
return armemory_rom + addr;
}
static addrbank arrom_bank = {
arrom_lget, arrom_wget, arrom_bget,
arrom_lput, arrom_wput, arrom_bput,
arrom_xlate, arrom_check, NULL, L"Action Replay ROM",
arrom_lget, arrom_wget, ABFLAG_ROM
};
static addrbank arram_bank = {
arram_lget, arram_wget, arram_bget,
arram_lput, arram_wput, arram_bput,
arram_xlate, arram_check, NULL, L"Action Replay RAM",
arram_lget, arram_wget, ABFLAG_RAM
};
static void action_replay_unmap_banks (void)
{
if(!armemory_rom)
return;
if (armodel == 1) {
action_replay_map_banks ();
return;
}
map_banks (&dummy_bank, arrom_start >> 16 , arrom_size >> 16, 0);
map_banks (&dummy_bank, arram_start >> 16 , arram_size >> 16, 0);
}
static void action_replay_map_banks (void)
{
if(!armemory_rom)
return;
map_banks (&arrom_bank, arrom_start >> 16, arrom_size >> 16, 0);
map_banks (&arram_bank, arram_start >> 16, arram_size >> 16, 0);
}
static void hide_cart (int hide)
{
#ifdef ACTION_REPLAY_HIDE_CARTRIDGE
if(hide) {
action_replay_unmap_banks ();
} else {
action_replay_map_banks ();
}
#endif
}
/* Cartridge activates itself by overlaying its rom
* over chip-ram and then issuing IRQ 7
*
* I just copy IRQ vector 7 from ROM to chip RAM
* instead of fully emulating cartridge's behaviour.
*/
static void action_replay_go (void)
{
cartridge_enter();
hide_cart (0);
memcpy (armemory_ram + 0xf000, ar_custom, 2 * 256);
action_replay_flag = ACTION_REPLAY_ACTIVE;
set_special (SPCFLAG_ACTION_REPLAY);
copyfromamiga (artemp, regs.vbr + 0x7c, 4);
copytoamiga (regs.vbr + 0x7c, armemory_rom + 0x7c, 4);
NMI ();
}
static void action_replay_go1 (int irq)
{
cartridge_enter();
hide_cart (0);
action_replay_flag = ACTION_REPLAY_ACTIVE;
memcpy (armemory_ram + 0xf000, ar_custom, 2 * 256);
NMI ();
}
typedef struct {
uae_u8 dummy[4+4];
uae_u8 jmps[3*4];
uae_u32 mon_size;
uae_u8 col0h, col0l, col1h, col1l;
uae_u8 right;
uae_u8 keyboard;
uae_u8 key;
uae_u8 ide;
uae_u8 a1200;
uae_u8 aga;
uae_u8 insert;
uae_u8 delay;
uae_u8 lview;
uae_u8 cd32;
uae_u8 screenmode;
uae_u8 novbr;
uae_u8 entered;
uae_u8 hexmode;
uae_u16 error_sr;
uae_u32 error_pc;
uae_u16 error_status;
uae_u8 newid[6];
uae_u16 mon_version;
uae_u16 mon_revision;
uae_u32 whd_base;
uae_u16 whd_version;
uae_u16 whd_revision;
uae_u32 max_chip;
uae_u32 whd_expstrt;
uae_u32 whd_expstop;
} HRTCFG;
static void hrtmon_go (void)
{
uaecptr old;
int i;
triggered_once = 1;
cartridge_enter();
hrtmon_flag = ACTION_REPLAY_ACTIVE;
set_special (SPCFLAG_ACTION_REPLAY);
if (hrtmon_zeropage)
memcpy (hrtmon_zeropage, chipmemory, 1024);
if (hrtmon_custom)
memcpy (hrtmon_custom, ar_custom, 2 * 256);
for (i = 0; i < 16; i++) {
if (hrtmon_ciaa)
hrtmon_ciaa[i * hrtmon_ciadiv + 1] = ar_ciaa[i];
if (hrtmon_ciab)
hrtmon_ciab[i * hrtmon_ciadiv + 0] = ar_ciab[i];
}
if (cart_type == CART_AR1200) {
old = get_long ((uaecptr)(regs.vbr + 0x8));
put_word (hrtmem_start + 0xc0000, 4);
put_long ((uaecptr)(regs.vbr + 8), get_long (hrtmem_start + 8));
Exception (2, 0);