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custom.cpp
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custom.cpp
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/*
* UAE - The Un*x Amiga Emulator
*
* Custom chip emulation
*
* Copyright 1995-2002 Bernd Schmidt
* Copyright 1995 Alessandro Bissacco
* Copyright 2000-2010 Toni Wilen
*/
#include "sysconfig.h"
#include "sysdeps.h"
#include <ctype.h>
#include <assert.h>
#include "options.h"
#include "uae.h"
#include "gensound.h"
#include "audio.h"
#include "sounddep/sound.h"
#include "events.h"
#include "memory.h"
#include "custom.h"
#include "newcpu.h"
#include "cia.h"
#include "disk.h"
#include "blitter.h"
#include "xwin.h"
#include "inputdevice.h"
#include "keybuf.h"
#include "serial.h"
#include "autoconf.h"
#include "traps.h"
#include "gui.h"
#include "picasso96.h"
#include "drawing.h"
#include "savestate.h"
#include "ar.h"
#ifdef AVIOUTPUT
#include "avioutput.h"
#endif
#include "debug.h"
#include "akiko.h"
#include "cdtv.h"
#if defined(ENFORCER)
#include "enforcer.h"
#endif
#include "gayle.h"
#include "gfxfilter.h"
#include "a2091.h"
#include "a2065.h"
#include "ncr_scsi.h"
#include "blkdev.h"
#include "sampler.h"
#define CUSTOM_DEBUG 0
#define SPRITE_DEBUG 0
#define SPRITE_DEBUG_MINY 0x0
#define SPRITE_DEBUG_MAXY 0x100
#define SPR0_HPOS 0x15
#define MAX_SPRITES 8
#define SPRITE_COLLISIONS
#define SPEEDUP
#define AUTOSCALE_SPRITES 1
#define SPRBORDER 0
STATIC_INLINE bool nocustom (void)
{
if (picasso_on && currprefs.picasso96_nocustom)
return 1;
return 0;
}
void uae_abort (const TCHAR *format,...)
{
static int nomore;
va_list parms;
TCHAR buffer[1000];
va_start (parms, format);
_vsntprintf (buffer, sizeof (buffer) - 1, format, parms );
va_end (parms);
if (nomore) {
write_log (L"%s\n", buffer);
return;
}
gui_message (buffer);
nomore = 1;
}
#if 0
void customhack_put (struct customhack *ch, uae_u16 v, int hpos)
{
ch->v = v;
ch->vpos = vpos;
ch->hpos = hpos;
}
uae_u16 customhack_get (struct customhack *ch, int hpos)
{
if (ch->vpos == vpos && ch->hpos == hpos) {
ch->vpos = -1;
return 0xffff;
}
return ch->v;
}
#endif
uae_u16 last_custom_value1;
static unsigned int n_consecutive_skipped = 0;
static unsigned int total_skipped = 0;
STATIC_INLINE void sync_copper (int hpos);
/* Events */
unsigned long int event_cycles, nextevent, is_lastline, currcycle;
long cycles_to_next_event;
long max_cycles_to_next_event;
long cycles_to_hsync_event;
static int rpt_did_reset;
struct ev eventtab[ev_max];
struct ev2 eventtab2[ev2_max];
volatile frame_time_t vsynctime, vsyncmintime;
int vpos;
static int vpos_count, vpos_count_prev;
static int lof_store; // real bit in custom registers
static int lof_current; // what display device thinks
static int lol;
static int next_lineno, prev_lineno;
static enum nln_how nextline_how;
static int lof_changed = 0;
static int scandoubled_line;
/* Stupid genlock-detection prevention hack.
* We should stop calling vsync_handler() and
* hstop_handler() completely but it is not
* worth the trouble..
*/
static int vpos_previous, hpos_previous;
static int vpos_lpen, hpos_lpen, lightpen_triggered;
int lightpen_x, lightpen_y, lightpen_cx, lightpen_cy;
static uae_u32 sprtaba[256],sprtabb[256];
static uae_u32 sprite_ab_merge[256];
/* Tables for collision detection. */
static uae_u32 sprclx[16], clxmask[16];
/* AGA T genlock bit in color registers */
static uae_u8 color_regs_aga_genlock[256];
/*
* Hardware registers of all sorts.
*/
static int REGPARAM3 custom_wput_1 (int, uaecptr, uae_u32, int) REGPARAM;
static uae_u16 cregs[256];
uae_u16 intena, intreq;
uae_u16 dmacon;
uae_u16 adkcon; /* used by audio code */
static uae_u32 cop1lc, cop2lc, copcon;
int maxhpos = MAXHPOS_PAL;
int maxhpos_short = MAXHPOS_PAL;
int maxvpos = MAXVPOS_PAL;
int maxvpos_nom = MAXVPOS_PAL; // nominal value (same as maxvpos but "faked" maxvpos in fake 60hz modes)
int hsyncstartpos;
static int maxvpos_total = 511;
int minfirstline = VBLANK_ENDLINE_PAL;
int equ_vblank_endline = EQU_ENDLINE_PAL;
int vblank_hz = VBLANK_HZ_PAL, fake_vblank_hz, vblank_skip, doublescan;
frame_time_t syncbase;
static int fmode;
uae_u16 beamcon0, new_beamcon0;
uae_u16 vtotal = MAXVPOS_PAL, htotal = MAXHPOS_PAL;
static int maxvpos_stored, maxhpos_stored, vblank_hz_stored;
static uae_u16 hsstop, hbstrt, hbstop, vsstop, vbstrt, vbstop, hsstrt, vsstrt, hcenter;
static int ciavsyncmode;
static int diw_hstrt, diw_hstop;
static int diw_hcounter;
#define HSYNCTIME (maxhpos * CYCLE_UNIT);
/* This is but an educated guess. It seems to be correct, but this stuff
* isn't documented well. */
struct sprite {
uaecptr pt;
int xpos;
int vstart;
int vstop;
int dblscan; /* AGA SSCAN2 */
int armed;
int dmastate;
int dmacycle;
int ptxhpos;
};
static struct sprite spr[MAX_SPRITES];
static int plfstrt_sprite;
uaecptr sprite_0;
int sprite_0_width, sprite_0_height, sprite_0_doubled;
uae_u32 sprite_0_colors[4];
static uae_u8 magic_sprite_mask = 0xff;
static int sprite_vblank_endline = VBLANK_SPRITE_PAL;
static unsigned int sprctl[MAX_SPRITES], sprpos[MAX_SPRITES];
#ifdef AGA
static uae_u16 sprdata[MAX_SPRITES][4], sprdatb[MAX_SPRITES][4];
#else
static uae_u16 sprdata[MAX_SPRITES][1], sprdatb[MAX_SPRITES][1];
#endif
static int sprite_last_drawn_at[MAX_SPRITES];
static int last_sprite_point, nr_armed;
static int sprite_width, sprres;
int sprite_buffer_res;
#ifdef CPUEMU_12
uae_u8 cycle_line[256];
#endif
static uae_u16 bplxdat[8];
static int bpl1dat_written, bpl1dat_early;
static uae_s16 bpl1mod, bpl2mod;
static uaecptr prevbpl[2][MAXVPOS][8];
static uaecptr bplpt[8], bplptx[8];
/*static int blitcount[256]; blitter debug */
static struct color_entry current_colors;
static unsigned int bplcon0, bplcon1, bplcon2, bplcon3, bplcon4;
static unsigned int bplcon0d, bplcon0dd, bplcon0_res, bplcon0_planes, bplcon0_planes_limit;
static unsigned int diwstrt, diwstop, diwhigh;
static int diwhigh_written;
static unsigned int ddfstrt, ddfstop, ddfstrt_old_hpos;
static int ddf_change, badmode, diw_change;
static int bplcon1_hpos;
/* The display and data fetch windows */
enum diw_states
{
DIW_waiting_start, DIW_waiting_stop
};
static int plffirstline, plflastline;
int plffirstline_total, plflastline_total;
static int autoscale_bordercolors;
static int plfstrt_start, plfstrt, plfstop;
static int sprite_minx, sprite_maxx;
static int first_bpl_vpos;
static int last_ddf_pix_hpos;
static int last_decide_line_hpos;
static int last_fetch_hpos, last_sprite_hpos;
static int diwfirstword, diwlastword;
static int plfleft_real;
static int last_hdiw;
static enum diw_states diwstate, hdiwstate, ddfstate;
int first_planes_vpos, last_planes_vpos;
int diwfirstword_total, diwlastword_total;
int ddffirstword_total, ddflastword_total;
int firstword_bplcon1;
static int last_copper_hpos;
static int copper_access;
/* Sprite collisions */
static unsigned int clxdat, clxcon, clxcon2, clxcon_bpl_enable, clxcon_bpl_match;
enum copper_states {
COP_stop,
COP_read1,
COP_read2,
COP_bltwait,
COP_wait_in2,
COP_skip_in2,
COP_wait1,
COP_wait,
COP_skip1,
COP_strobe_delay1,
COP_strobe_delay2,
COP_strobe_extra, // just to skip current cycle when CPU wrote to COPJMP
COP_start_delay
};
struct copper {
/* The current instruction words. */
unsigned int i1, i2;
unsigned int saved_i1, saved_i2;
enum copper_states state, state_prev;
/* Instruction pointer. */
uaecptr ip, saved_ip;
int hpos, vpos;
unsigned int ignore_next;
int vcmp, hcmp;
int strobe; /* COPJMP1 / COPJMP2 accessed */
int last_write, last_write_hpos;
int moveaddr, movedata, movedelay;
};
static struct copper cop_state;
static int copper_enabled_thisline;
static int cop_min_waittime;
/*
* Statistics
*/
unsigned long int frametime = 0, lastframetime = 0, timeframes = 0;
unsigned long hsync_counter = 0, vsync_counter = 0, ciavsync_counter = 0;
unsigned long int idletime;
int bogusframe;
/* Recording of custom chip register changes. */
static int current_change_set;
static struct sprite_entry sprite_entries[2][MAX_SPR_PIXELS / 16];
static struct color_change color_changes[2][MAX_REG_CHANGE];
struct decision line_decisions[2 * (MAXVPOS + 2) + 1];
static struct draw_info line_drawinfo[2][2 * (MAXVPOS + 2) + 1];
#define COLOR_TABLE_SIZE (MAXVPOS + 2) * 2
static struct color_entry color_tables[2][COLOR_TABLE_SIZE];
static int next_sprite_entry = 0;
static int prev_next_sprite_entry;
static int next_sprite_forced = 1;
struct sprite_entry *curr_sprite_entries, *prev_sprite_entries;
struct color_change *curr_color_changes, *prev_color_changes;
struct draw_info *curr_drawinfo, *prev_drawinfo;
struct color_entry *curr_color_tables, *prev_color_tables;
static int next_color_change;
static int next_color_entry, remembered_color_entry;
static int color_src_match, color_dest_match, color_compare_result;
static uae_u32 thisline_changed;
#ifdef SMART_UPDATE
#define MARK_LINE_CHANGED do { thisline_changed = 1; } while (0)
#else
#define MARK_LINE_CHANGED do { ; } while (0)
#endif
static struct decision thisline_decision;
static int fetch_cycle, fetch_modulo_cycle;
enum plfstate
{
plf_idle,
plf_start,
plf_active,
plf_passed_stop,
plf_passed_stop2,
plf_end
} plf_state;
enum fetchstate {
fetch_not_started,
fetch_started,
fetch_was_plane0
} fetch_state;
/*
* helper functions
*/
STATIC_INLINE int ecsshres(void)
{
return bplcon0_res == RES_SUPERHIRES && (currprefs.chipset_mask & CSMASK_ECS_DENISE) && !(currprefs.chipset_mask & CSMASK_AGA);
}
STATIC_INLINE int nodraw (void)
{
return !currprefs.cpu_cycle_exact && framecnt != 0;
}
static int doflickerfix (void)
{
return currprefs.gfx_vresolution && doublescan < 0 && vpos < MAXVPOS;
}
uae_u32 get_copper_address (int copno)
{
switch (copno) {
case 1: return cop1lc;
case 2: return cop2lc;
case -1: return cop_state.ip;
default: return 0;
}
}
int rpt_available = 0;
void reset_frame_rate_hack (void)
{
if (currprefs.m68k_speed != -1)
return;
if (! rpt_available) {
currprefs.m68k_speed = 0;
return;
}
rpt_did_reset = 1;
is_lastline = 0;
vsyncmintime = read_processor_time () + vsynctime;
write_log (L"Resetting frame rate hack\n");
}
STATIC_INLINE void setclr (uae_u16 *p, uae_u16 val)
{
if (val & 0x8000)
*p |= val & 0x7FFF;
else
*p &= ~val;
}
STATIC_INLINE void alloc_cycle (int hpos, int type)
{
#ifdef CPUEMU_12
#if 0
if (cycle_line[hpos])
write_log (L"hpos=%d, old=%d, new=%d\n", hpos, cycle_line[hpos], type);
if ((type == CYCLE_CPU || type == CYCLE_COPPER) && (hpos & 1))
write_log (L"odd %d cycle %d\n", hpos);
if (!(hpos & 1) && (type == CYCLE_SPRITE || type == CYCLE_REFRESH || type == CYCLE_MISC))
write_log (L"even %d cycle %d\n", type, hpos);
#endif
cycle_line[hpos] = type;
#endif
}
STATIC_INLINE void alloc_cycle_maybe (int hpos, int type)
{
if (cycle_line[hpos] == 0)
alloc_cycle (hpos, type);
}
void alloc_cycle_ext(int hpos, int type)
{
alloc_cycle (hpos, type);
}
static void hsyncdelay (void)
{
#if 0
static int prevhpos;
while (current_hpos () == prevhpos)
do_cycles(CYCLE_UNIT);
prevhpos = current_hpos();
#endif
}
static void update_mirrors (void)
{
aga_mode = (currprefs.chipset_mask & CSMASK_AGA) ? 1 : 0;
direct_rgb = aga_mode;
}
STATIC_INLINE uae_u8 *pfield_xlateptr (uaecptr plpt, int bytecount)
{
if (!chipmem_check_indirect (plpt, bytecount)) {
static int count = 0;
if (!count)
count++, write_log (L"Warning: Bad playfield pointer\n");
return NULL;
}
return chipmem_xlate_indirect (plpt);
}
STATIC_INLINE void docols (struct color_entry *colentry)
{
int i;
#ifdef AGA
if (currprefs.chipset_mask & CSMASK_AGA) {
for (i = 0; i < 256; i++) {
int v = color_reg_get (colentry, i);
if (v < 0 || v > 16777215)
continue;
colentry->acolors[i] = getxcolor (v);
}
} else {
#endif
for (i = 0; i < 32; i++) {
int v = color_reg_get (colentry, i);
if (v < 0 || v > 4095)
continue;
colentry->acolors[i] = getxcolor (v);
}
#ifdef AGA
}
#endif
}
extern struct color_entry colors_for_drawing;
void notice_new_xcolors (void)
{
int i;
update_mirrors ();
docols (¤t_colors);
docols (&colors_for_drawing);
for (i = 0; i < (MAXVPOS + 1) * 2; i++) {
docols (color_tables[0] + i);
docols (color_tables[1] + i);
}
}
static void do_sprites (int currhp);
static void remember_ctable (void)
{
if (remembered_color_entry == -1) {
/* The colors changed since we last recorded a color map. Record a
* new one. */
color_reg_cpy (curr_color_tables + next_color_entry, ¤t_colors);
remembered_color_entry = next_color_entry++;
}
thisline_decision.ctable = remembered_color_entry;
if (color_src_match == -1 || color_dest_match != remembered_color_entry
|| line_decisions[next_lineno].ctable != color_src_match)
{
/* The remembered comparison didn't help us - need to compare again. */
int oldctable = line_decisions[next_lineno].ctable;
int changed = 0;
if (oldctable == -1) {
changed = 1;
color_src_match = color_dest_match = -1;
} else {
color_compare_result = color_reg_cmp (&prev_color_tables[oldctable], ¤t_colors) != 0;
if (color_compare_result)
changed = 1;
color_src_match = oldctable;
color_dest_match = remembered_color_entry;
}
thisline_changed |= changed;
} else {
/* We know the result of the comparison */
if (color_compare_result)
thisline_changed = 1;
}
}
static void remember_ctable_for_border (void)
{
remember_ctable ();
}
/* Called to determine the state of the horizontal display window state
* machine at the current position. It might have changed since we last
* checked. */
static void decide_diw (int hpos)
{
/* Last hpos = hpos + 0.5, eg. normal PAL end hpos is 227.5 * 2 = 455
OCS Denise: 9 bit hdiw counter does not reset during lines 0 to 9
(PAL) or lines 0 to 10 (NTSC). A1000 PAL: 1 to 9, NTSC: 1 to 10.
ECS Denise and AGA: no above "features"
*/
int hdiw = hpos >= maxhpos ? maxhpos * 2 + 1 : hpos * 2 + 2;
if (!(currprefs.chipset_mask & CSMASK_ECS_DENISE) && vpos <= equ_vblank_endline) {
hdiw = diw_hcounter;
hdiw &= 511;
}
for (;;) {
int lhdiw = hdiw;
if (last_hdiw > lhdiw)
lhdiw = 512;
if (lhdiw >= diw_hstrt && last_hdiw < diw_hstrt && hdiwstate == DIW_waiting_start) {
if (thisline_decision.diwfirstword == -1)
thisline_decision.diwfirstword = diwfirstword < 0 ? 0 : diwfirstword;
hdiwstate = DIW_waiting_stop;
}
if (lhdiw >= diw_hstop && last_hdiw < diw_hstop && hdiwstate == DIW_waiting_stop) {
if (thisline_decision.diwlastword == -1)
thisline_decision.diwlastword = diwlastword < 0 ? 0 : diwlastword;
hdiwstate = DIW_waiting_start;
}
if (lhdiw != 512)
break;
last_hdiw = 0 - 1;
}
last_hdiw = hdiw;
}
static int fetchmode;
static int real_bitplane_number[3][3][9];
/* Disable bitplane DMA if planes > available DMA slots. This is needed
e.g. by the Sanity WOC demo (at the "Party Effect"). */
STATIC_INLINE int GET_PLANES_LIMIT (uae_u16 bc0)
{
int res = GET_RES_AGNUS (bc0);
int planes = GET_PLANES (bc0);
return real_bitplane_number[fetchmode][res][planes];
}
/* The HRM says 0xD8, but that can't work... */
#define HARD_DDF_STOP 0xd4
#define HARD_DDF_START 0x18
static void add_modulos (void)
{
int m1, m2;
if (fmode & 0x4000) {
if (((diwstrt >> 8) ^ vpos) & 1)
m1 = m2 = bpl2mod;
else
m1 = m2 = bpl1mod;
} else {
m1 = bpl1mod;
m2 = bpl2mod;
}
switch (bplcon0_planes_limit) {
#ifdef AGA
case 8: bplpt[7] += m2; bplptx[7] += m2;
case 7: bplpt[6] += m1; bplptx[6] += m1;
#endif
case 6: bplpt[5] += m2; bplptx[5] += m2;
case 5: bplpt[4] += m1; bplptx[4] += m1;
case 4: bplpt[3] += m2; bplptx[3] += m2;
case 3: bplpt[2] += m1; bplptx[2] += m1;
case 2: bplpt[1] += m2; bplptx[1] += m2;
case 1: bplpt[0] += m1; bplptx[0] += m1;
}
}
static void finish_playfield_line (void)
{
/* The latter condition might be able to happen in interlaced frames. */
if (vpos >= minfirstline && (thisframe_first_drawn_line == -1 || vpos < thisframe_first_drawn_line))
thisframe_first_drawn_line = vpos;
thisframe_last_drawn_line = vpos;
#ifdef SMART_UPDATE
if (line_decisions[next_lineno].plflinelen != thisline_decision.plflinelen
|| line_decisions[next_lineno].plfleft != thisline_decision.plfleft
|| line_decisions[next_lineno].bplcon0 != thisline_decision.bplcon0
|| line_decisions[next_lineno].bplcon2 != thisline_decision.bplcon2
#ifdef ECS_DENISE
|| line_decisions[next_lineno].bplcon3 != thisline_decision.bplcon3
#endif
#ifdef AGA
|| line_decisions[next_lineno].bplcon4 != thisline_decision.bplcon4
#endif
)
#endif /* SMART_UPDATE */
thisline_changed = 1;
}
/* The fetch unit mainly controls ddf stop. It's the number of cycles that
are contained in an indivisible block during which ddf is active. E.g.
if DDF starts at 0x30, and fetchunit is 8, then possible DDF stops are
0x30 + n * 8. */
static int fetchunit, fetchunit_mask;
/* The delay before fetching the same bitplane again. Can be larger than
the number of bitplanes; in that case there are additional empty cycles
with no data fetch (this happens for high fetchmodes and low
resolutions). */
static int fetchstart, fetchstart_shift, fetchstart_mask;
/* fm_maxplane holds the maximum number of planes possible with the current
fetch mode. This selects the cycle diagram:
8 planes: 73516240
4 planes: 3120
2 planes: 10. */
static int fm_maxplane, fm_maxplane_shift;
/* The corresponding values, by fetchmode and display resolution. */
static const int fetchunits[] = { 8,8,8,0, 16,8,8,0, 32,16,8,0 };
static const int fetchstarts[] = { 3,2,1,0, 4,3,2,0, 5,4,3,0 };
static const int fm_maxplanes[] = { 3,2,1,0, 3,3,2,0, 3,3,3,0 };
static int cycle_diagram_table[3][3][9][32];
static int cycle_diagram_free_cycles[3][3][9];
static int cycle_diagram_total_cycles[3][3][9];
static int *curr_diagram;
static const int cycle_sequences[3 * 8] = { 2,1,2,1,2,1,2,1, 4,2,3,1,4,2,3,1, 8,4,6,2,7,3,5,1 };
static void debug_cycle_diagram (void)
{
int fm, res, planes, cycle, v;
TCHAR aa;
for (fm = 0; fm <= 2; fm++) {
write_log (L"FMODE %d\n=======\n", fm);
for (res = 0; res <= 2; res++) {
for (planes = 0; planes <= 8; planes++) {
write_log (L"%d: ",planes);
for (cycle = 0; cycle < 32; cycle++) {
v=cycle_diagram_table[fm][res][planes][cycle];
if (v==0) aa='-'; else if(v>0) aa='1'; else aa='X';
write_log (L"%c",aa);
}
write_log (L" %d:%d\n",
cycle_diagram_free_cycles[fm][res][planes], cycle_diagram_total_cycles[fm][res][planes]);
}
write_log (L"\n");
}
}
fm=0;
}
static void create_cycle_diagram_table (void)
{
int fm, res, cycle, planes, rplanes, v;
int fetch_start, max_planes, freecycles;
const int *cycle_sequence;
for (fm = 0; fm <= 2; fm++) {
for (res = 0; res <= 2; res++) {
max_planes = fm_maxplanes[fm * 4 + res];
fetch_start = 1 << fetchstarts[fm * 4 + res];
cycle_sequence = &cycle_sequences[(max_planes - 1) * 8];
max_planes = 1 << max_planes;
for (planes = 0; planes <= 8; planes++) {
freecycles = 0;
for (cycle = 0; cycle < 32; cycle++)
cycle_diagram_table[fm][res][planes][cycle] = -1;
if (planes <= max_planes) {
for (cycle = 0; cycle < fetch_start; cycle++) {
if (cycle < max_planes && planes >= cycle_sequence[cycle & 7]) {
v = cycle_sequence[cycle & 7];
} else {
v = 0;
freecycles++;
}
cycle_diagram_table[fm][res][planes][cycle] = v;
}
}
cycle_diagram_free_cycles[fm][res][planes] = freecycles;
cycle_diagram_total_cycles[fm][res][planes] = fetch_start;
rplanes = planes;
if (rplanes > max_planes)
rplanes = 0;
if (rplanes == 7 && fm == 0 && res == 0 && !(currprefs.chipset_mask & CSMASK_AGA))
rplanes = 4;
real_bitplane_number[fm][res][planes] = rplanes;
}
}
}
#if 0
debug_cycle_diagram ();
#endif
}
/* Used by the copper. */
static int estimated_last_fetch_cycle;
static int cycle_diagram_shift;
static void estimate_last_fetch_cycle (int hpos)
{
int fetchunit = fetchunits[fetchmode * 4 + bplcon0_res];
if (plf_state < plf_passed_stop) {
int stop = plfstop < hpos || plfstop > HARD_DDF_STOP ? HARD_DDF_STOP : plfstop;
/* We know that fetching is up-to-date up until hpos, so we can use fetch_cycle. */
int fetch_cycle_at_stop = fetch_cycle + (stop - hpos);
int starting_last_block_at = (fetch_cycle_at_stop + fetchunit - 1) & ~(fetchunit - 1);
estimated_last_fetch_cycle = hpos + (starting_last_block_at - fetch_cycle) + fetchunit;
} else {
int starting_last_block_at = (fetch_cycle + fetchunit - 1) & ~(fetchunit - 1);
if (plf_state == plf_passed_stop2)
starting_last_block_at -= fetchunit;
estimated_last_fetch_cycle = hpos + (starting_last_block_at - fetch_cycle) + fetchunit;
}
}
static uae_u32 outword[MAX_PLANES];
static int out_nbits, out_offs;
static uae_u32 todisplay[MAX_PLANES][4];
static uae_u32 fetched[MAX_PLANES];
#ifdef AGA
static uae_u32 fetched_aga0[MAX_PLANES];
static uae_u32 fetched_aga1[MAX_PLANES];
#endif
/* Expansions from bplcon0/bplcon1. */
static int toscr_res, toscr_nr_planes, toscr_nr_planes2, fetchwidth;
static int toscr_delay1, toscr_delay2;
/* The number of bits left from the last fetched words.
This is an optimization - conceptually, we have to make sure the result is
the same as if toscr is called in each clock cycle. However, to speed this
up, we accumulate display data; this variable keeps track of how much.
Thus, once we do call toscr_nbits (which happens at least every 16 bits),
we can do more work at once. */
static int toscr_nbits;
/* undocumented bitplane delay hardware feature */
static int delayoffset;
STATIC_INLINE void compute_delay_offset (void)
{
delayoffset = (16 << fetchmode) - (((plfstrt - HARD_DDF_START) & fetchstart_mask) << 1);
#if 0
/* maybe we can finally get rid of this stupid table.. */
if (tmp == 4)
delayoffset = 4; // Loons Docs
else if (tmp == 8)
delayoffset = 8;
else if (tmp == 12) // Loons Docs
delayoffset = 4;
else if (tmp == 16) /* Overkill AGA */
delayoffset = 48;
else if (tmp == 24) /* AB 2 */
delayoffset = 8;
else if (tmp == 32)
delayoffset = 32;
else if (tmp == 48) /* Pinball Illusions AGA, ingame */
delayoffset = 16;
else /* what about 40 and 56? */
delayoffset = 0;
//write_log (L"%d:%d ", vpos, delayoffset);
#endif
}
static void record_color_change2 (int hpos, int regno, unsigned long value)
{
int pos = hpos * 2;
if (regno == 0x1000 + 0x10c)
pos++; // BPLCON4 change needs 1 lores pixel delay
curr_color_changes[next_color_change].linepos = pos;
curr_color_changes[next_color_change].regno = regno;
curr_color_changes[next_color_change++].value = value;
curr_color_changes[next_color_change].regno = -1;
}
static int isehb (uae_u16 bplcon0, uae_u16 bplcon2)
{
int bplehb;
if (currprefs.chipset_mask & CSMASK_AGA)
bplehb = (bplcon0 & 0x7010) == 0x6000;
else if (currprefs.chipset_mask & CSMASK_ECS_DENISE)
bplehb = ((bplcon0 & 0xFC00) == 0x6000 || (bplcon0 & 0xFC00) == 0x7000);
else
bplehb = ((bplcon0 & 0xFC00) == 0x6000 || (bplcon0 & 0xFC00) == 0x7000) && !currprefs.cs_denisenoehb;
return bplehb;
}
// OCS/ECS, lores, 7 planes = 4 "real" planes + BPL5DAT and BPL6DAT as static 5th and 6th plane
STATIC_INLINE int isocs7planes (void)
{
return !(currprefs.chipset_mask & CSMASK_AGA) && bplcon0_res == 0 && bplcon0_planes == 7;
}
int is_bitplane_dma (int hpos)
{
if (fetch_state == fetch_not_started || hpos < plfstrt)
return 0;
if ((plf_state == plf_end && hpos >= thisline_decision.plfright)
|| hpos >= estimated_last_fetch_cycle)
return 0;
return curr_diagram[(hpos - cycle_diagram_shift) & fetchstart_mask];
}
STATIC_INLINE int is_bitplane_dma_inline (int hpos)
{
if (fetch_state == fetch_not_started || hpos < plfstrt)
return 0;
if ((plf_state == plf_end && hpos >= thisline_decision.plfright)
|| hpos >= estimated_last_fetch_cycle)
return 0;
return curr_diagram[(hpos - cycle_diagram_shift) & fetchstart_mask];
}
static void update_denise (int hpos)
{
toscr_res = GET_RES_DENISE (bplcon0d);
if (bplcon0dd != bplcon0d) {
record_color_change2 (hpos, 0x100 + 0x1000, bplcon0d);
bplcon0dd = bplcon0d;
}
toscr_nr_planes = GET_PLANES (bplcon0d);
if (isocs7planes ()) {
if (toscr_nr_planes2 < 6)
toscr_nr_planes2 = 6;
} else {
toscr_nr_planes2 = toscr_nr_planes;
}
}
static int bpldmasetuphpos;
static int bpldmasetupphase;
/* set currently active Agnus bitplane DMA sequence */
static void setup_fmodes (int hpos)
{
switch (fmode & 3)
{
case 0:
fetchmode = 0;
break;
case 1:
case 2:
fetchmode = 1;
break;
case 3:
fetchmode = 2;
break;
}
badmode = GET_RES_AGNUS (bplcon0) != GET_RES_DENISE (bplcon0);
bplcon0_res = GET_RES_AGNUS (bplcon0);
bplcon0_planes = GET_PLANES (bplcon0);
bplcon0_planes_limit = GET_PLANES_LIMIT (bplcon0);
fetchunit = fetchunits[fetchmode * 4 + bplcon0_res];
fetchunit_mask = fetchunit - 1;
fetchstart_shift = fetchstarts[fetchmode * 4 + bplcon0_res];
fetchstart = 1 << fetchstart_shift;
fetchstart_mask = fetchstart - 1;
fm_maxplane_shift = fm_maxplanes[fetchmode * 4 + bplcon0_res];
fm_maxplane = 1 << fm_maxplane_shift;
fetch_modulo_cycle = fetchunit - fetchstart;
if (is_bitplane_dma (hpos - 1))
cycle_line[hpos - 1] = 1;
curr_diagram = cycle_diagram_table[fetchmode][bplcon0_res][bplcon0_planes_limit];
estimate_last_fetch_cycle (hpos);
if (bpldmasetuphpos >= 0 && debug_dma)
record_dma_event (DMA_EVENT_BPLFETCHUPDATE, hpos, vpos);
bpldmasetuphpos = -1;
bpldmasetupphase = 0;
ddf_change = vpos;
}
static void BPLCON0_Denise (int hpos, uae_u16 v);
// writing to BPLCON0 adds 4 cycle delay before Agnus bitplane DMA sequence changes
// (Note that Denise sees the change after 1 cycle)
// AGA needs extra cycle in some specific situations (Brian The Lion "dialog") but not
// in all situations (Superstardust weapon panel)
#define BPLCON_AGNUS_DELAY (4 + (bplcon0_planes == 8 ? 1 : 0))
#define BPLCON_DENISE_DELAY 1
static void maybe_setup_fmodes (int hpos)
{
switch (bpldmasetupphase)
{
case 0:
BPLCON0_Denise (hpos, bplcon0);
bpldmasetupphase++;
bpldmasetuphpos += BPLCON_AGNUS_DELAY - BPLCON_DENISE_DELAY;
break;
case 1:
setup_fmodes (hpos);
break;
}
}
STATIC_INLINE void maybe_check (int hpos)
{
if (bpldmasetuphpos > 0 && hpos >= bpldmasetuphpos)
maybe_setup_fmodes (hpos);
}
static void bpldmainitdelay (int hpos)
{
int hposa;
hposa = hpos + BPLCON_AGNUS_DELAY;
ddf_change = vpos;
if (hposa < 0x14) {
BPLCON0_Denise (hpos, bplcon0);
setup_fmodes (hpos);
return;
}
if (bpldmasetuphpos < 0) {
bpldmasetupphase = 0;
bpldmasetuphpos = hpos + BPLCON_DENISE_DELAY;
}
}
/* Expand bplcon0/bplcon1 into the toscr_xxx variables. */
static void compute_toscr_delay_1 (int bplcon1)
{
int delay1 = (bplcon1 & 0x0f) | ((bplcon1 & 0x0c00) >> 6);
int delay2 = ((bplcon1 >> 4) & 0x0f) | (((bplcon1 >> 4) & 0x0c00) >> 6);
int shdelay1 = (bplcon1 >> 12) & 3;
int shdelay2 = (bplcon1 >> 8) & 3;
int delaymask;
int fetchwidth = 16 << fetchmode;