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gencpu.cpp
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gencpu.cpp
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/*
* UAE - The Un*x Amiga Emulator
*
* MC68000 emulation generator
*
* This is a fairly stupid program that generates a lot of case labels that
* can be #included in a switch statement.
* As an alternative, it can generate functions that handle specific
* MC68000 instructions, plus a prototype header file and a function pointer
* array to look up the function for an opcode.
* Error checking is bad, an illegal table68k file will cause the program to
* call abort().
* The generated code is sometimes sub-optimal, an optimizing compiler should
* take care of this.
*
* The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992.
*
* Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt
*/
#include "sysconfig.h"
#include "sysdeps.h"
#include <ctype.h>
#include "readcpu.h"
#define BOOL_TYPE "int"
/* Define the minimal 680x0 where NV flags are not affected by xBCD instructions. */
#define xBCD_KEEPS_NV_FLAGS 4
static FILE *headerfile;
static FILE *stblfile;
static int using_prefetch, using_indirect, using_mmu;
static int using_ce020;
static int using_exception_3;
static int using_ce;
static int cpu_level;
static int count_read, count_write, count_cycles, count_ncycles;
static int count_read_ea, count_write_ea, count_cycles_ea;
static int optimized_flags;
#define GF_APDI 1
#define GF_AD8R 2
#define GF_PC8R 4
#define GF_AA 7
#define GF_NOREFILL 8
#define GF_PREFETCH 16
#define GF_FC 32
#define GF_MOVE 64
/* For the current opcode, the next lower level that will have different code.
* Initialized to -1 for each opcode. If it remains unchanged, indicates we
* are done with that opcode. */
static int next_cpu_level;
static int *opcode_map;
static int *opcode_next_clev;
static int *opcode_last_postfix;
static unsigned long *counts;
static int generate_stbl;
static int fixupcnt;
#define GENA_GETV_NO_FETCH 0
#define GENA_GETV_FETCH 1
#define GENA_GETV_FETCH_ALIGN 2
#define GENA_MOVEM_DO_INC 0
#define GENA_MOVEM_NO_INC 1
#define GENA_MOVEM_MOVE16 2
static void read_counts (void)
{
FILE *file;
unsigned long opcode, count, total;
char name[20];
int nr = 0;
memset (counts, 0, 65536 * sizeof *counts);
count = 0;
file = fopen ("frequent.68k", "r");
if (file) {
fscanf (file, "Total: %lu\n", &total);
while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
opcode_next_clev[nr] = 5;
opcode_last_postfix[nr] = -1;
opcode_map[nr++] = opcode;
counts[opcode] = count;
}
fclose (file);
}
if (nr == nr_cpuop_funcs)
return;
for (opcode = 0; opcode < 0x10000; opcode++) {
if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
&& counts[opcode] == 0)
{
opcode_next_clev[nr] = 5;
opcode_last_postfix[nr] = -1;
opcode_map[nr++] = opcode;
counts[opcode] = count;
}
}
if (nr != nr_cpuop_funcs)
abort ();
}
static char endlabelstr[80];
static int endlabelno = 0;
static int need_endlabel;
static int n_braces, limit_braces;
static int m68k_pc_offset;
static int insn_n_cycles, insn_n_cycles020;
static void fpulimit (void)
{
if (limit_braces)
return;
printf ("\n#ifdef FPUEMU\n");
limit_braces = n_braces;
n_braces = 0;
}
static void cpulimit (void)
{
printf ("#ifndef CPUEMU_68000_ONLY\n");
}
static void returncycles (char *s, int cycles)
{
if (using_ce)
return;
if (using_ce020)
printf ("%sreturn;\n", s);
else
printf ("%sreturn %d * CYCLE_UNIT / 2;\n", s, cycles);
}
static void addcycles_ce020 (int cycles)
{
if (!using_ce020)
return;
if (cycles > 0)
printf ("\tregs.ce020memcycles += %d * cpucycleunit;\n", cycles);
count_cycles += cycles;
}
static void addcycles000 (int cycles)
{
if (!using_ce)
return;
printf ("\tdo_cycles_ce000 (%d);\n", cycles);
count_cycles += cycles;
}
static void addcycles000_2 (char *s, int cycles)
{
if (!using_ce)
return;
printf ("%sdo_cycles_ce000 (%d);\n", s, cycles);
count_cycles += cycles;
}
static void addcycles000_3 (char *s)
{
if (!using_ce)
return;
printf ("%sif (cycles > 0) do_cycles_ce000 (cycles);\n", s);
count_ncycles++;
}
static int isreg (amodes mode)
{
if (mode == Dreg || mode == Areg)
return 1;
return 0;
}
static void start_brace (void)
{
n_braces++;
printf ("{");
}
static void close_brace (void)
{
assert (n_braces > 0);
n_braces--;
printf ("}");
}
static void finish_braces (void)
{
while (n_braces > 0)
close_brace ();
}
static void pop_braces (int to)
{
while (n_braces > to)
close_brace ();
}
static int bit_size (int size)
{
switch (size) {
case sz_byte: return 8;
case sz_word: return 16;
case sz_long: return 32;
default: abort ();
}
return 0;
}
static const char *bit_mask (int size)
{
switch (size) {
case sz_byte: return "0xff";
case sz_word: return "0xffff";
case sz_long: return "0xffffffff";
default: abort ();
}
return 0;
}
static char *srcl, *dstl;
static char *srcw, *dstw;
static char *srcb, *dstb;
static char *ce020_prefetch_long;
static char *ce020_prefetch_word;
static void gen_nextilong (char *type, char *name, int flags)
{
int r = m68k_pc_offset;
m68k_pc_offset += 4;
if (using_ce020) {
printf ("\t%s %s = %s (%d);\n", type, name, ce020_prefetch_long, r);
count_read += 2;
} else if (using_ce) {
printf ("\t%s %s;\n", type, name);
/* we must do this because execution order of (something | something2) is not defined */
if (flags & GF_NOREFILL) {
printf ("\t%s = get_word_ce_prefetch (%d) << 16;\n", name, r + 2);
count_read++;
printf ("\t%s |= regs.irc;\n", name);
} else {
printf ("\t%s = get_word_ce_prefetch (%d) << 16;\n", name, r + 2);
count_read++;
printf ("\t%s |= get_word_ce_prefetch (%d);\n", name, r + 4);
count_read++;
}
} else {
if (using_prefetch) {
if (flags & GF_NOREFILL) {
printf ("\t%s %s;\n", type, name);
printf ("\t%s = get_word_prefetch (%d) << 16;\n", name, r + 2);
count_read++;
printf ("\t%s |= regs.irc;\n", name);
insn_n_cycles += 4;
} else {
printf ("\t%s %s = get_long_prefetch (%d);\n", type, name, r + 2);
count_read++;
count_read++;
insn_n_cycles += 8;
}
} else if (using_indirect) {
insn_n_cycles += 8;
printf ("\t%s %s = get_ilongi (%d);\n", type, name, r);
} else if (using_mmu) {
insn_n_cycles += 8;
printf ("\t%s %s = get_ilong_mmu (%d);\n", type, name, r);
} else {
insn_n_cycles += 8;
printf ("\t%s %s = get_ilong (%d);\n", type, name, r);
}
}
}
static const char *gen_nextiword (int flags)
{
static char buffer[80];
int r = m68k_pc_offset;
m68k_pc_offset += 2;
if (using_ce020) {
sprintf (buffer, "%s (%d)", ce020_prefetch_word, r);
count_read++;
} else if (using_ce) {
if (flags & GF_NOREFILL) {
strcpy (buffer, "regs.irc");
} else {
sprintf (buffer, "get_word_ce_prefetch (%d)", r + 2);
count_read++;
}
} else {
if (using_prefetch) {
if (flags & GF_NOREFILL) {
sprintf (buffer, "regs.irc", r);
} else {
sprintf (buffer, "get_word_prefetch (%d)", r + 2);
count_read++;
insn_n_cycles += 4;
}
} else if (using_indirect) {
sprintf (buffer, "get_iwordi(%d)", r);
insn_n_cycles += 4;
} else if (using_mmu) {
sprintf (buffer, "get_iword_mmu (%d)", r);
insn_n_cycles += 4;
} else {
sprintf (buffer, "get_iword (%d)", r);
insn_n_cycles += 4;
}
}
return buffer;
}
static const char *gen_nextibyte (int flags)
{
static char buffer[80];
int r = m68k_pc_offset;
m68k_pc_offset += 2;
if (using_ce020) {
sprintf (buffer, "(uae_u8)%s (%d)", ce020_prefetch_word, r);
count_read++;
} else if (using_ce) {
if (flags & GF_NOREFILL) {
strcpy (buffer, "(uae_u8)regs.irc");
} else {
sprintf (buffer, "(uae_u8)get_word_ce_prefetch (%d)", r + 2);
count_read++;
}
} else {
insn_n_cycles += 4;
if (using_prefetch) {
if (flags & GF_NOREFILL) {
sprintf (buffer, "(uae_u8)regs.irc", r);
} else {
sprintf (buffer, "(uae_u8)get_word_prefetch (%d)", r + 2);
insn_n_cycles += 4;
count_read++;
}
} else if (using_indirect) {
sprintf (buffer, "get_ibytei (%d)", r);
insn_n_cycles += 4;
} else if (using_mmu) {
sprintf (buffer, "get_ibyte_mmu (%d)", r);
insn_n_cycles += 4;
} else {
sprintf (buffer, "get_ibyte (%d)", r);
insn_n_cycles += 4;
}
}
return buffer;
}
static void irc2ir (void)
{
if (!using_prefetch)
return;
printf ("\tregs.ir = regs.irc;\n");
if (using_ce)
printf ("\tipl_fetch ();\n");
}
static int did_prefetch;
static void fill_prefetch_2 (void)
{
if (!using_prefetch)
return;
if (using_ce)
printf ("\tget_word_ce_prefetch (%d);\n", m68k_pc_offset + 2);
else
printf ("\tget_word_prefetch (%d);\n", m68k_pc_offset + 2);
did_prefetch = 1;
count_read++;
insn_n_cycles += 4;
}
static void fill_prefetch_1 (int o)
{
if (!using_prefetch)
return;
if (using_ce) {
printf ("\tget_word_ce_prefetch (%d);\n", o);
} else {
printf ("\tget_word_prefetch (%d);\n", o);
}
did_prefetch = 1;
count_read++;
insn_n_cycles += 4;
}
static void fill_prefetch_full (void)
{
fill_prefetch_1 (0);
irc2ir ();
fill_prefetch_1 (2);
}
static void fill_prefetch_0 (void)
{
if (!using_prefetch)
return;
if (using_ce)
printf ("\tget_word_ce_prefetch (0);\n");
else
printf ("\tget_word_prefetch (0);\n");
did_prefetch = 1;
count_read++;
insn_n_cycles += 4;
}
static void dummy_prefetch (void)
{
int o = m68k_pc_offset + 2;
if (!using_prefetch)
return;
if (using_ce) {
printf ("\tget_wordi_ce (m68k_getpc () + %d);\n", o);
} else {
printf ("\tget_wordi (m68k_getpc () + %d);\n", o);
}
count_read++;
insn_n_cycles += 4;
}
static void fill_prefetch_next_1 (void)
{
irc2ir ();
fill_prefetch_1 (m68k_pc_offset + 2);
}
static void fill_prefetch_next (void)
{
fill_prefetch_next_1 ();
}
#if 0
static void fill_prefetch_next_delay (int extracycles)
{
if (!using_prefetch)
return;
if (using_ce) {
if (extracycles > 0) {
printf("\t{\n");
fill_prefetch_next ();
printf("\tif (%d > 0) do_cycles(%d * CYCLE_UNIT / 2);\n",
extracycles, extracycles);
printf("\t}\n");
} else {
fill_prefetch_next ();
}
} else {
fill_prefetch_next ();
}
}
#endif
static void fill_prefetch_finish (void)
{
if (did_prefetch || !using_prefetch)
return;
fill_prefetch_1 (m68k_pc_offset);
}
static void setpc (const char *format, ...)
{
va_list parms;
char buffer[1000];
va_start (parms, format);
_vsnprintf (buffer, 1000 - 1, format, parms);
va_end (parms);
if (using_mmu)
printf ("\tm68k_setpc_mmu (%s);\n", buffer);
else
printf ("\tm68k_setpc (%s);\n", buffer);
}
static void incpc (const char *format, ...)
{
va_list parms;
char buffer[1000];
va_start (parms, format);
_vsnprintf (buffer, 1000 - 1, format, parms);
va_end (parms);
if (using_mmu)
printf ("\tm68k_incpci (%s);\n", buffer);
else
printf ("\tm68k_incpc (%s);\n", buffer);
}
static void sync_m68k_pc (void)
{
if (m68k_pc_offset == 0)
return;
incpc ("%d", m68k_pc_offset);
m68k_pc_offset = 0;
}
static void gen_set_fault_pc (void)
{
if (!using_mmu)
return;
sync_m68k_pc ();
printf ("\tregs.fault_pc = m68k_getpci ();\n");
m68k_pc_offset = 0;
}
static void syncmovepc (int getv, int flags)
{
#if 0
if (!(flags & GF_MOVE))
return;
if (getv == 1) {
sync_m68k_pc ();
//fill_prefetch_next ();
}
#endif
}
/* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
* the calling routine handles Apdi and Aipi modes.
* gb-- movem == 2 means the same thing but for a MOVE16 instruction */
/* fixup indicates if we want to fix up adress registers in pre decrement
* or post increment mode now (0) or later (1). A value of 2 will then be
* used to do the actual fix up. This allows to do all memory readings
* before any register is modified, and so to rerun operation without
* side effect in case a bus fault is generated by any memory access.
* XJ - 2006/11/13 */
static void genamode2 (amodes mode, char *reg, wordsizes size, char *name, int getv, int movem, int flags, int fixup)
{
char namea[100];
int m68k_pc_offset_last = m68k_pc_offset;
sprintf (namea, "%sa", name);
start_brace ();
switch (mode) {
case Dreg:
if (movem)
abort ();
if (getv == 1)
switch (size) {
case sz_byte:
#ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
/* This causes the target compiler to generate better code on few systems */
printf ("\tuae_s8 %s = ((uae_u8*)&m68k_dreg (regs, %s))[3];\n", name, reg);
#else
printf ("\tuae_s8 %s = m68k_dreg (regs, %s);\n", name, reg);
#endif
break;
case sz_word:
#ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
printf ("\tuae_s16 %s = ((uae_s16*)&m68k_dreg (regs, %s))[1];\n", name, reg);
#else
printf ("\tuae_s16 %s = m68k_dreg (regs, %s);\n", name, reg);
#endif
break;
case sz_long:
printf ("\tuae_s32 %s = m68k_dreg (regs, %s);\n", name, reg);
break;
default:
abort ();
}
syncmovepc (getv, flags);
return;
case Areg:
if (movem)
abort ();
if (getv == 1)
switch (size) {
case sz_word:
printf ("\tuae_s16 %s = m68k_areg (regs, %s);\n", name, reg);
break;
case sz_long:
printf ("\tuae_s32 %s = m68k_areg (regs, %s);\n", name, reg);
break;
default:
abort ();
}
syncmovepc (getv, flags);
return;
case Aind: // (An)
printf ("\tuaecptr %sa = m68k_areg (regs, %s);\n", name, reg);
break;
case Aipi: // (An)+
printf ("\tuaecptr %sa = m68k_areg (regs, %s);\n", name, reg);
break;
case Apdi: // -(An)
printf ("\tuaecptr %sa;\n", name);
switch (size) {
case sz_byte:
if (movem)
printf ("\t%sa = m68k_areg (regs, %s);\n", name, reg);
else
printf ("\t%sa = m68k_areg (regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
break;
case sz_word:
printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
break;
case sz_long:
printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
break;
default:
abort ();
}
if (!(flags & GF_APDI)) {
addcycles000 (2);
insn_n_cycles += 2;
count_cycles_ea += 2;
}
break;
case Ad16: // (d16,An)
printf ("\tuaecptr %sa = m68k_areg (regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword (flags));
count_read_ea++;
break;
case Ad8r: // (d8,An,Xn)
printf ("\tuaecptr %sa;\n", name);
if (cpu_level > 1) {
if (next_cpu_level < 1)
next_cpu_level = 1;
sync_m68k_pc ();
start_brace ();
/* This would ordinarily be done in gen_nextiword, which we bypass. */
insn_n_cycles += 4;
if (using_ce020 || using_mmu)
printf ("\t%sa = x_get_disp_ea_020 (m68k_areg (regs, %s), x_next_iword ());\n", name, reg);
else
printf ("\t%sa = get_disp_ea_020 (m68k_areg (regs, %s), next_iword ());\n", name, reg);
} else {
if (!(flags & GF_AD8R)) {
addcycles000 (2);
insn_n_cycles += 2;
count_cycles_ea += 2;
}
printf ("\t%sa = get_disp_ea_000 (m68k_areg (regs, %s), %s);\n", name, reg, gen_nextiword (flags));
count_read_ea++;
}
break;
case PC16: // (d16,PC,Xn)
printf ("\tuaecptr %sa = m68k_getpc () + %d;\n", name, m68k_pc_offset);
printf ("\t%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
break;
case PC8r: // (d8,PC,Xn)
printf ("\tuaecptr tmppc;\n");
printf ("\tuaecptr %sa;\n", name);
if (cpu_level > 1) {
if (next_cpu_level < 1)
next_cpu_level = 1;
sync_m68k_pc ();
start_brace ();
/* This would ordinarily be done in gen_nextiword, which we bypass. */
insn_n_cycles += 4;
printf ("\ttmppc = m68k_getpc ();\n");
if (using_ce020 || using_mmu)
printf ("\t%sa = x_get_disp_ea_020 (tmppc, x_next_iword ());\n", name);
else
printf ("\t%sa = get_disp_ea_020 (tmppc, next_iword ());\n", name);
} else {
printf ("\ttmppc = m68k_getpc () + %d;\n", m68k_pc_offset);
if (!(flags & GF_PC8R)) {
addcycles000 (2);
insn_n_cycles += 2;
count_cycles_ea += 2;
}
printf ("\t%sa = get_disp_ea_000 (tmppc, %s);\n", name, gen_nextiword (flags));
}
break;
case absw:
printf ("\tuaecptr %sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
break;
case absl:
gen_nextilong ("uaecptr", namea, flags);
count_read_ea += 2;
break;
case imm:
if (getv != 1)
abort ();
insn_n_cycles020++;
switch (size) {
case sz_byte:
printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
count_read_ea++;
break;
case sz_word:
printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
count_read_ea++;
break;
case sz_long:
gen_nextilong ("uae_s32", name, flags);
count_read_ea += 2;
break;
default:
abort ();
}
syncmovepc (getv, flags);
return;
case imm0:
if (getv != 1)
abort ();
printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
count_read_ea++;
syncmovepc (getv, flags);
return;
case imm1:
if (getv != 1)
abort ();
printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
count_read_ea++;
syncmovepc (getv, flags);
return;
case imm2:
if (getv != 1)
abort ();
gen_nextilong ("uae_s32", name, flags);
count_read_ea += 2;
syncmovepc (getv, flags);
return;
case immi:
if (getv != 1)
abort ();
printf ("\tuae_u32 %s = %s;\n", name, reg);
syncmovepc (getv, flags);
return;
default:
abort ();
}
syncmovepc (getv, flags);
/* We get here for all non-reg non-immediate addressing modes to
* actually fetch the value. */
if ((using_prefetch || using_ce) && using_exception_3 && getv != 0 && size != sz_byte) {
int offset = 0;
if (flags & GF_MOVE) {
offset = m68k_pc_offset;
if (getv == 2)
offset += 2;
} else {
offset = m68k_pc_offset_last;
}
printf ("\tif (%sa & 1) {\n", name);
printf ("\t\texception3 (opcode, m68k_getpc () + %d, %sa);\n",
offset, name);
printf ("\t\tgoto %s;\n", endlabelstr);
printf ("\t}\n");
need_endlabel = 1;
start_brace ();
}
if (flags & GF_PREFETCH)
fill_prefetch_next ();
if (getv == 1) {
start_brace ();
if (using_ce020) {
switch (size) {
case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = %s (%sa);\n", name, srcb, name); count_read++; break;
case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = %s (%sa);\n", name, srcw, name); count_read++; break;
case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = %s (%sa);\n", name, srcl, name); count_read += 2; break;
default: abort ();
}
} else if (using_ce) {
switch (size) {
case sz_byte: printf ("\tuae_s8 %s = get_byte_ce (%sa);\n", name, name); count_read++; break;
case sz_word: printf ("\tuae_s16 %s = get_word_ce (%sa);\n", name, name); count_read++; break;
case sz_long: printf ("\tuae_s32 %s = get_word_ce (%sa) << 16; %s |= get_word_ce (%sa + 2);\n", name, name, name, name); count_read += 2; break;
default: abort ();
}
} else if (using_mmu) {
if (flags & GF_FC) {
switch (size) {
case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = sfc_get_byte (%sa);\n", name, name); break;
case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = sfc_get_word (%sa);\n", name, name); break;
case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = sfc_get_long (%sa);\n", name, name); break;
default: abort ();
}
} else {
switch (size) {
case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = get_byte_mmu (%sa);\n", name, name); break;
case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = get_word_mmu (%sa);\n", name, name); break;
case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = get_long_mmu (%sa);\n", name, name); break;
default: abort ();
}
}
} else {
switch (size) {
case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = get_byte (%sa);\n", name, name); count_read++; break;
case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = get_word (%sa);\n", name, name); count_read++; break;
case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = get_long (%sa);\n", name, name); count_read += 2; break;
default: abort ();
}
}
}
/* We now might have to fix up the register for pre-dec or post-inc
* addressing modes. */
if (!movem)
switch (mode) {
case Aipi:
if (fixup == 1) {
printf ("\tmmufixup[%d].reg = %s;\n", fixupcnt, reg);
printf ("\tmmufixup[%d].value = m68k_areg (regs, %s);\n", fixupcnt, reg);
}
switch (size) {
case sz_byte:
printf ("\tm68k_areg (regs, %s) += areg_byteinc[%s];\n", reg, reg);
break;
case sz_word:
printf ("\tm68k_areg (regs, %s) += 2;\n", reg);
break;
case sz_long:
printf ("\tm68k_areg (regs, %s) += 4;\n", reg);
break;
default:
abort ();
}
break;
case Apdi:
if (fixup == 1) {
printf ("\tmmufixup[%d].reg = %s;\n", fixupcnt, reg);
printf ("\tmmufixup[%d].value = m68k_areg (regs, %s);\n", fixupcnt, reg);
}
printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name);
break;
default:
break;
}
}
static void genamode_fixup (amodes mode, char *reg, wordsizes size, char *name, int getv, int movem, int flags, int fixup)
{
if (fixup != 2) {
genamode2 (mode, reg, size, name, getv, movem, flags, fixup);
} else {
if (!movem) {
switch (mode)
{
case Aipi:
case Apdi:
printf ("\tmmufixup[0].reg = -1;\n", fixupcnt);
break;
}
}
}
}
static void genamode (amodes mode, char *reg, wordsizes size, char *name, int getv, int movem, int flags)
{
genamode2 (mode, reg, size, name, getv, movem, flags, 0);
}
static void genamode_pre (amodes mode, char *reg, wordsizes size, char *name, int getv, int movem, int flags)
{
genamode_fixup (mode, reg, size, name, getv, movem, flags, using_mmu ? 1 : 0);
}
static void genamode_post (amodes mode, char *reg, wordsizes size, char *name, int getv, int movem, int flags)
{
if (using_mmu)
genamode_fixup (mode, reg, size, name, getv, movem, flags, 2);
}
static void genastore_2 (char *from, amodes mode, char *reg, wordsizes size, char *to, int store_dir, int flags)
{
switch (mode) {
case Dreg:
switch (size) {
case sz_byte:
printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
break;
case sz_word:
printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
break;
case sz_long:
printf ("\tm68k_dreg (regs, %s) = (%s);\n", reg, from);
break;
default:
abort ();
}
break;
case Areg:
switch (size) {
case sz_word:
printf ("\tm68k_areg (regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
break;
case sz_long:
printf ("\tm68k_areg (regs, %s) = (%s);\n", reg, from);
break;
default:
abort ();
}
break;
case Aind:
case Aipi:
case Apdi:
case Ad16:
case Ad8r:
case absw:
case absl:
case PC16:
case PC8r:
gen_set_fault_pc ();
if (using_ce020) {
switch (size) {
case sz_byte:
printf ("\t%s (%sa, %s);\n", dstb, to, from);
count_write++;
break;
case sz_word:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
abort ();
printf ("\t%s (%sa, %s);\n", dstw, to, from);
count_write++;
break;
case sz_long:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
abort ();
printf ("\t%s (%sa, %s);\n", dstl, to, from);
count_write += 2;
break;
default:
abort ();
}
} else if (using_ce) {
switch (size) {
case sz_byte:
printf ("\tput_byte_ce (%sa, %s);\n", to, from);
count_write++;
break;
case sz_word:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
abort ();
printf ("\tput_word_ce (%sa, %s);\n", to, from);
count_write++;
break;
case sz_long:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
abort ();
if (store_dir)
printf ("\tput_word_ce (%sa + 2, %s); put_word_ce (%sa, %s >> 16);\n", to, from, to, from);
else
printf ("\tput_word_ce (%sa, %s >> 16); put_word_ce (%sa + 2, %s);\n", to, from, to, from);
count_write += 2;
break;
default:
abort ();
}
} else if (using_mmu) {
switch (size) {
case sz_byte:
insn_n_cycles += 4;
if (flags & GF_FC)
printf ("\tdfc_put_byte (%sa, %s);\n", to, from);
else
printf ("\tput_byte_mmu (%sa, %s);\n", to, from);
break;
case sz_word:
insn_n_cycles += 4;
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
abort ();
if (flags & GF_FC)
printf ("\tdfc_put_word (%sa, %s);\n", to, from);
else
printf ("\tput_word_mmu (%sa, %s);\n", to, from);
break;
case sz_long:
insn_n_cycles += 8;
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
abort ();
if (flags & GF_FC)
printf ("\tdfc_put_long (%sa, %s);\n", to, from);
else
printf ("\tput_long_mmu (%sa, %s);\n", to, from);
break;
default:
abort ();
}
} else {
switch (size) {
case sz_byte:
insn_n_cycles += 4;
printf ("\tput_byte (%sa, %s);\n", to, from);
count_write++;
break;
case sz_word:
insn_n_cycles += 4;
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
abort ();
printf ("\tput_word (%sa, %s);\n", to, from);
count_write++;
break;