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newcpu.cpp
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newcpu.cpp
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/*
* UAE - The Un*x Amiga Emulator
*
* MC68000 emulation
*
* (c) 1995 Bernd Schmidt
*/
#define MOVEC_DEBUG 0
#define MMUOP_DEBUG 2
#define DEBUG_CD32CDTVIO 0
#include "sysconfig.h"
#include "sysdeps.h"
#include "options.h"
#include "events.h"
#include "uae.h"
#include "memory.h"
#include "custom.h"
#include "newcpu.h"
#include "cpummu.h"
#include "cpu_prefetch.h"
#include "autoconf.h"
#include "traps.h"
#include "ersatz.h"
#include "debug.h"
#include "gui.h"
#include "savestate.h"
#include "blitter.h"
#include "ar.h"
#include "gayle.h"
#include "cia.h"
#include "inputdevice.h"
#ifdef JIT
#include "jit/compemu.h"
#include <signal.h>
#else
/* Need to have these somewhere */
static void build_comp (void) {}
bool check_prefs_changed_comp (void) { return false; }
#endif
/* For faster JIT cycles handling */
signed long pissoff = 0;
/* Opcode of faulting instruction */
static uae_u16 last_op_for_exception_3;
/* PC at fault time */
static uaecptr last_addr_for_exception_3;
/* Address that generated the exception */
static uaecptr last_fault_for_exception_3;
/* read (0) or write (1) access */
static int last_writeaccess_for_exception_3;
/* instruction (1) or data (0) access */
static int last_instructionaccess_for_exception_3;
unsigned long irqcycles[15];
int irqdelay[15];
int mmu_enabled, mmu_triggered;
int cpu_cycles;
static int baseclock;
int cpucycleunit;
const int areg_byteinc[] = { 1, 1, 1, 1, 1, 1, 1, 2 };
const int imm8_table[] = { 8, 1, 2, 3, 4, 5, 6, 7 };
int movem_index1[256];
int movem_index2[256];
int movem_next[256];
cpuop_func *cpufunctbl[65536];
struct mmufixup mmufixup[2];
extern uae_u32 get_fpsr (void);
#define COUNT_INSTRS 0
#define MC68060_PCR 0x04300000
#define MC68EC060_PCR 0x04310000
static uae_u64 srp_030, crp_030;
static uae_u32 tt0_030, tt1_030, tc_030;
static uae_u16 mmusr_030;
static struct cache020 caches020[CACHELINES020];
static struct cache030 icaches030[CACHELINES030];
static struct cache030 dcaches030[CACHELINES030];
static struct cache040 caches040[CACHESETS040];
#if COUNT_INSTRS
static unsigned long int instrcount[65536];
static uae_u16 opcodenums[65536];
static int compfn (const void *el1, const void *el2)
{
return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
}
static TCHAR *icountfilename (void)
{
TCHAR *name = getenv ("INSNCOUNT");
if (name)
return name;
return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
}
void dump_counts (void)
{
FILE *f = fopen (icountfilename (), "w");
unsigned long int total;
int i;
write_log (L"Writing instruction count file...\n");
for (i = 0; i < 65536; i++) {
opcodenums[i] = i;
total += instrcount[i];
}
qsort (opcodenums, 65536, sizeof (uae_u16), compfn);
fprintf (f, "Total: %lu\n", total);
for (i=0; i < 65536; i++) {
unsigned long int cnt = instrcount[opcodenums[i]];
struct instr *dp;
struct mnemolookup *lookup;
if (!cnt)
break;
dp = table68k + opcodenums[i];
for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
;
fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
}
fclose (f);
}
#else
void dump_counts (void)
{
}
#endif
uae_u32 (*x_prefetch)(int);
uae_u32 (*x_next_iword)(void);
uae_u32 (*x_next_ilong)(void);
uae_u32 (*x_get_long)(uaecptr);
uae_u32 (*x_get_word)(uaecptr);
uae_u32 (*x_get_byte)(uaecptr);
void (*x_put_long)(uaecptr,uae_u32);
void (*x_put_word)(uaecptr,uae_u32);
void (*x_put_byte)(uaecptr,uae_u32);
// shared memory access functions
static void set_x_funcs (void)
{
if (currprefs.mmu_model) {
x_prefetch = get_iword_mmu;
x_next_iword = next_iword_mmu;
x_next_ilong = next_ilong_mmu;
x_put_long = put_long_mmu;
x_put_word = put_word_mmu;
x_put_byte = put_byte_mmu;
x_get_long = get_long_mmu;
x_get_word = get_word_mmu;
x_get_byte = get_byte_mmu;
} else if (!currprefs.cpu_cycle_exact) {
x_prefetch = get_iword;
x_next_iword = next_iword;
x_next_ilong = next_ilong;
x_put_long = put_long;
x_put_word = put_word;
x_put_byte = put_byte;
x_get_long = get_long;
x_get_word = get_word;
x_get_byte = get_byte;
} else if (currprefs.cpu_model < 68020) {
x_prefetch = NULL;
x_next_iword = NULL;
x_next_ilong = NULL;
x_put_long = put_long_ce;
x_put_word = put_word_ce;
x_put_byte = put_byte_ce;
x_get_long = get_long_ce;
x_get_word = get_word_ce;
x_get_byte = get_byte_ce;
} else if (currprefs.cpu_model == 68020) {
x_prefetch = get_word_ce020_prefetch;
x_next_iword = next_iword_020ce;
x_next_ilong = next_ilong_020ce;
x_put_long = put_long_ce020;
x_put_word = put_word_ce020;
x_put_byte = put_byte_ce020;
x_get_long = get_long_ce020;
x_get_word = get_word_ce020;
x_get_byte = get_byte_ce020;
} else {
x_prefetch = get_word_ce030_prefetch;
x_next_iword = next_iword_030ce;
x_next_ilong = next_ilong_030ce;
x_put_long = put_long_ce030;
x_put_word = put_word_ce030;
x_put_byte = put_byte_ce030;
x_get_long = get_long_ce030;
x_get_word = get_word_ce030;
x_get_byte = get_byte_ce030;
}
}
static void set_cpu_caches (void)
{
int i;
for (i = 0; i < CPU_PIPELINE_MAX; i++)
regs.prefetch020addr[i] = 0xffffffff;
#ifdef JIT
if (currprefs.cachesize) {
if (currprefs.cpu_model < 68040) {
set_cache_state (regs.cacr & 1);
if (regs.cacr & 0x08) {
flush_icache (0, 3);
}
} else {
set_cache_state ((regs.cacr & 0x8000) ? 1 : 0);
}
}
#endif
if (currprefs.cpu_model == 68020) {
if (regs.cacr & 0x08) { // clear instr cache
for (i = 0; i < CACHELINES020; i++)
caches020[i].valid = 0;
}
if (regs.cacr & 0x04) { // clear entry in instr cache
caches020[(regs.caar >> 2) & (CACHELINES020 - 1)].valid = 0;
regs.cacr &= ~0x04;
}
} else if (currprefs.cpu_model == 68030) {
//regs.cacr |= 0x100;
if (regs.cacr & 0x08) { // clear instr cache
for (i = 0; i < CACHELINES030; i++) {
icaches030[i].valid[0] = 0;
icaches030[i].valid[1] = 0;
icaches030[i].valid[2] = 0;
icaches030[i].valid[3] = 0;
}
}
if (regs.cacr & 0x04) { // clear entry in instr cache
icaches030[(regs.caar >> 4) & (CACHELINES030 - 1)].valid[(regs.caar >> 2) & 3] = 0;
regs.cacr &= ~0x04;
}
if (regs.cacr & 0x800) { // clear data cache
for (i = 0; i < CACHELINES030; i++) {
dcaches030[i].valid[0] = 0;
dcaches030[i].valid[1] = 0;
dcaches030[i].valid[2] = 0;
dcaches030[i].valid[3] = 0;
}
regs.cacr &= ~0x800;
}
if (regs.cacr & 0x400) { // clear entry in data cache
dcaches030[(regs.caar >> 4) & (CACHELINES030 - 1)].valid[(regs.caar >> 2) & 3] = 0;
regs.cacr &= ~0x400;
}
} else if (currprefs.cpu_model == 68040) {
if (!(regs.cacr & 0x8000)) {
for (i = 0; i < CACHESETS040; i++) {
caches040[i].valid[0] = 0;
caches040[i].valid[1] = 0;
caches040[i].valid[2] = 0;
caches040[i].valid[3] = 0;
}
}
}
}
STATIC_INLINE void count_instr (unsigned int opcode)
{
}
static unsigned long REGPARAM3 op_illg_1 (uae_u32 opcode) REGPARAM;
static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
{
op_illg (opcode);
return 4;
}
static void build_cpufunctbl (void)
{
int i, opcnt;
unsigned long opcode;
const struct cputbl *tbl = 0;
int lvl;
switch (currprefs.cpu_model)
{
#ifdef CPUEMU_0
#ifndef CPUEMU_68000_ONLY
case 68060:
lvl = 5;
tbl = op_smalltbl_0_ff;
if (currprefs.cpu_cycle_exact)
tbl = op_smalltbl_21_ff;
if (currprefs.mmu_model)
tbl = op_smalltbl_31_ff;
break;
case 68040:
lvl = 4;
tbl = op_smalltbl_1_ff;
if (currprefs.cpu_cycle_exact)
tbl = op_smalltbl_22_ff;
if (currprefs.mmu_model)
tbl = op_smalltbl_31_ff;
break;
case 68030:
lvl = 3;
tbl = op_smalltbl_2_ff;
if (currprefs.cpu_cycle_exact)
tbl = op_smalltbl_23_ff;
break;
case 68020:
lvl = 2;
tbl = op_smalltbl_3_ff;
if (currprefs.cpu_cycle_exact)
tbl = op_smalltbl_20_ff;
break;
case 68010:
lvl = 1;
tbl = op_smalltbl_4_ff;
break;
#endif
#endif
default:
changed_prefs.cpu_model = currprefs.cpu_model = 68000;
case 68000:
lvl = 0;
tbl = op_smalltbl_5_ff;
#ifdef CPUEMU_11
if (currprefs.cpu_compatible)
tbl = op_smalltbl_11_ff; /* prefetch */
#endif
#ifdef CPUEMU_12
if (currprefs.cpu_cycle_exact)
tbl = op_smalltbl_12_ff; /* prefetch and cycle-exact */
#endif
break;
}
if (tbl == 0) {
write_log (L"no CPU emulation cores available CPU=%d!", currprefs.cpu_model);
abort ();
}
for (opcode = 0; opcode < 65536; opcode++)
cpufunctbl[opcode] = op_illg_1;
for (i = 0; tbl[i].handler != NULL; i++) {
opcode = tbl[i].opcode;
cpufunctbl[opcode] = tbl[i].handler;
}
/* hack fpu to 68000/68010 mode */
if (currprefs.fpu_model && currprefs.cpu_model < 68020) {
tbl = op_smalltbl_3_ff;
for (i = 0; tbl[i].handler != NULL; i++) {
if ((tbl[i].opcode & 0xfe00) == 0xf200)
cpufunctbl[tbl[i].opcode] = tbl[i].handler;
}
}
opcnt = 0;
for (opcode = 0; opcode < 65536; opcode++) {
cpuop_func *f;
if (table68k[opcode].mnemo == i_ILLG)
continue;
if (currprefs.fpu_model && currprefs.cpu_model < 68020) {
/* more hack fpu to 68000/68010 mode */
if (table68k[opcode].clev > lvl && (opcode & 0xfe00) != 0xf200)
continue;
} else if (table68k[opcode].clev > lvl) {
continue;
}
if (table68k[opcode].handler != -1) {
int idx = table68k[opcode].handler;
f = cpufunctbl[idx];
if (f == op_illg_1)
abort ();
cpufunctbl[opcode] = f;
opcnt++;
}
}
write_log (L"Building CPU, %d opcodes (%d %d %d)\n",
opcnt, lvl,
currprefs.cpu_cycle_exact ? -1 : currprefs.cpu_compatible ? 1 : 0, currprefs.address_space_24);
write_log (L"CPU=%d, FPU=%d, MMU=%d, JIT%s=%d.\n",
currprefs.cpu_model, currprefs.fpu_model,
currprefs.mmu_model,
currprefs.cachesize ? (currprefs.compfpu ? L"=CPU/FPU" : L"=CPU") : L"",
currprefs.cachesize);
#ifdef JIT
build_comp ();
#endif
set_cpu_caches ();
if (currprefs.mmu_model) {
mmu_reset ();
mmu_set_tc (regs.tcr);
mmu_set_super (regs.s != 0);
}
}
void fill_prefetch_slow (void)
{
if (currprefs.mmu_model)
return;
regs.ir = x_get_word (m68k_getpc ());
regs.irc = x_get_word (m68k_getpc () + 2);
}
unsigned long cycles_mask, cycles_val;
static void update_68k_cycles (void)
{
cycles_mask = 0;
cycles_val = currprefs.m68k_speed;
if (currprefs.m68k_speed < 1) {
cycles_mask = 0xFFFFFFFF;
cycles_val = 0;
}
currprefs.cpu_clock_multiplier = changed_prefs.cpu_clock_multiplier;
currprefs.cpu_frequency = changed_prefs.cpu_frequency;
baseclock = currprefs.ntscmode ? 28636360 : 28375160;
cpucycleunit = CYCLE_UNIT / 2;
if (currprefs.cpu_clock_multiplier) {
if (currprefs.cpu_clock_multiplier >= 256) {
cpucycleunit = CYCLE_UNIT / (currprefs.cpu_clock_multiplier >> 8);
} else {
cpucycleunit = CYCLE_UNIT * currprefs.cpu_clock_multiplier;
}
} else if (currprefs.cpu_frequency) {
cpucycleunit = CYCLE_UNIT * baseclock / currprefs.cpu_frequency;
}
if (cpucycleunit < 1)
cpucycleunit = 1;
if (currprefs.cpu_cycle_exact)
write_log (L"CPU cycleunit: %d (%.3f)\n", cpucycleunit, (float)cpucycleunit / CYCLE_UNIT);
config_changed = 1;
}
static void prefs_changed_cpu (void)
{
fixup_cpu (&changed_prefs);
currprefs.cpu_model = changed_prefs.cpu_model;
currprefs.fpu_model = changed_prefs.fpu_model;
currprefs.mmu_model = changed_prefs.mmu_model;
currprefs.cpu_compatible = changed_prefs.cpu_compatible;
currprefs.cpu_cycle_exact = changed_prefs.cpu_cycle_exact;
currprefs.blitter_cycle_exact = changed_prefs.cpu_cycle_exact;
}
void check_prefs_changed_cpu (void)
{
bool changed = 0;
if (!config_changed)
return;
#ifdef JIT
changed = check_prefs_changed_comp ();
#endif
if (changed
|| currprefs.cpu_model != changed_prefs.cpu_model
|| currprefs.fpu_model != changed_prefs.fpu_model
|| currprefs.mmu_model != changed_prefs.mmu_model
|| currprefs.cpu_compatible != changed_prefs.cpu_compatible
|| currprefs.cpu_cycle_exact != changed_prefs.cpu_cycle_exact) {
prefs_changed_cpu ();
if (!currprefs.cpu_compatible && changed_prefs.cpu_compatible)
fill_prefetch_slow ();
build_cpufunctbl ();
changed = 1;
}
if (changed
|| currprefs.m68k_speed != changed_prefs.m68k_speed
|| currprefs.cpu_clock_multiplier != changed_prefs.cpu_clock_multiplier
|| currprefs.cpu_frequency != changed_prefs.cpu_frequency) {
currprefs.m68k_speed = changed_prefs.m68k_speed;
reset_frame_rate_hack ();
update_68k_cycles ();
changed = 1;
}
if (currprefs.cpu_idle != changed_prefs.cpu_idle) {
currprefs.cpu_idle = changed_prefs.cpu_idle;
}
if (changed)
set_special (SPCFLAG_BRK);
}
void init_m68k (void)
{
int i;
prefs_changed_cpu ();
update_68k_cycles ();
for (i = 0 ; i < 256 ; i++) {
int j;
for (j = 0 ; j < 8 ; j++) {
if (i & (1 << j)) break;
}
movem_index1[i] = j;
movem_index2[i] = 7-j;
movem_next[i] = i & (~(1 << j));
}
#if COUNT_INSTRS
{
FILE *f = fopen (icountfilename (), "r");
memset (instrcount, 0, sizeof instrcount);
if (f) {
uae_u32 opcode, count, total;
TCHAR name[20];
write_log (L"Reading instruction count file...\n");
fscanf (f, "Total: %lu\n", &total);
while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
instrcount[opcode] = count;
}
fclose (f);
}
}
#endif
write_log (L"Building CPU table for configuration: %d", currprefs.cpu_model);
regs.address_space_mask = 0xffffffff;
if (currprefs.cpu_compatible) {
if (currprefs.address_space_24 && currprefs.cpu_model >= 68030)
currprefs.address_space_24 = false;
}
if (currprefs.fpu_model > 0)
write_log (L"/%d", currprefs.fpu_model);
if (currprefs.cpu_cycle_exact) {
if (currprefs.cpu_model == 68000)
write_log (L" prefetch and cycle-exact");
else
write_log (L" ~cycle-exact");
} else if (currprefs.cpu_compatible)
write_log (L" prefetch");
if (currprefs.address_space_24) {
regs.address_space_mask = 0x00ffffff;
write_log (L" 24-bit");
}
write_log (L"\n");
read_table68k ();
do_merges ();
write_log (L"%d CPU functions\n", nr_cpuop_funcs);
build_cpufunctbl ();
set_x_funcs ();
#ifdef JIT
/* We need to check whether NATMEM settings have changed
* before starting the CPU */
check_prefs_changed_comp ();
#endif
}
struct regstruct regs, mmu_backup_regs;
struct flag_struct regflags;
static struct regstruct regs_backup[16];
static int backup_pointer = 0;
static long int m68kpc_offset;
#define get_ibyte_1(o) get_byte (regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
#define get_iword_1(o) get_word (regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
#define get_ilong_1(o) get_long (regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
static uae_s32 ShowEA (void *f, uae_u16 opcode, int reg, amodes mode, wordsizes size, TCHAR *buf, uae_u32 *eaddr, int safemode)
{
uae_u16 dp;
uae_s8 disp8;
uae_s16 disp16;
int r;
uae_u32 dispreg;
uaecptr addr = 0;
uae_s32 offset = 0;
TCHAR buffer[80];
switch (mode){
case Dreg:
_stprintf (buffer, L"D%d", reg);
break;
case Areg:
_stprintf (buffer, L"A%d", reg);
break;
case Aind:
_stprintf (buffer, L"(A%d)", reg);
addr = regs.regs[reg + 8];
break;
case Aipi:
_stprintf (buffer, L"(A%d)+", reg);
addr = regs.regs[reg + 8];
break;
case Apdi:
_stprintf (buffer, L"-(A%d)", reg);
addr = regs.regs[reg + 8];
break;
case Ad16:
{
TCHAR offtxt[80];
disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
if (disp16 < 0)
_stprintf (offtxt, L"-$%04x", -disp16);
else
_stprintf (offtxt, L"$%04x", disp16);
addr = m68k_areg (regs, reg) + disp16;
_stprintf (buffer, L"(A%d, %s) == $%08lx", reg, offtxt, (unsigned long)addr);
}
break;
case Ad8r:
dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
disp8 = dp & 0xFF;
r = (dp & 0x7000) >> 12;
dispreg = dp & 0x8000 ? m68k_areg (regs, r) : m68k_dreg (regs, r);
if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
dispreg <<= (dp >> 9) & 3;
if (dp & 0x100) {
uae_s32 outer = 0, disp = 0;
uae_s32 base = m68k_areg (regs, reg);
TCHAR name[10];
_stprintf (name, L"A%d, ", reg);
if (dp & 0x80) { base = 0; name[0] = 0; }
if (dp & 0x40) dispreg = 0;
if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
base += disp;
if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
if (!(dp & 4)) base += dispreg;
if ((dp & 3) && !safemode) base = get_long (base);
if (dp & 4) base += dispreg;
addr = base + outer;
_stprintf (buffer, L"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
1 << ((dp >> 9) & 3),
disp, outer,
(unsigned long)addr);
} else {
addr = m68k_areg (regs, reg) + (uae_s32)((uae_s8)disp8) + dispreg;
_stprintf (buffer, L"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
1 << ((dp >> 9) & 3), disp8,
(unsigned long)addr);
}
break;
case PC16:
addr = m68k_getpc () + m68kpc_offset;
disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
addr += (uae_s16)disp16;
_stprintf (buffer, L"(PC,$%04x) == $%08lx", disp16 & 0xffff, (unsigned long)addr);
break;
case PC8r:
addr = m68k_getpc () + m68kpc_offset;
dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
disp8 = dp & 0xFF;
r = (dp & 0x7000) >> 12;
dispreg = dp & 0x8000 ? m68k_areg (regs, r) : m68k_dreg (regs, r);
if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
dispreg <<= (dp >> 9) & 3;
if (dp & 0x100) {
uae_s32 outer = 0, disp = 0;
uae_s32 base = addr;
TCHAR name[10];
_stprintf (name, L"PC, ");
if (dp & 0x80) { base = 0; name[0] = 0; }
if (dp & 0x40) dispreg = 0;
if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
base += disp;
if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
if (!(dp & 4)) base += dispreg;
if ((dp & 3) && !safemode) base = get_long (base);
if (dp & 4) base += dispreg;
addr = base + outer;
_stprintf (buffer, L"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
1 << ((dp >> 9) & 3),
disp, outer,
(unsigned long)addr);
} else {
addr += (uae_s32)((uae_s8)disp8) + dispreg;
_stprintf (buffer, L"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
(int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
disp8, (unsigned long)addr);
}
break;
case absw:
addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
_stprintf (buffer, L"$%08lx", (unsigned long)addr);
m68kpc_offset += 2;
break;
case absl:
addr = get_ilong_1 (m68kpc_offset);
_stprintf (buffer, L"$%08lx", (unsigned long)addr);
m68kpc_offset += 4;
break;
case imm:
switch (size){
case sz_byte:
_stprintf (buffer, L"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
m68kpc_offset += 2;
break;
case sz_word:
_stprintf (buffer, L"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
m68kpc_offset += 2;
break;
case sz_long:
_stprintf (buffer, L"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
m68kpc_offset += 4;
break;
default:
break;
}
break;
case imm0:
offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
m68kpc_offset += 2;
_stprintf (buffer, L"#$%02x", (unsigned int)(offset & 0xff));
break;
case imm1:
offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
m68kpc_offset += 2;
buffer[0] = 0;
_stprintf (buffer, L"#$%04x", (unsigned int)(offset & 0xffff));
break;
case imm2:
offset = (uae_s32)get_ilong_1 (m68kpc_offset);
m68kpc_offset += 4;
_stprintf (buffer, L"#$%08lx", (unsigned long)offset);
break;
case immi:
offset = (uae_s32)(uae_s8)(reg & 0xff);
_stprintf (buffer, L"#$%08lx", (unsigned long)offset);
break;
default:
break;
}
if (buf == 0)
f_out (f, L"%s", buffer);
else
_tcscat (buf, buffer);
if (eaddr)
*eaddr = addr;
return offset;
}
#if 0
/* The plan is that this will take over the job of exception 3 handling -
* the CPU emulation functions will just do a longjmp to m68k_go whenever
* they hit an odd address. */
static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
{
uae_u16 dp;
uae_s8 disp8;
uae_s16 disp16;
int r;
uae_u32 dispreg;
uaecptr addr;
uae_s32 offset = 0;
switch (mode){
case Dreg:
*val = m68k_dreg (regs, reg);
return 1;
case Areg:
*val = m68k_areg (regs, reg);
return 1;
case Aind:
case Aipi:
addr = m68k_areg (regs, reg);
break;
case Apdi:
addr = m68k_areg (regs, reg);
break;
case Ad16:
disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
addr = m68k_areg (regs, reg) + (uae_s16)disp16;
break;
case Ad8r:
addr = m68k_areg (regs, reg);
d8r_common:
dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
disp8 = dp & 0xFF;
r = (dp & 0x7000) >> 12;
dispreg = dp & 0x8000 ? m68k_areg (regs, r) : m68k_dreg (regs, r);
if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
dispreg <<= (dp >> 9) & 3;
if (dp & 0x100) {
uae_s32 outer = 0, disp = 0;
uae_s32 base = addr;
if (dp & 0x80) base = 0;
if (dp & 0x40) dispreg = 0;
if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
base += disp;
if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
if (!(dp & 4)) base += dispreg;
if (dp & 3) base = get_long (base);
if (dp & 4) base += dispreg;
addr = base + outer;
} else {
addr += (uae_s32)((uae_s8)disp8) + dispreg;
}
break;
case PC16:
addr = m68k_getpc () + m68kpc_offset;
disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
addr += (uae_s16)disp16;
break;
case PC8r:
addr = m68k_getpc () + m68kpc_offset;
goto d8r_common;
case absw:
addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
m68kpc_offset += 2;
break;
case absl:
addr = get_ilong_1 (m68kpc_offset);
m68kpc_offset += 4;
break;
case imm:
switch (size){
case sz_byte:
*val = get_iword_1 (m68kpc_offset) & 0xff;
m68kpc_offset += 2;
break;
case sz_word:
*val = get_iword_1 (m68kpc_offset) & 0xffff;
m68kpc_offset += 2;
break;
case sz_long:
*val = get_ilong_1 (m68kpc_offset);
m68kpc_offset += 4;
break;
default:
break;
}
return 1;
case imm0:
*val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
m68kpc_offset += 2;
return 1;
case imm1:
*val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
m68kpc_offset += 2;
return 1;
case imm2:
*val = get_ilong_1 (m68kpc_offset);
m68kpc_offset += 4;
return 1;
case immi:
*val = (uae_s32)(uae_s8)(reg & 0xff);
return 1;
default:
addr = 0;
break;
}
if ((addr & 1) == 0)
return 1;
last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
last_fault_for_exception_3 = addr;
last_writeaccess_for_exception_3 = 0;
last_instructionaccess_for_exception_3 = 0;
return 0;
}
#endif
int get_cpu_model (void)
{
return currprefs.cpu_model;
}
/*
* extract bitfield data from memory and return it in the MSBs
* bdata caches the unmodified data for put_bitfield()
*/
uae_u32 REGPARAM2 get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width)
{
uae_u32 tmp, res, mask;
offset &= 7;
mask = 0xffffffffu << (32 - width);
switch ((offset + width + 7) >> 3) {
case 1:
tmp = get_byte (src);
res = tmp << (24 + offset);
bdata[0] = tmp & ~(mask >> (24 + offset));
break;
case 2:
tmp = get_word (src);
res = tmp << (16 + offset);
bdata[0] = tmp & ~(mask >> (16 + offset));
break;
case 3:
tmp = get_word (src);
res = tmp << (16 + offset);
bdata[0] = tmp & ~(mask >> (16 + offset));
tmp = get_byte (src + 2);
res |= tmp << (8 + offset);
bdata[1] = tmp & ~(mask >> (8 + offset));
break;
case 4:
tmp = get_long (src);
res = tmp << offset;
bdata[0] = tmp & ~(mask >> offset);
break;
case 5:
tmp = get_long (src);
res = tmp << offset;
bdata[0] = tmp & ~(mask >> offset);
tmp = get_byte (src + 4);
res |= tmp >> (8 - offset);
bdata[1] = tmp & ~(mask << (8 - offset));
break;
default:
/* Panic? */
res = 0;
break;
}
return res;
}
/*
* write bitfield data (in the LSBs) back to memory, upper bits
* must be cleared already.
*/
void REGPARAM2 put_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width)
{
offset = (offset & 7) + width;
switch ((offset + 7) >> 3) {
case 1:
put_byte (dst, bdata[0] | (val << (8 - offset)));
break;
case 2:
put_word (dst, bdata[0] | (val << (16 - offset)));
break;
case 3:
put_word (dst, bdata[0] | (val >> (offset - 16)));
put_byte (dst + 2, bdata[1] | (val << (24 - offset)));
break;
case 4:
put_long (dst, bdata[0] | (val << (32 - offset)));
break;
case 5:
put_long (dst, bdata[0] | (val >> (offset - 32)));
put_byte (dst + 4, bdata[1] | (val << (40 - offset)));
break;
}
}
uae_u32 REGPARAM2 x_get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width)
{
uae_u32 tmp, res, mask;
offset &= 7;
mask = 0xffffffffu << (32 - width);
switch ((offset + width + 7) >> 3) {
case 1:
tmp = x_get_byte (src);
res = tmp << (24 + offset);
bdata[0] = tmp & ~(mask >> (24 + offset));
break;
case 2:
tmp = x_get_word (src);
res = tmp << (16 + offset);
bdata[0] = tmp & ~(mask >> (16 + offset));
break;
case 3:
tmp = x_get_word (src);
res = tmp << (16 + offset);
bdata[0] = tmp & ~(mask >> (16 + offset));
tmp = x_get_byte (src + 2);
res |= tmp << (8 + offset);
bdata[1] = tmp & ~(mask >> (8 + offset));
break;