From 012f9aa9982f7a62b1b583b12772576c9f079d3b Mon Sep 17 00:00:00 2001
From: "Esteban \"Skallwar\" Blanc" <estblcsk@gmail.com>
Date: Thu, 10 Oct 2024 09:43:29 +0200
Subject: [PATCH] misc: replace asm! with naked_asm! in naked functions

Fixes: error[E0787]: the `asm!` macro is not allowed in naked functions

Signed-off-by: Esteban Blanc <estblcsk@gmail.com>
---
 hal_aarch64/src/irq.rs | 4 ++--
 hal_aarch64/src/lib.rs | 7 +++----
 hal_riscv64/src/irq.rs | 5 ++---
 hal_riscv64/src/lib.rs | 4 ++--
 4 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/hal_aarch64/src/irq.rs b/hal_aarch64/src/irq.rs
index f7b09d0..6e382f8 100644
--- a/hal_aarch64/src/irq.rs
+++ b/hal_aarch64/src/irq.rs
@@ -1,3 +1,4 @@
+use core::arch::naked_asm;
 use core::ptr;
 use core::sync::atomic::{AtomicPtr, Ordering};
 
@@ -57,7 +58,7 @@ macro_rules! gen_isr_stub {
 #[no_mangle]
 #[repr(align(0x800))]
 unsafe extern "C" fn el1_vector_table() {
-    core::arch::asm!(
+    naked_asm!(
         gen_isr_stub!(),
         gen_isr_stub!(),
         gen_isr_stub!(),
@@ -70,7 +71,6 @@ unsafe extern "C" fn el1_vector_table() {
         gen_isr_stub!(),
         gen_isr_stub!(),
         gen_isr_stub!(),
-        options(noreturn)
     );
 }
 
diff --git a/hal_aarch64/src/lib.rs b/hal_aarch64/src/lib.rs
index 4f1d0c1..70e1783 100644
--- a/hal_aarch64/src/lib.rs
+++ b/hal_aarch64/src/lib.rs
@@ -5,7 +5,7 @@
 use cortex_a::registers::*;
 use tock_registers::interfaces::Readable;
 
-use core::arch::asm;
+use core::arch::naked_asm;
 
 pub mod cpu;
 pub mod irq;
@@ -32,14 +32,13 @@ pub fn panic_info() -> PanicInfo {
 #[naked]
 #[no_mangle]
 unsafe extern "C" fn _start() -> ! {
-    asm!(
+    naked_asm!(
         "
         adrp x9, STACK_START
         msr spsel, xzr
         mov sp, x9
         b k_main
-        ",
-        options(noreturn)
+        "
     );
 }
 
diff --git a/hal_riscv64/src/irq.rs b/hal_riscv64/src/irq.rs
index 1e7c9de..8e6090b 100644
--- a/hal_riscv64/src/irq.rs
+++ b/hal_riscv64/src/irq.rs
@@ -5,7 +5,7 @@ use log;
 use super::plic::Plic;
 use super::registers;
 
-use core::arch::asm;
+use core::arch::naked_asm;
 use core::ptr;
 use core::sync::atomic::{AtomicPtr, Ordering};
 
@@ -228,7 +228,7 @@ extern "C" fn c_trap_dispatch(cause: u64) -> u64 {
 #[no_mangle]
 #[repr(align(4))]
 unsafe extern "C" fn asm_trap_handler() {
-    asm!(
+    naked_asm!(
         "
         addi sp, sp, -0x100
 
@@ -315,7 +315,6 @@ unsafe extern "C" fn asm_trap_handler() {
         addi sp, sp, 0x100
 
         sret",
-        options(noreturn)
     );
     // Obviously this isn't done, we need to jump back to the previous context before the
     // interrupt using mpp/spp and mepc/sepc.
diff --git a/hal_riscv64/src/lib.rs b/hal_riscv64/src/lib.rs
index e04deb0..42c919f 100644
--- a/hal_riscv64/src/lib.rs
+++ b/hal_riscv64/src/lib.rs
@@ -7,14 +7,14 @@ pub mod mm;
 mod plic;
 mod registers;
 
-use core::arch::asm;
+use core::arch::naked_asm;
 
 pub fn panic_info() {}
 
 #[naked]
 #[no_mangle]
 unsafe extern "C" fn _start() -> ! {
-    asm!("la sp, STACK_START", "call k_main", options(noreturn));
+    naked_asm!("la sp, STACK_START", "call k_main");
 }
 
 pub struct Riscv64CoreInfo;