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vivado.log
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vivado.log
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#-----------------------------------------------------------
# Vivado v2020.2 (64-bit)
# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
# Start of session at: Wed Apr 13 22:54:00 2022
# Process ID: 29787
# Current directory: /home/liuh0f/project/pro1
# Command line: vivado
# Log file: /home/liuh0f/project/pro1/vivado.log
# Journal file: /home/liuh0f/project/pro1/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /home/liuh0f/test/test_pro/test_pro.xpr
WARNING: [filemgmt 56-3] Default IP Output Path : Could not find the directory '/home/liuh0f/test/test_pro/test_pro.gen/sources_1'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/sw/workstations/apps/linux-ubuntu18.04-ivybridge/xilinx/2020.2/gcc-7.5.0/egagsozgixafjmnittzgqtr2zi55uxhw/Vivado/2020.2/data/ip'.
INFO: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
open_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:09 . Memory (MB): peak = 7430.855 ; gain = 58.176 ; free physical = 481025 ; free virtual = 500490
update_compile_order -fileset sources_1
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/liuh0f/test/test_pro/test_pro.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'a_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/liuh0f/test/test_pro/test_pro.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj a_tb_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/liuh0f/test/test_pro/test_pro.srcs/sources_1/new/a.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module a
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/liuh0f/test/test_pro/test_pro.srcs/sim_1/new/a_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module a_tb
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/liuh0f/test/test_pro/test_pro.sim/sim_1/behav/xsim'
xelab -wto c7eac34b1fe74225bfe6672a59e7732f --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot a_tb_behav xil_defaultlib.a_tb xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /sw/workstations/apps/linux-ubuntu18.04-ivybridge/xilinx/2020.2/gcc-7.5.0/egagsozgixafjmnittzgqtr2zi55uxhw/Vivado/2020.2/bin/unwrapped/lnx64.o/xelab -wto c7eac34b1fe74225bfe6672a59e7732f --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot a_tb_behav xil_defaultlib.a_tb xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
WARNING: [XSIM 43-3431] One or more environment variables have been detected which affect the operation of the C compiler. These are typically not set in standard installations and are not tested by Xilinx, however they may be appropriate for your system, so the flow will attempt to continue. If errors occur, try running xelab with the "-mt off -v 1" switches to see more information from the C compiler. The following environment variables have been detected:
LIBRARY_PATH
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.a
Compiling module xil_defaultlib.a_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot a_tb_behav
****** Webtalk v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /home/liuh0f/test/test_pro/test_pro.sim/sim_1/behav/xsim/xsim.dir/a_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Apr 13 22:57:00 2022...
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/liuh0f/test/test_pro/test_pro.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "a_tb_behav -key {Behavioral:sim_1:Functional:a_tb} -tclbatch {a_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
source a_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'a_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 7632.074 ; gain = 164.047 ; free physical = 481159 ; free virtual = 500479
run all