Bitstream manipulation for programmable clock network

[tangxifan]

Is your feature request related to a problem? Please describe.
To satisfy the growing demands in corner case evaluation during sign-off, various FPGA bitstreams are required, each of which represents an unique configuration. Note that these configurations cannot be merged, as the same paths in an FPGA are required to be enabled or disabled, representing two operating modes.
Also, these configurations are not synthesizable or consume a lot of effort to develop HDL designs that can result in the desired bitstream.

Clock network is such a case which requires very intensive efforts during sign-off. Engineers may wish to turn on all or part of the clock paths, to check setup/hold time. When there are multiple clocks, engineers have to check the performance of each clock.
Even though the existing command route_clock_rr_graph by default route all the clocks in the global network. It does not enable the clock tap multiplexer (See the green line in the figure below) unless it is mapped. Therefore, we need a dedicated feature to force enabling the clock tap multiplexer.

Describe the solution you'd like

Add a new syntax clock_routing to the bitstream setting file, which allows user to select which clock is selected to propagate at the tap point. Note that

For example,

<openfpga_bitstream_setting>
  <clock_routing network="clk_tree_2lvl" pin="clk[0]"/>
  <clock_routing network="rst_tree_2lvl" pin="rst[1]"/>
</openfpga_bitstream_setting>

The network and pin correspond to the clock network name and a valid pin of global_port in the clock network description.

  <clock_network name="clk_tree_2lvl" global_port="clk[0:7]"/>
  <clock_network name="rst_tree_2lvl" global_port="rst[0:7]"/>