From f31e1ca2528237f74deaa5da75000f6d29df6ca1 Mon Sep 17 00:00:00 2001
From: Alexander Williams <awill@opentitan.org>
Date: Fri, 19 Jan 2024 16:10:57 -0800
Subject: [PATCH] test_virtual: Create test case for desired resolution

Extend test_virtual() cases to show desired dependency resolution when
one core depends on a virtual VLNV and another core has an explicit
dependency on an implementing core for that virtual VLNV. The solver
should choose that one implementing core and no other.

Signed-off-by: Alexander Williams <awill@opentitan.org>
---
 tests/capi2_cores/virtual/top_impl1.core | 21 ++++++++++++++++++
 tests/capi2_cores/virtual/top_impl2.core | 21 ++++++++++++++++++
 tests/test_coremanager.py                | 27 ++++++++++++++----------
 3 files changed, 58 insertions(+), 11 deletions(-)
 create mode 100644 tests/capi2_cores/virtual/top_impl1.core
 create mode 100644 tests/capi2_cores/virtual/top_impl2.core

diff --git a/tests/capi2_cores/virtual/top_impl1.core b/tests/capi2_cores/virtual/top_impl1.core
new file mode 100644
index 00000000..dfafdefc
--- /dev/null
+++ b/tests/capi2_cores/virtual/top_impl1.core
@@ -0,0 +1,21 @@
+CAPI=2:
+# Copyright FuseSoC contributors
+# Licensed under the 2-Clause BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-2-Clause
+
+name: ::top_impl1:0
+filesets:
+  rtl:
+    depend:
+      - ::user:0
+      - ::impl1:0
+    files:
+      - top_impl1.sv
+    file_type: systemVerilogSource
+
+
+targets:
+  default:
+    filesets:
+      - rtl
+    toplevel: top_impl1
diff --git a/tests/capi2_cores/virtual/top_impl2.core b/tests/capi2_cores/virtual/top_impl2.core
new file mode 100644
index 00000000..10110afb
--- /dev/null
+++ b/tests/capi2_cores/virtual/top_impl2.core
@@ -0,0 +1,21 @@
+CAPI=2:
+# Copyright FuseSoC contributors
+# Licensed under the 2-Clause BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-2-Clause
+
+name: ::top_impl2:0
+filesets:
+  rtl:
+    depend:
+      - ::user:0
+      - ::impl2:0
+    files:
+      - top_impl2.sv
+    file_type: systemVerilogSource
+
+
+targets:
+  default:
+    filesets:
+      - rtl
+    toplevel: top_impl2
diff --git a/tests/test_coremanager.py b/tests/test_coremanager.py
index ba30355f..4b3e071d 100644
--- a/tests/test_coremanager.py
+++ b/tests/test_coremanager.py
@@ -243,17 +243,22 @@ def test_virtual():
     cm = CoreManager(Config())
     cm.add_library(Library("virtual", core_dir))
 
-    root_core = cm.get_core(Vlnv("::user"))
+    test_vectors = {
+        "::top_impl1": ["::impl1:0", "::user:0", "::top_impl1:0"],
+        "::top_impl2": ["::impl2:0", "::user:0", "::top_impl2:0"],
+    }
+    for top_vlnv, expected_deps in test_vectors.items():
+        root_core = cm.get_core(Vlnv(top_vlnv))
 
-    edalizer = Edalizer(
-        toplevel=root_core.name,
-        flags=flags,
-        core_manager=cm,
-        work_root=work_root,
-    )
-    edalizer.run()
+        edalizer = Edalizer(
+            toplevel=root_core.name,
+            flags=flags,
+            core_manager=cm,
+            work_root=work_root,
+        )
+        edalizer.run()
 
-    deps = cm.get_depends(root_core.name, {})
-    deps_names = [str(c) for c in deps]
+        deps = cm.get_depends(root_core.name, {})
+        deps_names = [str(c) for c in deps]
 
-    assert deps_names == ["::impl2:0", "::user:0"]
+        assert deps_names == expected_deps