From 604ba343bb7f1d2969b7d3584378d034630d13e3 Mon Sep 17 00:00:00 2001 From: Greg Chadwick Date: Thu, 20 Jun 2024 16:21:46 +0100 Subject: [PATCH] [dv] Fix race condition in ibex_mem_intf_agent Previous code working with clocking blocks synced to the raw clock event. Instead they should sync to the clocking block event. This ensures the values being read are the latest values rather than a cycle old. In particular for ibex_mem_intf_agent this meant it was unable to produce a single cycle response to any memory transaction. With this fix these are now observed. --- .../common/ibex_mem_intf_agent/ibex_mem_intf_monitor.sv | 6 +++--- .../ibex_mem_intf_agent/ibex_mem_intf_response_driver.sv | 8 +++++--- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_monitor.sv b/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_monitor.sv index e8c48f8f47..51a99dfbdd 100644 --- a/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_monitor.sv +++ b/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_monitor.sv @@ -54,7 +54,7 @@ class ibex_mem_intf_monitor extends uvm_monitor; ibex_mem_intf_seq_item trans_collected; forever begin trans_collected = ibex_mem_intf_seq_item::type_id::create("trans_collected"); - while(!(vif.monitor_cb.request && vif.monitor_cb.grant)) vif.wait_clks(1); + while(!(vif.monitor_cb.request && vif.monitor_cb.grant)) @(vif.monitor_cb); trans_collected.addr = vif.monitor_cb.addr; trans_collected.be = vif.monitor_cb.be; trans_collected.misaligned_first = vif.monitor_cb.misaligned_first; @@ -71,7 +71,7 @@ class ibex_mem_intf_monitor extends uvm_monitor; addr_ph_port.write(trans_collected); `uvm_info(get_full_name(),"Send through addr_ph_port", UVM_HIGH) collect_response_queue.put(trans_collected); - vif.wait_clks(1); + @(vif.monitor_cb); end endtask : collect_address_phase @@ -80,7 +80,7 @@ class ibex_mem_intf_monitor extends uvm_monitor; forever begin collect_response_queue.get(trans_collected); do - vif.wait_clks(1); + @(vif.monitor_cb); while(vif.monitor_cb.rvalid === 0); if (trans_collected.read_write == READ) begin diff --git a/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_driver.sv b/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_driver.sv index b907a74419..45ed17986c 100644 --- a/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_driver.sv +++ b/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_driver.sv @@ -66,7 +66,7 @@ class ibex_mem_intf_response_driver extends uvm_driver #(ibex_mem_intf_seq_item) begin forever begin ibex_mem_intf_seq_item req, req_c; - cfg.vif.wait_clks(1); + @(cfg.vif.response_driver_cb); seq_item_port.get_next_item(req); $cast(req_c, req.clone()); if(~cfg.vif.response_driver_cb.reset) begin @@ -112,14 +112,16 @@ class ibex_mem_intf_response_driver extends uvm_driver #(ibex_mem_intf_seq_item) virtual protected task send_read_data(); ibex_mem_intf_seq_item tr; forever begin - cfg.vif.wait_clks(1); + @(cfg.vif.response_driver_cb); cfg.vif.response_driver_cb.rvalid <= 1'b0; cfg.vif.response_driver_cb.rdata <= 'x; cfg.vif.response_driver_cb.rintg <= 'x; cfg.vif.response_driver_cb.error <= 'x; rdata_queue.get(tr); if(cfg.vif.response_driver_cb.reset) continue; - cfg.vif.wait_clks(tr.rvalid_delay); + + repeat (tr.rvalid_delay) @(cfg.vif.response_driver_cb); + if(~cfg.vif.response_driver_cb.reset) begin cfg.vif.response_driver_cb.rvalid <= 1'b1; cfg.vif.response_driver_cb.error <= tr.error;