diff --git a/blog/2024/02/opentitan-commercial-viability/index.html b/blog/2024/02/opentitan-commercial-viability/index.html new file mode 100644 index 00000000..1bf427f5 --- /dev/null +++ b/blog/2024/02/opentitan-commercial-viability/index.html @@ -0,0 +1 @@ +https://www.lowrisc.org/news/2024/02/opentitan-commercial-viability/ \ No newline at end of file diff --git a/index.html b/index.html index 4cb140ed..caad42d3 100644 --- a/index.html +++ b/index.html @@ -1,8 +1,7 @@ lowRISC: Collaborative open silicon engineering

Open to the core

lowRISC is a not-for-profit company with a full stack engineering team based in Cambridge, UK. -We use collaborative engineering to develop and maintain open source silicon designs and tools.

Unveiling Sonata: Affordable CHERI Hardware for Embedded Systems

The lowRISC®/Sunburst team are pleased to announce that the initial Sonata prototype boards have been manufactured by our wholly owned subsidiary NewAE and are currently being tested, marking a significant milestone towards our goal of making CHERI technology widely available to embedded systems engineers. -lowRISC®’s Sonata Board - powered up and running! -Ibex Inside The CHERIoT Ibex core lies at the heart of the Sonata system. Ibex is a production-quality, open-source 32-bit RISC-V CPU core, written in SystemVerilog.

Read More…

open source icon

Open source

Our work is open and permissively licensed, helping to move the industry forward with flexible, accessible and effective systems and tools. We implement and have expertise in the free and open RISC-V ISA.

Durable icon

Durable technology

lowRISC creates infrastructure which will be used, useful and sustainable for future generations of computer systems, by getting the foundations right and not cutting corners.

Excellence icon

Full stack technical excellence

High quality, robust engineering and great documentation are essential to provide useful and maintainable technology. lowRISC create, support and maintain open cores, hardware IP blocks, compiler infrastructure and test and verification systems.

collaborative icon

Collaborative engineering

We work closely with others, testing new ideas and developing systems together, and sharing what we learn and build. lowRISC is part of the open technology ecosystem, and fosters inclusive and participatory communities.

pragmatic icon

Pragmatic

We make choices that enable us to take concrete steps as best we can towards open source silicon being used at scale. lowRISC aims to show that it's entirely possible to develop open source silicon solutions at a quality suitable for large-scale production and deployment.

independent icon

Independent and
not-for-profit

lowRISC is a neutral home for multi-partner projects delivering verified, high quality IP and tools. This enables shared investment into pre-competitive technology and open standards, providing the solid foundations necessary for the rapid development cycles of next generation silicon products.


OpenTitan partners

Announcing OpenTitan, the first transparent silicon root of trust

We are excited to unveil the OpenTitan silicon root of trust project, a new effort built using the successful collaborative engineering model created by lowRISC in partnership with Google and other commercial and academic partners.

This effort sets a new bar for transparency in trusted silicon, and lowRISC is proud to serve as both steward and not-for-profit engineering contributor to OpenTitan, the world’s first open source silicon root of trust.

Silicon root of trust chips increase trust in the integrity of the infrastructure on which software runs. +We use collaborative engineering to develop and maintain open source silicon designs and tools.

OpenTitan® Partnership Makes History as First Open-Source Silicon Project to Reach Commercial Availability

Definitive Project Success is Result of Five Years of Strong Collaboration and Investment by the OpenTitan Coalition to Bring First Trustworthy, Transparent, Secure Silicon Platform to Market +CAMBRIDGE, England – February 13, 2024 – lowRISC C.I.C., the open silicon ecosystem organization, and the OpenTitan coalition today announced a historic milestone as the first open-source silicon project to reach commercial availability, with validated chips in hand. The capstone moment is the result of an unprecedented amount of support and investment by the nine coalition members, including Google, Winbond, Nuvoton, zeroRISC, Rivos, Western Digital, Seagate, ETH Zurich and Giesecke+Devrient, hosted by the non-profit lowRISC CIC.

Read More…

open source icon

Open source

Our work is open and permissively licensed, helping to move the industry forward with flexible, accessible and effective systems and tools. We implement and have expertise in the free and open RISC-V ISA.

Durable icon

Durable technology

lowRISC creates infrastructure which will be used, useful and sustainable for future generations of computer systems, by getting the foundations right and not cutting corners.

Excellence icon

Full stack technical excellence

High quality, robust engineering and great documentation are essential to provide useful and maintainable technology. lowRISC create, support and maintain open cores, hardware IP blocks, compiler infrastructure and test and verification systems.

collaborative icon

Collaborative engineering

We work closely with others, testing new ideas and developing systems together, and sharing what we learn and build. lowRISC is part of the open technology ecosystem, and fosters inclusive and participatory communities.

pragmatic icon

Pragmatic

We make choices that enable us to take concrete steps as best we can towards open source silicon being used at scale. lowRISC aims to show that it's entirely possible to develop open source silicon solutions at a quality suitable for large-scale production and deployment.

independent icon

Independent and
not-for-profit

lowRISC is a neutral home for multi-partner projects delivering verified, high quality IP and tools. This enables shared investment into pre-competitive technology and open standards, providing the solid foundations necessary for the rapid development cycles of next generation silicon products.


OpenTitan partners

Announcing OpenTitan, the first transparent silicon root of trust

We are excited to unveil the OpenTitan silicon root of trust project, a new effort built using the successful collaborative engineering model created by lowRISC in partnership with Google and other commercial and academic partners.

This effort sets a new bar for transparency in trusted silicon, and lowRISC is proud to serve as both steward and not-for-profit engineering contributor to OpenTitan, the world’s first open source silicon root of trust.

Silicon root of trust chips increase trust in the integrity of the infrastructure on which software runs. Open sourcing the silicon design makes it more transparent, trustworthy, and ultimately, secure.


\ No newline at end of file diff --git a/index.xml b/index.xml index 09277320..40ec03bc 100644 --- a/index.xml +++ b/index.xml @@ -1,4 +1,98 @@ -lowRISC: Collaborative open silicon engineeringhttps://www.lowrisc.org/Latest news from lowRISCen-usMon, 15 Jan 2024 00:00:00 +0000 The text content on this website is licensed under a Creative Commons Attribution 4.0 International License, except where otherwise noted. No license is granted for logos or other trademarks. Other content Copyright lowRISC Contributors.Unveiling Sonata: Affordable CHERI Hardware for Embedded Systemshttps://www.lowrisc.org/news/2024/01/sonata-board-update/https://www.lowrisc.org/news/2024/01/sonata-board-update/Mon, 15 Jan 2024 00:00:00 +0000info@lowrisc.org (lowRISC)lowRISC: Collaborative open silicon engineeringhttps://www.lowrisc.org/Latest news from lowRISCen-usTue, 13 Feb 2024 00:00:00 +0000 The text content on this website is licensed under a Creative Commons Attribution 4.0 International License, except where otherwise noted. No license is granted for logos or other trademarks. Other content Copyright lowRISC Contributors.OpenTitan® Partnership Makes History as First Open-Source Silicon Project to Reach Commercial Availabilityhttps://www.lowrisc.org/news/2024/02/opentitan-commercial-viability/https://www.lowrisc.org/news/2024/02/opentitan-commercial-viability/Tue, 13 Feb 2024 00:00:00 +0000info@lowrisc.org (lowRISC)Definitive Project Success is Result of Five Years of Strong Collaboration and Investment by the OpenTitan Coalition to Bring First Trustworthy, Transparent, Secure Silicon Platform to Market

+ +

CAMBRIDGE, England – February 13, 2024 – lowRISC C.I.C., the open silicon ecosystem organization, and the OpenTitan coalition today announced a historic milestone as the first open-source silicon project to reach commercial availability, with validated chips in hand. +The capstone moment is the result of an unprecedented amount of support and investment by the nine coalition members, including Google, Winbond, Nuvoton, zeroRISC, Rivos, Western Digital, Seagate, ETH Zurich and Giesecke+Devrient, hosted by the non-profit lowRISC CIC.

+ + + + + + + + + + + + + + + + + + + + + Silicon + + + + + +

OpenTitan® – The World’s First Commercial-Grade Open-Source Silicon is Here!

+ +

“I am incredibly proud of the OpenTitan partnership for succeeding where every other project has failed – producing the first commercial quality open-source chip in the world,” said Dr. Gavin Ferris, CEO of lowRISC, OpenTitan’s host organization. +“This is the culmination of the monumentally hard work of a vibrant and engaged community of contributors focused on a singular goal to achieve what’s never been done before – make open-source silicon work the same way as open-source software. +I am grateful for this support and can’t wait for what’s to come.”

+ +

Google launched the OpenTitan project together with lowRISC and its partners in 2018 with the goal to make a completely transparent and trustworthy secure silicon platform. +It is the world’s first open-source secure chip to include commercial-grade design verification, top-level testing and continuous integration. +Capable of serving as the hardware root of trust, OpenTitan ensures that the hardware infrastructure and the software that runs on it remain in their intended, trustworthy state by verifying that the critical system components boot securely using only authorized and verifiable code.

+ +

With Google’s support, the project took off from its first year, setting it on a trajectory to make it the most active and successful open-source silicon project in history. +Throughout its lifetime, the OpenTitan coalition thrived as an open silicon ecosystem, consistently following a well-defined roadmap from discrete to integrated secure silicon designs. +The project partners are deeply engaged in this process, ensuring that the final designs are adaptable to many applications. +OpenTitan also has a large and growing community of contributors beyond its formal partners. +As a whole, the community resolves hundreds of pull requests and issues monthly.

+ +

“OpenTitan in silicon is the realization of many years of dedication and hard work from our team. +It is a significant moment for us and all contributors to the project,” emphasized Miguel Osorio, OpenTitan Lead at Google.

+ +

This major milestone follows a series of significant successes for the OpenTitan project in 2023. +Most critically, the project also accomplished the first discrete silicon tapeout in June 2023. +In November 2023, the project coalition announced the first SoC secure execution environment, including RoT functionality, which has enabled coalition partners to embed OpenTitan in their SoC and chiplet designs.

+ +

Supporting Quotes from OpenTitan Members

+ +

“We’ve been privileged to work closely with our OpenTitan coalition partners from early on and are even prouder now to bring the first ‘EarlGrey’ OpenTitan chip design to market, demonstrating our leadership in open, secure ICs,” said Erez Naory, VP of Client and Security Products at Nuvoton. +“Open-source secure silicon is now proven as a radical leap forward in solving the market’s need for a truly trustworthy foundation.”

+ +

“Our mission is to advance the incredible work of the OpenTitan project by delivering an end-to-end supply chain security solution built on an open secure silicon foundation,” said Dom Rizzo, zeroRISC CEO. +“That we’re able to deliver commercial products so soon after tapeout clearly illustrates the coalition’s momentum. +With this first, crucial step for open silicon implementations, we look forward to a world where a transparent and trustworthy supply chain is the default.”

+ +

“The rigor at the heart of the OpenTitan project’s roadmap has ensured the success of this first-of-its-kind, silicon-proven integrated design,” said Tung-Yi Chan, Vice Chairman and Deputy CEO at Winbond. +“By proving the viability of securely integrating certified IPs, OpenTitan opens up new possibilities for SoC vendors. +Winbond supports the OpenTitan initiative with its certified Secure Flash solutions.”

+ +

“We’ve benefited tremendously from the collaborative relationships within the OpenTitan partnership,” said Mark Hayter, Founder and Chief Strategy Officer of Rivos Inc. +“It’s made it easy for us to share our SoC experience to help the coalition provide silicon-proven IP that enables us to integrate RoT into our chiplets.”

+ +

“Seagate is a proud consortium member and contributor of the OpenTitan project,” according to Ed Gage, VP of Seagate Research. +“Both the open-source IP and the OpenTitan chip will set a new baseline for hardware-based security. +Seagate considers this high-quality security IP a key enabler of both enhanced storage device integrity and data protection.”

+ +

“It has been a privilege for Giesecke+Devrient to contribute to the success of OpenTitan so far, as we believe that a secure IP block based on OpenTitan will enable smooth, fast and cost-effective integration into larger SoCs, unlocking a host of new use cases, especially in the IoT ecosystem,” says Bernd Müller, Head of Connectivity and IoT Portfolio Strategy at Giesecke+Devrient. +“With G+D’s trusted embedded operating systems pre-integrated on OpenTitan coupled with our broad portfolio of IoT and connectivity solutions, we are excited for the opportunity this provides us to support customers and projects in this emerging ecosystem.”

+ +

The OpenTitan coalition continues to work in unison to accelerate the project’s momentum. +Upcoming key milestones include the full production release of the “Darjeeling” integrated OpenTitan secure extension environment (SEE) and the first production release of ‘Chai,’ the integrated OpenTitan SEE with support for secure external flash. +In addition, the project will release an updated discrete “EarlGrey” chip design, with additional coverage and development.

+ +

About lowRISC

+ +

Founded in 2014 at the University of Cambridge Department of Computer Science and Technology, lowRISC is a not-for-profit company/CIC that provides a neutral home for collaborative engineering to develop and maintain open-source silicon designs and tools for the long term. +The lowRISC not-for-profit structure combined with full-stack engineering capabilities in-house enables the hosting and management of high-quality projects like OpenTitan via the Silicon Commons approach.

+ +

Media Contacts

+ +

lowRISC@w2comm.com
+OpenTitan@famapr.com

+ ]]>
Unveiling Sonata: Affordable CHERI Hardware for Embedded Systemshttps://www.lowrisc.org/news/2024/01/sonata-board-update/https://www.lowrisc.org/news/2024/01/sonata-board-update/Mon, 15 Jan 2024 00:00:00 +0000info@lowrisc.org (lowRISC)The lowRISC®/Sunburst team are pleased to announce that the initial Sonata prototype boards have been manufactured by our wholly owned subsidiary NewAE and are currently being tested, marking a significant milestone towards our goal of making CHERI technology widely available to embedded systems engineers.

diff --git a/news/2024/02/opentitan-commercial-viability/index.html b/news/2024/02/opentitan-commercial-viability/index.html new file mode 100644 index 00000000..8596f813 --- /dev/null +++ b/news/2024/02/opentitan-commercial-viability/index.html @@ -0,0 +1,28 @@ +OpenTitan® Partnership Makes History as First Open-Source Silicon Project to Reach Commercial Availability · lowRISC: Collaborative open silicon engineering

OpenTitan® Partnership Makes History as First Open-Source Silicon Project to Reach Commercial Availability

Definitive Project Success is Result of Five Years of Strong Collaboration and Investment by the OpenTitan Coalition to Bring First Trustworthy, Transparent, Secure Silicon Platform to Market

CAMBRIDGE, England – February 13, 2024 – lowRISC C.I.C., the open silicon ecosystem organization, and the OpenTitan coalition today announced a historic milestone as the first open-source silicon project to reach commercial availability, with validated chips in hand. +The capstone moment is the result of an unprecedented amount of support and investment by the nine coalition members, including Google, Winbond, Nuvoton, zeroRISC, Rivos, Western Digital, Seagate, ETH Zurich and Giesecke+Devrient, hosted by the non-profit lowRISC CIC.

Silicon

OpenTitan® – The World’s First Commercial-Grade Open-Source Silicon is Here!

“I am incredibly proud of the OpenTitan partnership for succeeding where every other project has failed – producing the first commercial quality open-source chip in the world,” said Dr. Gavin Ferris, CEO of lowRISC, OpenTitan’s host organization. +“This is the culmination of the monumentally hard work of a vibrant and engaged community of contributors focused on a singular goal to achieve what’s never been done before – make open-source silicon work the same way as open-source software. +I am grateful for this support and can’t wait for what’s to come.”

Google launched the OpenTitan project together with lowRISC and its partners in 2018 with the goal to make a completely transparent and trustworthy secure silicon platform. +It is the world’s first open-source secure chip to include commercial-grade design verification, top-level testing and continuous integration. +Capable of serving as the hardware root of trust, OpenTitan ensures that the hardware infrastructure and the software that runs on it remain in their intended, trustworthy state by verifying that the critical system components boot securely using only authorized and verifiable code.

With Google’s support, the project took off from its first year, setting it on a trajectory to make it the most active and successful open-source silicon project in history. +Throughout its lifetime, the OpenTitan coalition thrived as an open silicon ecosystem, consistently following a well-defined roadmap from discrete to integrated secure silicon designs. +The project partners are deeply engaged in this process, ensuring that the final designs are adaptable to many applications. +OpenTitan also has a large and growing community of contributors beyond its formal partners. +As a whole, the community resolves hundreds of pull requests and issues monthly.

“OpenTitan in silicon is the realization of many years of dedication and hard work from our team. +It is a significant moment for us and all contributors to the project,” emphasized Miguel Osorio, OpenTitan Lead at Google.

This major milestone follows a series of significant successes for the OpenTitan project in 2023. +Most critically, the project also accomplished the first discrete silicon tapeout in June 2023. +In November 2023, the project coalition announced the first SoC secure execution environment, including RoT functionality, which has enabled coalition partners to embed OpenTitan in their SoC and chiplet designs.

Supporting Quotes from OpenTitan Members

“We’ve been privileged to work closely with our OpenTitan coalition partners from early on and are even prouder now to bring the first ‘EarlGrey’ OpenTitan chip design to market, demonstrating our leadership in open, secure ICs,” said Erez Naory, VP of Client and Security Products at Nuvoton. +“Open-source secure silicon is now proven as a radical leap forward in solving the market’s need for a truly trustworthy foundation.”

“Our mission is to advance the incredible work of the OpenTitan project by delivering an end-to-end supply chain security solution built on an open secure silicon foundation,” said Dom Rizzo, zeroRISC CEO. +“That we’re able to deliver commercial products so soon after tapeout clearly illustrates the coalition’s momentum. +With this first, crucial step for open silicon implementations, we look forward to a world where a transparent and trustworthy supply chain is the default.”

“The rigor at the heart of the OpenTitan project’s roadmap has ensured the success of this first-of-its-kind, silicon-proven integrated design,” said Tung-Yi Chan, Vice Chairman and Deputy CEO at Winbond. +“By proving the viability of securely integrating certified IPs, OpenTitan opens up new possibilities for SoC vendors. +Winbond supports the OpenTitan initiative with its certified Secure Flash solutions.”

“We’ve benefited tremendously from the collaborative relationships within the OpenTitan partnership,” said Mark Hayter, Founder and Chief Strategy Officer of Rivos Inc. +“It’s made it easy for us to share our SoC experience to help the coalition provide silicon-proven IP that enables us to integrate RoT into our chiplets.”

“Seagate is a proud consortium member and contributor of the OpenTitan project,” according to Ed Gage, VP of Seagate Research. +“Both the open-source IP and the OpenTitan chip will set a new baseline for hardware-based security. +Seagate considers this high-quality security IP a key enabler of both enhanced storage device integrity and data protection.”

“It has been a privilege for Giesecke+Devrient to contribute to the success of OpenTitan so far, as we believe that a secure IP block based on OpenTitan will enable smooth, fast and cost-effective integration into larger SoCs, unlocking a host of new use cases, especially in the IoT ecosystem,” says Bernd Müller, Head of Connectivity and IoT Portfolio Strategy at Giesecke+Devrient. +“With G+D’s trusted embedded operating systems pre-integrated on OpenTitan coupled with our broad portfolio of IoT and connectivity solutions, we are excited for the opportunity this provides us to support customers and projects in this emerging ecosystem.”

The OpenTitan coalition continues to work in unison to accelerate the project’s momentum. +Upcoming key milestones include the full production release of the “Darjeeling” integrated OpenTitan secure extension environment (SEE) and the first production release of ‘Chai,’ the integrated OpenTitan SEE with support for secure external flash. +In addition, the project will release an updated discrete “EarlGrey” chip design, with additional coverage and development.

About lowRISC

Founded in 2014 at the University of Cambridge Department of Computer Science and Technology, lowRISC is a not-for-profit company/CIC that provides a neutral home for collaborative engineering to develop and maintain open-source silicon designs and tools for the long term. +The lowRISC not-for-profit structure combined with full-stack engineering capabilities in-house enables the hosting and management of high-quality projects like OpenTitan via the Silicon Commons approach.

Media Contacts

lowRISC@w2comm.com
OpenTitan@famapr.com

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lowRISC News

Unveiling Sonata: Affordable CHERI Hardware for Embedded Systems

The lowRISC®/Sunburst team are pleased to announce that the initial Sonata prototype boards have been manufactured by our wholly owned subsidiary NewAE and are currently being tested, marking a significant milestone towards our goal of making CHERI technology widely available to embedded systems engineers. +

lowRISC News

OpenTitan® Partnership Makes History as First Open-Source Silicon Project to Reach Commercial Availability

Definitive Project Success is Result of Five Years of Strong Collaboration and Investment by the OpenTitan Coalition to Bring First Trustworthy, Transparent, Secure Silicon Platform to Market +CAMBRIDGE, England – February 13, 2024 – lowRISC C.I.C., the open silicon ecosystem organization, and the OpenTitan coalition today announced a historic milestone as the first open-source silicon project to reach commercial availability, with validated chips in hand. The capstone moment is the result of an unprecedented amount of support and investment by the nine coalition members, including Google, Winbond, Nuvoton, zeroRISC, Rivos, Western Digital, Seagate, ETH Zurich and Giesecke+Devrient, hosted by the non-profit lowRISC CIC.

Read More…

Unveiling Sonata: Affordable CHERI Hardware for Embedded Systems

The lowRISC®/Sunburst team are pleased to announce that the initial Sonata prototype boards have been manufactured by our wholly owned subsidiary NewAE and are currently being tested, marking a significant milestone towards our goal of making CHERI technology widely available to embedded systems engineers. lowRISC®’s Sonata Board - powered up and running! Ibex Inside The CHERIoT Ibex core lies at the heart of the Sonata system. Ibex is a production-quality, open-source 32-bit RISC-V CPU core, written in SystemVerilog.

Read More…

Sunburst Project Update

The Sunburst Project, supported by DSbD/UKRI grant (#107540), focuses on enhancing security within the embedded and operational technology (OpTe) sectors. Its primary goal is to promote the adoption of CHERIoT, an open-source microcontroller technology that integrates CHERI capabilities within the RISC-V architecture. Today lowRISC and NewAE are pleased to announce we’ve already made significant strides towards that goal, which we’ll briefly review in this blog! @@ -12,5 +13,5 @@ OpenTitan’s mission is to provide a secure root of trust, which is complemented by a secure processor core. To address this need, we elevated one of the most widely deployed, highest quality RISC-V cores in academia to the industrial-level of quality characteristic of this project.

Read More…

OpenTitan’s RTL Freeze - Leveraging Transparency to Create Trustworthy Computing

We are delighted to announce an important development for OpenTitan®: RTL Freeze for the Earl Grey discrete, the first OpenTitan chip tapeout. This milestone is a source of immense pride for lowRISC and our OpenTitan partners, because it’s a concrete demonstration of the success of the Silicon Commons™ approach to making silicon radically more transparent and trustworthy. In partnership with Nuvoton, a major TPM vendor, this RTL freeze means that the OpenTitan coalition will have engineering samples of the discrete silicon root of trust (RoT) this calendar year.

Read More…

A Major Milestone for OpenTitan

We are excited to announce today that the OpenTitan project has hit a major tapeout milestone: a feature freeze of its open-source RTL. Together with our partners, we began the OpenTitan project in 2019 with the goal of producing the world’s first open-source silicon Root of Trust (RoT). With this new achievement we are a step closer to realising that goal. -Getting to this point has taken a lot of coordinated work, as we’ve had to navigate the many stumbling blocks that have traditionally made open-source silicon development a challenge.

Read More…

lowRISC wins OpenUK 2022 Awards Hardware Category

We are thrilled to have been selected as the winner of the OpenUK 2022 Awards Hardware Category and would like to thank OpenUK, the award sponsors StackPublishing, the judges and all our hard working staff at lowRISC without whom this would not be possible.

Read More…

\ No newline at end of file diff --git a/news/page/2/index.html b/news/page/2/index.html index 8ad15efc..11278135 100644 --- a/news/page/2/index.html +++ b/news/page/2/index.html @@ -1,6 +1,6 @@ lowRISC News · lowRISC: Collaborative open silicon engineering

lowRISC News

Introducing the Foundation of True Security - the Silicon Root of Trust

Recent headlines about ransomware attacks, account phishing, and identity theft continue to underscore the critical importance of cybersecurity in our everyday lives. This has led to a growing awareness among most businesses and households of important mitigations like encryption, 2-factor authentication and verified software updates. But guess what? There’s an unsung hero behind all these safeguards that underpins their effectiveness: the silicon Root of Trust (RoT). +

lowRISC News

lowRISC wins OpenUK 2022 Awards Hardware Category

We are thrilled to have been selected as the winner of the OpenUK 2022 Awards Hardware Category and would like to thank OpenUK, the award sponsors StackPublishing, the judges and all our hard working staff at lowRISC without whom this would not be possible.

Read More…

Introducing the Foundation of True Security - the Silicon Root of Trust

Recent headlines about ransomware attacks, account phishing, and identity theft continue to underscore the critical importance of cybersecurity in our everyday lives. This has led to a growing awareness among most businesses and households of important mitigations like encryption, 2-factor authentication and verified software updates. But guess what? There’s an unsung hero behind all these safeguards that underpins their effectiveness: the silicon Root of Trust (RoT). And yet, despite the vital role these RoTs play, few people, including even security professionals, are familiar with what a Root of Trust is — or in fact that it even exists.

Read More…

lowRISC Appoints Cybersecurity Expert Prof. Dr. Claudia Eckert to Board of Directors

CAMBRIDGE, United Kingdom, Oct. 5th, 2022 – lowRISC C.I.C., the open source system on a chip (SoC) organization, today announced the appointment of Prof. Dr. Claudia Eckert to its board of directors. Eckert holds the chair for IT Security in the Department of Computer Science at Technical University of Munich (TUM) and is director of the Fraunhofer Institute for Applied and Integrated Security (AISEC) in Munich, overseeing more than 220 researchers.

Read More…

Security Verification of an Open Source Hardware Root of Trust

OpenTitan is a powerful open source silicon root of trust project, designed from scratch as a transparent, trustworthy and secure implementation for enterprises, platform providers and chip manufacturers. Featuring numerous hardware security features ranging from secure boot and remote attestation to secure storage of private user data. The open source development model allows OpenTitan to serve as a vehicle for innovation in academia, but also as an effective commercial platform as well.

Read More…

lowRISC Acquires NewAE Technology, Adding Advanced Security Analysis Tools to the OpenTitan Platform

lowRISC C.I.C., the open source organization dedicated to bringing secure collaborative innovation to silicon development, today announced the acquisition of NewAE Technology, Inc., a privately-held designer and manufacturer of broadly accessible silicon security analysis tools. The acquisition brings added momentum to lowRISC, whose OpenTitan project – a collaboration between lowRISC, Google, Western Digital, Seagate and other commercial and academic partners – has created the first transparent, high-quality reference design and integration guidelines for silicon root of trust (RoT) chips.

Read More…

Andy Hopper knighted for services to Computer Technology

lowRISC is delighted that Andy Hopper, lowRISC’s independent chair, has been knighted for services to Computer Technology. @@ -8,7 +8,5 @@ The culture he created, and his interest in and support for doing things in non-standard ways, has helped to establish over 200 start-ups, including lowRISC CIC.

Read More…

OpenTitan at One Year

Last year, along with our partners, lowRISC announced OpenTitan, the world’s first open source silicon root of trust. The project has progressed rapidly since then. A recent Google Security Blog post detailed key milestones met, our growth in contributors, and revealed news of the first commercial OpenTitan tapeout. OpenTitan’s success demonstrates the value of the lowRISC collaborative engineering model, wherein our full-stack engineering team allows us to serve as an essential development hub.

Read More…

A birthday present for lowRISC: We won an OpenUK Award!

On October 20th, lowRISC CIC won in the Open Hardware category at the 2020 OpenUK Awards, describing lowRISC as “the jewel in the crown of the UK’s open silicon companies”. The OpenUK awards promote “UK Leadership in Open Technology”, and are given out by OpenUK, a UK-based not-for-profit company which supports open source collaboration and open technologies within the United Kingdom. On receiving the award, lowRISC CTO, Alex Bradbury, said “We’re incredibly grateful to have been recognised for our achievements and contributions to date.

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lowRISC's 2020 OpenUK Award

How we used differential testing to rapidly find and fix missed optimisation opportunities in LLVM's RISC-V backend

At this October 2020 LLVM Developers’ Meeting I presented a poster about how, with a surprisingly simple tool, we were able to rapidly identify, isolate, and fix a range of missed optimisation opportunities in LLVM’s RISC-V backend. -The tool works by generating random C programs, compiling each program with both Clang and GCC (targeting RISC-V) and comparing the assembly generated by both compilers. If it estimates that Clang/LLVM generated worse code than GCC then it saves that case for further analysis.

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GSoC Projects Successfully Completed

Time is ticking and summer is almost over already. With that, also our this years’ Google Summer of Code (GSoC) projects are coming to an end. A lot of open-source coding has been done, pull requests have been made, reviewed and merged. Experiments have been conducted, results were gathered, interpreted and presented. Bugs were found and fixed, and the resulting designs further improved. Both our students and mentors have been working hard and we are pleased to announce that both our two projects described below have been completed successfully.

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GSoC Accepted Projects Announcement

We are pleased to announce that we will be mentoring two students as part of Google Summer of Code (GSoC). -We are looking forward to working with Flavien and Yuichi on features and tools to improve IP such as Ibex, our open-source RISC-V core. -Flavien Solt: Simulated Memory Controller It is a common pitfall to misinterpret or incorrectly scale performance numbers derived from benchmarks run on an FPGA-based SoC design.

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The text content on this website is licensed under a Creative Commons Attribution 4.0 International License, except where otherwise noted. No license is granted for logos or other trademarks. Other content © lowRISC Contributors.

Privacy and cookies policy +The tool works by generating random C programs, compiling each program with both Clang and GCC (targeting RISC-V) and comparing the assembly generated by both compilers. If it estimates that Clang/LLVM generated worse code than GCC then it saves that case for further analysis.

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GSoC Projects Successfully Completed

Time is ticking and summer is almost over already. With that, also our this years’ Google Summer of Code (GSoC) projects are coming to an end. A lot of open-source coding has been done, pull requests have been made, reviewed and merged. Experiments have been conducted, results were gathered, interpreted and presented. Bugs were found and fixed, and the resulting designs further improved. Both our students and mentors have been working hard and we are pleased to announce that both our two projects described below have been completed successfully.

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\ No newline at end of file diff --git a/news/page/3/index.html b/news/page/3/index.html index 0d2f9b56..6793bf99 100644 --- a/news/page/3/index.html +++ b/news/page/3/index.html @@ -1,10 +1,12 @@ lowRISC News · lowRISC: Collaborative open silicon engineering

lowRISC News

Students for GSoC projects wanted

We are excited to be back as a mentoring organisation for Google Summer of Code (GSoC) and are currently looking for enthusiastic students interested in doing a project with us. The GSoC initiative gives students the opportunity to spend the summer break gaining real-world hardware and software development experience while earning a stipend from Google. If you’re a student interested in applying, we strongly recommend you read up on how GSoC works and study the Google Summer of Code Student Guide, which contains excellent advice on preparing a high quality proposal.

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At FOSDEM you can hear how we made our Ibex CPU core faster

I’ll be giving a talk in the RISC-V devroom at FOSDEM on Saturday 1st February, in which I’ll describe how we are analysing and improving the performance of the Ibex RISC-V CPU core. I’ll discuss how Verilator is used to simulate Ibex running CoreMark and Embench and how I’ve analysed these simulations to identify major sources of stalls. This is used to inform what improvements should be made. Yosys was used to analyse the impact on area and clock frequency from these changes.

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FOSDEM

lowRISC 101: Introduction to lowRISC at the RISC-V Summit

With the recent announcement of OpenTitan, we at lowRISC had many great conversations about the work we do to produce high-quality open source hardware and software. A great place to continue these discussions is the RISC-V Summit in San Jose, CA (Dec 10 - 12, 2019). lowRISC will showcase its work in the conference track and in the exhibit hall. +

lowRISC News

GSoC Accepted Projects Announcement

We are pleased to announce that we will be mentoring two students as part of Google Summer of Code (GSoC). +We are looking forward to working with Flavien and Yuichi on features and tools to improve IP such as Ibex, our open-source RISC-V core. +Flavien Solt: Simulated Memory Controller It is a common pitfall to misinterpret or incorrectly scale performance numbers derived from benchmarks run on an FPGA-based SoC design.

Read More…

Students for GSoC projects wanted

We are excited to be back as a mentoring organisation for Google Summer of Code (GSoC) and are currently looking for enthusiastic students interested in doing a project with us. The GSoC initiative gives students the opportunity to spend the summer break gaining real-world hardware and software development experience while earning a stipend from Google. If you’re a student interested in applying, we strongly recommend you read up on how GSoC works and study the Google Summer of Code Student Guide, which contains excellent advice on preparing a high quality proposal.

Read More…

At FOSDEM you can hear how we made our Ibex CPU core faster

I’ll be giving a talk in the RISC-V devroom at FOSDEM on Saturday 1st February, in which I’ll describe how we are analysing and improving the performance of the Ibex RISC-V CPU core. I’ll discuss how Verilator is used to simulate Ibex running CoreMark and Embench and how I’ve analysed these simulations to identify major sources of stalls. This is used to inform what improvements should be made. Yosys was used to analyse the impact on area and clock frequency from these changes.

Read More…

FOSDEM

lowRISC 101: Introduction to lowRISC at the RISC-V Summit

With the recent announcement of OpenTitan, we at lowRISC had many great conversations about the work we do to produce high-quality open source hardware and software. A great place to continue these discussions is the RISC-V Summit in San Jose, CA (Dec 10 - 12, 2019). lowRISC will showcase its work in the conference track and in the exhibit hall. At booth 101, lowRISC will showcase its recent work and our engineers will be around to answer your questions.

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Get started with OpenTitan

Interested in trying out the recently announced OpenTitan? We’ve put together a video that goes through an overview of how the OpenTitan prototype system is put together and how to get up and running with our pre-built release (providing simulator binaries and pre-built FPGA images for the Nexys Video Artix-7 board). It follows the steps from the OpenTitan Quickstart Guide. You can find out more about OpenTitan from our announcement blog and the OpenTitan website.

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Announcing OpenTitan, the First Transparent Silicon Root of Trust

Today, we are excited to unveil the OpenTitan silicon root of trust (RoT) project, a new effort built using the successful collaborative engineering model created by lowRISC in partnership with Google and other commercial and academic partners. This effort sets a new bar for transparency in trusted silicon, and lowRISC is proud to serve as both steward and not-for-profit engineering contributor to OpenTitan, the world’s first open source silicon RoT.

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OpenTitan

lowRISC Collaborates with Industry Leaders to Create OpenTitan

Organisations aim to make the hardware root more transparent, trustworthy, and secure for everyone. CAMBRIDGE, England–(BUSINESS WIRE)–lowRISC C.I.C., the open source silicon and tools collaborative engineering company, today announced that it has partnered with ETH Zürich, Google, G+D Mobile Security, Nuvoton Technology and Western Digital in support of OpenTitan, an open source hardware root of trust (RoT) reference design and integration guidelines that enable chip producers and platform providers to build transparently implemented, high-quality hardware RoT chips tailored for data center servers and other devices.

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Andy Hopper joins lowRISC CIC Board as Independent Chair

Today, we are delighted to announce that Professor Andy Hopper, CBE FRS FIET FREng, has joined the lowRISC Board of Directors as Independent Chair. “I’m delighted to be joining lowRISC CIC,” said Prof. Hopper, speaking today from Cambridge UK, “As digital systems pervade every aspect of our lives trust and transparency become crucial. An open source approach allows for public inspection of the principles and implementations being used. I believe the future of digital systems will be underpinned by not for profit organisations that provide design transparency and enable real innovation.

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Andy Hopper

Introducing Greg & Tom

Greg Chadwick and Tom Roberts recently joined lowRISC’s growing engineering team. They’ve both taken some time to share a little about what they’re doing at lowRISC and what motivated them to join. -Greg “It’s an exciting time to join the lowRISC team! Our Ibex core provides a solid foundation and clearly demonstrates the value of open source silicon, which I’m excited to be working on. My work so far has focused on the performance of Ibex; whilst it’s not intended as a high performance core there are various things we can do to improve it without major impact to area or power.

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Ibex on FPGA - Get stuff executed

Our microcontroller-class RISC-V processor core Ibex for sure is a solid base with which to start your own project. Over the past months, we have invested a lot of effort in making the design more mature. This includes refactoring the RTL to make the design more understandable and programmer friendly, adding UVM-based verification to the source tree, but also integrating support for the RISC-V compliance suite and enabling publicly visible, open-source powered continuous integration (CI) to keep the design stable.

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Ibex on the Nexys Video FPGA board

Ibex: Code with Confidence

Ibex, our small RISC-V core, is constantly changing. Roughly 50 percent of the RTL was refactored recently! We added features, tests, and cleaned the code up. We and our collaborators were able to make these changes (mostly) without breaking Ibex because we invested in testing: earlier this year we added UVM-based verification to the tree, and we run these tests after every change. We run static code analysis to catch common programming bugs.

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The text content on this website is licensed under a Creative Commons Attribution 4.0 International License, except where otherwise noted. No license is granted for logos or other trademarks. Other content © lowRISC Contributors.

Privacy and cookies policy +Greg “It’s an exciting time to join the lowRISC team! Our Ibex core provides a solid foundation and clearly demonstrates the value of open source silicon, which I’m excited to be working on. My work so far has focused on the performance of Ibex; whilst it’s not intended as a high performance core there are various things we can do to improve it without major impact to area or power.

Read More…

Ibex on FPGA - Get stuff executed

Our microcontroller-class RISC-V processor core Ibex for sure is a solid base with which to start your own project. Over the past months, we have invested a lot of effort in making the design more mature. This includes refactoring the RTL to make the design more understandable and programmer friendly, adding UVM-based verification to the source tree, but also integrating support for the RISC-V compliance suite and enabling publicly visible, open-source powered continuous integration (CI) to keep the design stable.

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Ibex on the Nexys Video FPGA board
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lowRISC News

Six more weeks of Ibex development - what's new?

In the past months, we have invested considerable effort in improving our RISC-V core Ibex. This 2-stage, in-order, 32-bit microcontroller-class CPU core was contributed to us by ETH Zürich in December 2018, with activity really ramping up since May. Having been taped out multiple times (as zero-riscy) in a mix of academic and industry projects, it came to us as a relatively mature code base. Despite this, we have continued to invest in improving its design and maintainability.

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Ibex cleaning up

Large-scale RISC-V LLVM testing with Buildroot

A few years ago lowRISC started developing a new LLVM backend targeting RISC-V. Rather than copying and modifying an existing backend, in an ad hoc fashion, we started from scratch and proceeded systematically. This approach proved successful in producing a high-quality codebase. We recently announced on the llvm-dev mailing list that the backend is now reaching stability and could be promoted from its current status of experimental to an official target.

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The RISC-V LLVM backend in Clang/LLVM 9.0

On Monday I proposed promoting the upstream RISC-V LLVM backend from “experimental” to “official” for the LLVM 9.0 release. Responses so far are extremely positive, and we’re working to ensure this is a smooth process. This means that from 9.0, the RISC-V backend will be built by default for LLVM, making it usable out of the box for standard LLVM/Clang builds. As well as being more convenient for end users, this also makes it significantly easier for e.

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Introducing Sam

On June 1st, Sam Elliott followed Laura and Pirmin in becoming lowRISC’s newest employee. A few weeks into his new role, he shares why he joined lowRISC and what he’s been doing since he started. +

lowRISC News

Ibex: Code with Confidence

Ibex, our small RISC-V core, is constantly changing. Roughly 50 percent of the RTL was refactored recently! We added features, tests, and cleaned the code up. We and our collaborators were able to make these changes (mostly) without breaking Ibex because we invested in testing: earlier this year we added UVM-based verification to the tree, and we run these tests after every change. We run static code analysis to catch common programming bugs.

Read More…

Six more weeks of Ibex development - what's new?

In the past months, we have invested considerable effort in improving our RISC-V core Ibex. This 2-stage, in-order, 32-bit microcontroller-class CPU core was contributed to us by ETH Zürich in December 2018, with activity really ramping up since May. Having been taped out multiple times (as zero-riscy) in a mix of academic and industry projects, it came to us as a relatively mature code base. Despite this, we have continued to invest in improving its design and maintainability.

Read More…

Ibex cleaning up

Large-scale RISC-V LLVM testing with Buildroot

A few years ago lowRISC started developing a new LLVM backend targeting RISC-V. Rather than copying and modifying an existing backend, in an ad hoc fashion, we started from scratch and proceeded systematically. This approach proved successful in producing a high-quality codebase. We recently announced on the llvm-dev mailing list that the backend is now reaching stability and could be promoted from its current status of experimental to an official target.

Read More…

The RISC-V LLVM backend in Clang/LLVM 9.0

On Monday I proposed promoting the upstream RISC-V LLVM backend from “experimental” to “official” for the LLVM 9.0 release. Responses so far are extremely positive, and we’re working to ensure this is a smooth process. This means that from 9.0, the RISC-V backend will be built by default for LLVM, making it usable out of the box for standard LLVM/Clang builds. As well as being more convenient for end users, this also makes it significantly easier for e.

Read More…

Introducing Sam

On June 1st, Sam Elliott followed Laura and Pirmin in becoming lowRISC’s newest employee. A few weeks into his new role, he shares why he joined lowRISC and what he’s been doing since he started. “I joined lowRISC CIC as a Compiler Developer, working on the RISC-V LLVM backend, and so far I’m enjoying working on the team! Prior to lowRISC, I worked as a compilers and programming languages researcher at the University of Washington, where I completed my Masters degree.

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lowRISC at Week of Open Source Hardware

Pretty much the whole team is in Zurich this week for the RISC-V Workshop and inaugural Week of Open Source Hardware, with a packed programme that got off to a start today and which runs all the way through to Friday afternoon. This morning lowRISC board member, Professor Luca Benini, gave a RISC-V Workshop keynote entitled, Energy efficient computing from Exascale to MicroWatts: The RISC-V playground. Our friends and close collaborators at PULP Platform are giving a number of talks this week and, we’re pleased to say, so are members of the lowRISC team!

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lowRISC enamel badge

An update on Ibex, our microcontroller-class CPU core

At the beginning of many chips projects, there’s a dream. Could we create a more future-proof chip by embedding an FPGA fabric into it? Could we measure glucose levels more accurately by integrating a small bio lab onto a chip? Could we more reliably recognize kittens in a set of pictures by implementing neural network inference in hardware? In implementation, this dream becomes a piece of hardware, with digital or analog logic, sensors, actuators, and much more.

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Ibex block diagram

Introducing Pirmin & Laura

Pirmin Vogel and Laura James both joined lowRISC on May 1st this year. A few weeks in to their new roles, they each share thoughts on what attracted them to work at lowRISC. Pirmin: “After having traveled around the world for 6 months, I finally started my new position as hardware/software engineer at lowRISC C.I.C. in Cambridge at the beginning of May. At lowRISC, we are working on open-source hardware/software ecosystems with a fully open-sourced, Linux-capable, RISC-V-based SoC being the ultimate goal.

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Onwards and upwards at lowRISC

If you haven’t checked it out yet, be sure to take a look at our press release and the corresponding Google blog post. This industry support and growth of our board is a huge step forwards for lowRISC. As Royal Hansen, vice president of Security, Google, said: "Google believes that open source is good for everyone. To further our commitment, we are investing both capital and engineering resources to create a sustainable open source hardware ecosystem.

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lowRISC Expands and Appoints New Members to the Board of Directors from Google and ETH Zurich

London, England - lowRISC C.I.C., the open source system on a chip (SoC) organisation, today announced that Prof. Luca Benini (ETH Zurich), Dominic Rizzo (Google) and Ron Minnich (Google) have joined its board of directors. The announcement coincides with a new phase of hiring by lowRISC with the goal of significantly increasing the size of its Cambridge-based engineering team during 2019. -lowRISC is a not-for-profit, community-driven organisation working to provide a high quality, security-enabling, open SoC base for derivative designs.

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lowRISC Board

lowRISC at the SiFive Symposium in Cambridge

Several lowRISC team members attended the SiFive Symposium in our home town of Cambridge on May 13th 2019, a lovely sunny day. -Imagination Technologies were co-hosting with SiFive, and we heard from both companies. Krste Asanovic, chairman of the board at the RISC-V Foundation, gave a great introduction to RISC-V and progress so far. Naveed Sherwani, CEO of SiFive, talked us through their silicon design platform and future services. We also heard from SecureRF and IAR Systems.

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lowRISC News

lowRISC 0-6 milestone release

The lowRISC 0.6 milestone release is now available. This release includes an updated version of the Rocket RISC-V core, a higher core clock frequency, JTAG debugging support, Ethernet improvements, and more. See the release notes, for full details. We’ve also taken the opportunity to re-organise our documentation, adding an easy to follow quick-start guide. +

lowRISC News

lowRISC at the SiFive Symposium in Cambridge

Several lowRISC team members attended the SiFive Symposium in our home town of Cambridge on May 13th 2019, a lovely sunny day. +Imagination Technologies were co-hosting with SiFive, and we heard from both companies. Krste Asanovic, chairman of the board at the RISC-V Foundation, gave a great introduction to RISC-V and progress so far. Naveed Sherwani, CEO of SiFive, talked us through their silicon design platform and future services. We also heard from SecureRF and IAR Systems.

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lowRISC 0-6 milestone release

The lowRISC 0.6 milestone release is now available. This release includes an updated version of the Rocket RISC-V core, a higher core clock frequency, JTAG debugging support, Ethernet improvements, and more. See the release notes, for full details. We’ve also taken the opportunity to re-organise our documentation, adding an easy to follow quick-start guide. Our next development focus is to add support for dropping in the Ariane RISC-V design (from ETH Zurich) as an alternative to Rocket.

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Barcelona RISC-V Workshop: Day Two

The eighth RISC-V workshop is continuing today in Barcleona. As usual, I’ll be keeping a semi-live blog of talks and announcements throughout the day. Look back here for the day one live blog. Note that slides from most presentations are now available at riscv.org. @@ -13,6 +14,5 @@ Follow here for the day two live blog. Introduction: Rick O’Connor Workshop is sold out, 498 attendees registered representing 138 companies and 35 universities. There will be 47 sessions squeezed into 12 and 24 minute increments, plus 26 poster / demo sessions.

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GSoC 2017 student report: core lockstep for minion cores

This year, as part of Google Summer of Code we had the pleasure of working with Nikitas Chronas. Alongside his degree studies, Nikitas had become involved with the Libre Space Foundation and developed a strong interest in the possibility of open source hardware in CubeSats. Fault tolerance of some sort is important for harsh environments, and Nikitas worked to add fault tolerance through the implementation of core lockstep for the PULPino-based minion core subsystem.

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Moving RISC-V LLVM forwards

A high quality, upstream RISC-V backend for LLVM is perhaps the most frequently requested missing piece of the RISC-V software ecosystem. This blog post provides an update on the rapid progress we’ve been making towards that goal, outlines next steps and upcoming events, and tries to better explain the approach that we’re taking. As always, you can track status here and find the code here. Status I’ve been able to make substantial progress since the last update.

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lowRISC tagged memory OS enablement

This summer, we were fortunate enough to have Katherine Lim join the lowRISC team at the University of Cambridge Computer Laboratory as an intern. Katherine’s focus was on operating system and software enabled for lowRISC’s tagged memory, building upon our most recent milestone release. As Katherine’s detailed write-up demonstrates, it’s been a very productive summer. -The goal of this internship was to take the lowRISC hardware release, and demonstrate kernel support and software support for the hardware tagged memory primitives.

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We're hiring! Work on making open source hardware a reality

We are looking for a talented hardware engineer to join the lowRISC team and help make our vision for an open source, secure, and flexible SoC a reality. Apply now! -lowRISC C.I.C. is a not-for-profit company that aims to demonstrate, promote and support the use of open-source hardware. The lowRISC project was established in 2014 with the aim of bringing the benefits of open-source to the hardware world. It is working to do this by producing a high quality, secure, open, and flexible System-on-Chip (SoC) platform.

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lowRISC News

Building upstream RISC-V GCC+binutils+newlib: the quick and dirty way

There are a number of available options for building a RISC-V GCC toolchain. You might use the build system from the riscv/riscv-tools repository, or investigate toolchain generators such as crosstool-ng. However in the case of riscv-tools, it’s not always clear how this corresponds to the code in the relevant upstream projects. When investigating a potential bug, you often just want to build the latest upstream code with as little fuss as possible.

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lowRISC 0-4 milestone release

The lowRISC 0.4 milestone release is now available. The various changes are best described in our accompanying documentation, but in summary this release: +

lowRISC News

We're hiring! Work on making open source hardware a reality

We are looking for a talented hardware engineer to join the lowRISC team and help make our vision for an open source, secure, and flexible SoC a reality. Apply now! +lowRISC C.I.C. is a not-for-profit company that aims to demonstrate, promote and support the use of open-source hardware. The lowRISC project was established in 2014 with the aim of bringing the benefits of open-source to the hardware world. It is working to do this by producing a high quality, secure, open, and flexible System-on-Chip (SoC) platform.

Read More…

Building upstream RISC-V GCC+binutils+newlib: the quick and dirty way

There are a number of available options for building a RISC-V GCC toolchain. You might use the build system from the riscv/riscv-tools repository, or investigate toolchain generators such as crosstool-ng. However in the case of riscv-tools, it’s not always clear how this corresponds to the code in the relevant upstream projects. When investigating a potential bug, you often just want to build the latest upstream code with as little fuss as possible.

Read More…

lowRISC 0-4 milestone release

The lowRISC 0.4 milestone release is now available. The various changes are best described in our accompanying documentation, but in summary this release: Moves forward our support for tagged memory by re-integrating the tag cache, reducing overhead with a hierarchical scheme. This will significantly reduce caches misses caused by tagged memory accesses where tags are distributed sparsely. Integrates support for specifying and configuring tag propagation and exception behaviour. A PULPino based “minion core” has been integrated, and is used to provide peripherals such as the SD card interface, keyboard, and VGA tex display (when using the Nexys4 DDR FPGA development board).

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Apply now for GSoC 2017

We are very grateful for being selected again to take part as a mentoring organisation in the Google Summer of Code, now for the third year running. If you are a student who would like to be paid to work on open source during the summer, then take a look at the lowRISC ideas list and apply. The deadline for applications is 4pm UTC on April 3rd. We’re always very interested in ideas suggested by students, and encourage you to share them on our discussion list for feedback before making a proposal.

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2017 NetFPGA Design Challenge

As most of you know, the majority of full-time development on lowRISC takes place at the University of Cambridge Computer Laboratory. However, we’re far from the only open source hardware activity at the University. Our colleagues on the NetFPGA project have an open source design challenge that many readers of this blog might be interested in. See the design challenge website, or read below for more details: We are pleased to announce the 2017 NetFPGA Design Challenge!

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lowRISC Q+A

Yesterday, lowRISC triggered a lot of discussion when someone submitted it to Hacker News. The comment thread became something of an impromptu Q+A about our project direction and status. I thought it was worth linking to it here and highlighting the discussion for a wider audience. If you have any additional questions, then feel free to comment on this blog post or else, as always, drop by our mailing list.

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Fifth RISC-V Workshop: Day Two

Today is the second day of the fifth RISC-V workshop. I’ll be keeping a semi-live blog of talks and announcements throughout the day. OpenSoC System Architect: Farzad Fatollahi-Fard Current architectures are wasteful. Only a small fraction of chip area goes to computation. For both GoblinCore and OpenHPC, ended up doing a lot of similar work to achieve only a point design. Why not make a generator to avoid repeating the same steps?

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Fifth RISC-V Workshop: Day One

The fifth RISC-V workshop is going on today and tomorrow at the Google’s Quad Campus in Mountain View. I’ll be keeping a semi-live blog of talks and announcements throughout the day. Introduction: Rick O’Connor and Dom Rizzo This workshop is yet again bigger than the last. 350+ attendees, 107 companies, 29 universities. The next workshop will be May 9th-10 in Shanghai, China. RISC-V at UC San Diego: Michael Taylor Startup software stacks today look a light like an iceberg.

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Generating a Gantt chart from HJSON input

This blog post is a slight departure from the normal topics here. Worry not, we’ll return to discussing Verilog, Chisel, and low-level software work soon. I wrote a quick script to help serve a need (producing a Gantt chart) and thought perhaps others would find it useful. There are a wide range of online services to help produce and maintain Gantt charts, but none quite offered what I was looking for.

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Example Gantt Chart

lowRISC+IMC internship: second update

This is the second update from our team of interns, comprised of four University of Cambridge undergrads. Their work is kindly sponsored by IMC Financial Markets who are also helping to advise this summer project. -At the time of our last blog post, we had just finished VGA and were working on implementing the frame buffer. Over the last 2 weeks, we have made significant progress, completing the frame buffer and starting video decode.

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Notes from the fourth RISC-V workshop

Many of the lowRISC team (Robert Mullins, Wei Song, and Alex Bradbury) have been in Boston this week for the fourth RISC-V workshop. By any measure, this has been a massive success with over 250 attendees representing 63 companies and 42 Universities. Wei presented our most recent work on integrating trace debug, which you’ll soon be able to read much more about here (it’s worth signing up to our announcement list if you want to be informed of each of our releases).

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The text content on this website is licensed under a Creative Commons Attribution 4.0 International License, except where otherwise noted. No license is granted for logos or other trademarks. Other content © lowRISC Contributors.

Privacy and cookies policy +At the time of our last blog post, we had just finished VGA and were working on implementing the frame buffer. Over the last 2 weeks, we have made significant progress, completing the frame buffer and starting video decode.

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lowRISC News

lowRISC / IMC internship week one - VGA output

Begnning on Monday, June 27th, we had a team of four University of Cambridge undergrads begin a 10 week internship working on the lowRISC project at the Computer Laboratory, kindly sponsored by IMC Financial Markets (who are also helping to advise this project). The team will be blogging regularly over the course of the summer - I’ll pass over to them to introduce themselves. +

lowRISC News

Notes from the fourth RISC-V workshop

Many of the lowRISC team (Robert Mullins, Wei Song, and Alex Bradbury) have been in Boston this week for the fourth RISC-V workshop. By any measure, this has been a massive success with over 250 attendees representing 63 companies and 42 Universities. Wei presented our most recent work on integrating trace debug, which you’ll soon be able to read much more about here (it’s worth signing up to our announcement list if you want to be informed of each of our releases).

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lowRISC / IMC internship week one - VGA output

Begnning on Monday, June 27th, we had a team of four University of Cambridge undergrads begin a 10 week internship working on the lowRISC project at the Computer Laboratory, kindly sponsored by IMC Financial Markets (who are also helping to advise this project). The team will be blogging regularly over the course of the summer - I’ll pass over to them to introduce themselves. After some initial brainstorming, we decided to aim to extend the current lowRISC SoC design to enable video output, with the final goal of playing video smoothly at a resolution of 640x480 on FPGA.

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Announcing the LibreCores design contest and ORConf 2016

Our friends and collaborators at the Free and Open Source Silicon Foundation have launched the LibreCores design contest. This is a student design contest which aims to recognise and reward contributions to the open source hardware ecosystem. The main evaluation criteria are: Openness. Your work must be published under an established Open Source license. Reusability. How easily can your work be used and modified by someone else? Is it well documented?

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lowRISC's 2016 Google Summer of Code Students

The 2016 Google Summer of Code is now underway and we’re delighted to be working with five students, covering a variety of interesting projects. They have all introduced themselves over the past few weeks on our project mailing list. Many thanks to everyone who applied, to the mentors who volunteered, and to Google for sponsoring this programme. If your application was unsuccessful, I hope you’ll try again next year. The projects for lowRISC in the 2016 GSoC are:

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Apply now to work with lowRISC in Google Summer of Code

We are very grateful to have been selected to take part as a mentoring organisation in the Google Summer of Code for the second year running. As with last year, we’re working with a number of friends from across the wider open source hardware community to act as an umbrella for a range of hardware-related projects. If you are a student who would like to be paid to work on open source during the summer, then take a look at the lowRISC ideas list and apply.

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Third RISC-V Workshop: Day Two

Today is the second day of the third RISC-V workshop. Again, I’ll be keeping a semi-live blog of talks and announcements throughout the day. See here for notes from the first day. RISC-V ASIC and FPGA implementations: Richard Herveille Look for freedom of design. Want to free migrate between FPGAs, structured ASICs, standard cell ASICs Want to make it easier to migrate FPGAs to ASICs for advantages in price, performance, power, IP protection.

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Third RISC-V Workshop: Day One

The third RISC-V workshop is going on today and tomorrow at the Oracle Conference Center, California. I’ll be keeping a semi-live blog of talks and announcements throughout the day. See here for notes from the second day. Introductions and RISC-V Foundation Overview: Rick O’Connor Save the date, the 4th RISC-V workshop will be July 12th-13th at the MIT CSAIL/Stata Center. In August 2015, articles of incorporation were filed to create a non-profit RISC-V Foundation to govern the ISA.

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Untethered lowRISC release

Over the past several months, we’ve been working to provide a standalone or ‘untethered’ SoC. Cores in the original Rocket chip rely on communicating with a companion processor via the host-target interface (HTIF) to access peripherals and I/O. This release removes this requirement, adding an I/O bus and instantiating FPGA peripherals. The accompanying tutorial, written by Wei Song, describes how to build this code release and explains the underlying structural changes.

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lowRISC at ORConf 2015

Please join us October 9th-11th in Geneva, Switzerland for ORConf 2015. The event is kindly being hosted by CERN at the IdeaSquare. Last year’s ORConf was home to the first public talk on lowRISC and we’re delighted this year it will also be hosting a series of lowRISC and RISC-V discussions, serving as a European lowRISC and RISC-V workshop. ORConf has in recent years grown to cover a range of open source hardware topics beyond the original OpenRISC focus.

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Second RISC-V Workshop: Day Two

It’s the second day of the second RISC-V workshop today in Berkeley, California. I’ll be keeping a semi-live blog of talks and announcements throughout the day. -Z-scale. Tiny 32-bit RISC-V Systems: Yunsup Lee Z-Scale is a family of tiny cores, similar in spirit to the ARM Cortex-M family. It integrates with the AHB-Lite interconnect. Contrast to Rocket (in-order cores, 64-bit, 32-bit, dual-issue options), and BOOM (a family of out-of-order cores).

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Second RISC-V Workshop: Day One

The second RISC-V workshop is going on today and tomorrow in Berkeley, California. I’ll be keeping a semi-live blog of talks and announcements throughout the day. -Introductions and welcome: Krste Asanović The beginning of Krste’s talk will be familiar for anyone who’s seen an introduction to RISC-V before. Pleasingly, there are a lot of new faces here at the workshop so the introduction of course makes a lot of sense.

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Privacy and cookies policy +Z-scale. Tiny 32-bit RISC-V Systems: Yunsup Lee Z-Scale is a family of tiny cores, similar in spirit to the ARM Cortex-M family. It integrates with the AHB-Lite interconnect. Contrast to Rocket (in-order cores, 64-bit, 32-bit, dual-issue options), and BOOM (a family of out-of-order cores).

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lowRISC News

Summer of Code students for lowRISC

lowRISC was fortunate enough to be chosen as a mentoring organisation in this year’s Google Summer of Code. The Google Summer of Code program funds students to work on open source projects over the summer. We had 52 applications across the range of project ideas we’ve been advertising. As you can see from the range of project ideas, lowRISC is taking part as an umbrella organisation, working with a number of our friends in the wider open source software and hardware community.

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lowRISC tagged memory preview release

We’re pleased to announce the first lowRISC preview release, demonstrating support for tagged memory as described in our memo. Our ambition with lowRISC is to provide an open-source System-on-Chip platform for others to build on, along with low-cost development boards featuring a reference implementation. Although there’s more work to be done on the tagged memory implementation, now seemed a good time to document what we’ve done in order for the wider community to take a look.

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