This checklist is for Hardware Stage transitions for the Pinmux peripheral. All checklist items refer to the content in the Checklist.
Type | Item | Resolution | Note/Collaterals |
---|---|---|---|
Documentation | SPEC_COMPLETE | Done | Pinmux spec |
Documentation | CSR_DEFINED | Done | |
RTL | CLKRST_CONNECTED | Done | |
RTL | IP_TOP | Done | |
RTL | IP_INSTANTIABLE | Done | |
RTL | PHYSICAL_MACROS_DEFINED_80 | Done | |
RTL | FUNC_IMPLEMENTED | Done | |
RTL | ASSERT_KNOWN_ADDED | Done | Primary I/Os are exempted from KNOWN assertions since the chip-level testbench may drive X'es onto some of these signals. |
Code Quality | LINT_SETUP | Done |
Type | Item | Resolution | Note/Collaterals |
---|---|---|---|
Documentation | NEW_FEATURES | Done | |
Documentation | BLOCK_DIAGRAM | Done | |
Documentation | DOC_INTERFACE | Done | |
Documentation | DOC_INTEGRATION_GUIDE | Waived | This checklist item has been added retrospectively. |
Documentation | MISSING_FUNC | Done | |
Documentation | FEATURE_FROZEN | Done | |
RTL | FEATURE_COMPLETE | Done | |
RTL | PORT_FROZEN | Done | |
RTL | ARCHITECTURE_FROZEN | Done | |
RTL | REVIEW_TODO | Done | |
RTL | STYLE_X | Done | |
RTL | CDC_SYNCMACRO | Done | |
Code Quality | LINT_PASS | Done | |
Code Quality | CDC_SETUP | Waived | No block-level flow available - waived to top-level signoff. |
Code Quality | RDC_SETUP | Waived | No block-level flow available - waived to top-level signoff. |
Code Quality | AREA_CHECK | Done | |
Code Quality | TIMING_CHECK | Done | |
Security | SEC_CM_DOCUMENTED | N/A |
Type | Item | Resolution | Note/Collaterals |
---|---|---|---|
Security | SEC_CM_ASSETS_LISTED | Done | |
Security | SEC_CM_IMPLEMENTED | Done | |
Security | SEC_CM_RND_CNST | N/A | |
Security | SEC_CM_NON_RESET_FLOPS | N/A | |
Security | SEC_CM_SHADOW_REGS | N/A | |
Security | SEC_CM_RTL_REVIEWED | N/A | |
Security | SEC_CM_COUNCIL_REVIEWED | N/A | This block only contains the bus-integrity CM. |
Type | Item | Resolution | Note/Collaterals |
---|---|---|---|
Documentation | NEW_FEATURES_D3 | Done | |
RTL | TODO_COMPLETE | Done | |
Code Quality | LINT_COMPLETE | Done | |
Code Quality | CDC_COMPLETE | Waived | No block-level flow available - waived to top-level signoff. |
Code Quality | RDC_COMPLETE | Waived | No block-level flow available - waived to top-level signoff. |
Review | REVIEW_RTL | Done | Note that the USB wakeup detector submodule u_usbdev_aon_wake is excluded in this review as it will be reviewed as part of the USB sign-off process. |
Review | REVIEW_DELETED_FF | Waived | No block-level flow available - waived to top-level signoff. |
Review | REVIEW_SW_CHANGE | Done | |
Review | REVIEW_SW_ERRATA | Done | |
Review | Reviewer(s) | Done | msf@ tjaychen@ chencindy@ awill@ |
Review | Signoff date | Done | 2022-08-17 |
Type | Item | Resolution | Note/Collaterals |
---|---|---|---|
Documentation | DV_DOC_DRAFT_COMPLETED | Done | |
Documentation | TESTPLAN_COMPLETED | Done | |
Testbench | TB_TOP_CREATED | Done | |
Testbench | PRELIMINARY_ASSERTION_CHECKS_ADDED | Done | |
Testbench | SIM_TB_ENV_CREATED | N/A | |
Testbench | SIM_RAL_MODEL_GEN_AUTOMATED | N/A | This block uses FPV |
Testbench | CSR_CHECK_GEN_AUTOMATED | Done | |
Testbench | TB_GEN_AUTOMATED | Done | |
Tests | SIM_SMOKE_TEST_PASSING | N/A | |
Tests | SIM_CSR_MEM_TEST_SUITE_PASSING | N/A | |
Tests | FPV_MAIN_ASSERTIONS_PROVEN | Done | |
Tool Setup | SIM_ALT_TOOL_SETUP | N/A | |
Regression | SIM_SMOKE_REGRESSION_SETUP | N/A | |
Regression | SIM_NIGHTLY_REGRESSION_SETUP | N/A | |
Regression | FPV_REGRESSION_SETUP | Done | |
Coverage | SIM_COVERAGE_MODEL_ADDED | N/A | |
Code Quality | TB_LINT_SETUP | Done | |
Integration | PRE_VERIFIED_SUB_MODULES_V1 | Waived | usbdev will be verified by a separate DV testbench. |
Review | DESIGN_SPEC_REVIEWED | Not Started | |
Review | TESTPLAN_REVIEWED | Done | |
Review | STD_TEST_CATEGORIES_PLANNED | N/A | |
Review | V2_CHECKLIST_SCOPED | Done |
Type | Item | Resolution | Note/Collaterals |
---|---|---|---|
Documentation | DESIGN_DELTAS_CAPTURED_V2 | Done | |
Documentation | DV_DOC_COMPLETED | Done | |
Testbench | FUNCTIONAL_COVERAGE_IMPLEMENTED | Done | |
Testbench | ALL_INTERFACES_EXERCISED | Done | |
Testbench | ALL_ASSERTION_CHECKS_ADDED | Done | |
Testbench | SIM_TB_ENV_COMPLETED | N/A | |
Tests | SIM_ALL_TESTS_PASSING | N/A | |
Tests | FPV_ALL_ASSERTIONS_WRITTEN | Done | |
Tests | FPV_ALL_ASSUMPTIONS_REVIEWED | Done | |
Tests | SIM_FW_SIMULATED | N/A | |
Regression | SIM_NIGHTLY_REGRESSION_V2 | N/A | |
Coverage | SIM_CODE_COVERAGE_V2 | N/A | |
Coverage | SIM_FUNCTIONAL_COVERAGE_V2 | N/A | |
Coverage | FPV_CODE_COVERAGE_V2 | Done | |
Coverage | FPV_COI_COVERAGE_V2 | Done | |
Integration | PRE_VERIFIED_SUB_MODULES_V2 | Waived | usbdev will be verified by a separate DV testbench. |
Issues | NO_HIGH_PRIORITY_ISSUES_PENDING | Done | |
Issues | ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED | Done | |
Review | DV_DOC_TESTPLAN_REVIEWED | Done | |
Review | V3_CHECKLIST_SCOPED | Done |
Type | Item | Resolution | Note/Collaterals |
---|---|---|---|
Documentation | SEC_CM_TESTPLAN_COMPLETED | Done | The testplan has been generated, but there is no DV environment to test these CMs. The CMs (bus integrity and LC gated TAP muxing/demuxing) are tested with the FPV testbench instead. |
Tests | [FPV_SEC_CM_PROVEN][] | Done | The SEC_CM behavior has been proven with formal. |
Tests | SIM_SEC_CM_VERIFIED | N/A | This module only has an FPV testbench. |
Coverage | SIM_COVERAGE_REVIEWED | N/A | This module only has an FPV testbench. |
Review | SEC_CM_DV_REVIEWED | Done |
Type | Item | Resolution | Note/Collaterals |
---|---|---|---|
Documentation | DESIGN_DELTAS_CAPTURED_V3 | Not Started | |
Tests | X_PROP_ANALYSIS_COMPLETED | Not Started | |
Tests | FPV_ASSERTIONS_PROVEN_AT_V3 | Not Started | |
Regression | SIM_NIGHTLY_REGRESSION_AT_V3 | Not Started | |
Coverage | SIM_CODE_COVERAGE_AT_100 | Not Started | |
Coverage | SIM_FUNCTIONAL_COVERAGE_AT_100 | Not Started | |
Coverage | FPV_CODE_COVERAGE_AT_100 | Not Started | |
Coverage | FPV_COI_COVERAGE_AT_100 | Not Started | |
Code Quality | ALL_TODOS_RESOLVED | Not Started | |
Code Quality | NO_TOOL_WARNINGS_THROWN | Not Started | |
Code Quality | TB_LINT_COMPLETE | Not Started | |
Integration | PRE_VERIFIED_SUB_MODULES_V3 | Not Started | |
Issues | NO_ISSUES_PENDING | Not Started | |
Review | Reviewer(s) | Not Started | |
Review | Signoff date | Not Started |