diff --git a/hw/ip/aes/rtl/aes_cipher_core.sv b/hw/ip/aes/rtl/aes_cipher_core.sv index 80b3ef17f100e..11492a211dbb9 100644 --- a/hw/ip/aes/rtl/aes_cipher_core.sv +++ b/hw/ip/aes/rtl/aes_cipher_core.sv @@ -724,7 +724,7 @@ module aes_cipher_core import aes_pkg::*; logic [(4*WidthPRDSBox)-1:0] in ); logic [3:0][(WidthPRDSBox-8)-1:0] prd_msbs; - for (int i=0; i<4; i++) begin + for (int i = 0; i < 4; i++) begin prd_msbs[i] = in[(i*WidthPRDSBox) + 8 +: (WidthPRDSBox-8)]; end return prd_msbs; @@ -738,7 +738,7 @@ module aes_cipher_core import aes_pkg::*; logic [3:0][(WidthPRDSBox-8)-1:0] prd_msbs ); logic [(4*WidthPRDSBox)-1:0] prd; - for (int i=0; i<4; i++) begin + for (int i = 0; i < 4; i++) begin prd[(i*WidthPRDSBox) +: WidthPRDSBox] = {prd_msbs[i], prd_lsbs[i]}; end return prd; diff --git a/hw/ip/aes/rtl/aes_control.sv b/hw/ip/aes/rtl/aes_control.sv index 4eb90f33c23ea..59659a2f6ba78 100644 --- a/hw/ip/aes/rtl/aes_control.sv +++ b/hw/ip/aes/rtl/aes_control.sv @@ -343,12 +343,12 @@ module aes_control import aes_pkg::*; if (idle_o) begin // Initial key and IV updates are ignored if we are not idle. - for (int s=0; s<2; s++) begin - for (int i=0; i<8; i++) begin + for (int s = 0; s < 2; s++) begin + for (int i = 0; i < 8; i++) begin key_init_we_o[s][i] = key_init_qe_i[s][i] ? SP2V_HIGH : SP2V_LOW; end end - for (int i=0; i<8; i++) begin + for (int i = 0; i < 8; i++) begin iv_we_o[i] = iv_qe[i] ? SP2V_HIGH : SP2V_LOW; end diff --git a/hw/ip/aes/rtl/aes_core.sv b/hw/ip/aes/rtl/aes_core.sv index 0939bfd4c9c55..ef27a184004d8 100644 --- a/hw/ip/aes/rtl/aes_core.sv +++ b/hw/ip/aes/rtl/aes_core.sv @@ -194,7 +194,7 @@ module aes_core //////////// always_comb begin : key_init_get - for (int i=0; i<8; i++) begin + for (int i = 0; i < 8; i++) begin key_init[0][i] = reg2hw.key_share0[i].q; key_init_qe[0][i] = reg2hw.key_share0[i].qe; key_init[1][i] = reg2hw.key_share1[i].q; @@ -203,21 +203,21 @@ module aes_core end always_comb begin : iv_get - for (int i=0; i<4; i++) begin + for (int i = 0; i < 4; i++) begin iv[i] = reg2hw.iv[i].q; iv_qe[i] = reg2hw.iv[i].qe; end end always_comb begin : data_in_get - for (int i=0; i<4; i++) begin + for (int i = 0; i < 4; i++) begin data_in[i] = reg2hw.data_in[i].q; data_in_qe[i] = reg2hw.data_in[i].qe; end end always_comb begin : data_out_get - for (int i=0; i<4; i++) begin + for (int i = 0; i < 4; i++) begin // data_out is actually hwo, but we need hrw for hwre unused_data_out_q[i] = reg2hw.data_out[i].q; data_out_re[i] = reg2hw.data_out[i].re; @@ -241,8 +241,8 @@ module aes_core if (!rst_ni) begin key_init_q <= '{default: '0}; end else begin - for (int s=0; s<2; s++) begin - for (int i=0; i<8; i++) begin + for (int s = 0; s < 2; s++) begin + for (int i = 0; i < 8; i++) begin if (key_init_we[s][i] == SP2V_HIGH) begin key_init_q[s][i] <= key_init_d[s][i]; end @@ -268,7 +268,7 @@ module aes_core if (!rst_ni) begin iv_q <= '0; end else begin - for (int i=0; i<8; i++) begin + for (int i = 0; i < 8; i++) begin if (iv_we[i] == SP2V_HIGH) begin iv_q[i] <= iv_d[i]; end @@ -593,7 +593,7 @@ module aes_core // Input data register clear always_comb begin : data_in_reg_clear - for (int i=0; i<4; i++) begin + for (int i = 0; i < 4; i++) begin hw2reg.data_in[i].d = prd_clearing_128[i*32 +: 32]; hw2reg.data_in[i].de = data_in_we; end @@ -778,20 +778,20 @@ module aes_core end always_comb begin : key_reg_put - for (int i=0; i<8; i++) begin + for (int i = 0; i < 8; i++) begin hw2reg.key_share0[i].d = key_init_q[0][i]; hw2reg.key_share1[i].d = key_init_q[1][i]; end end always_comb begin : iv_reg_put - for (int i=0; i<4; i++) begin + for (int i = 0; i < 4; i++) begin hw2reg.iv[i].d = {iv_q[2*i+1], iv_q[2*i]}; end end always_comb begin : data_out_put - for (int i=0; i<4; i++) begin + for (int i = 0; i < 4; i++) begin hw2reg.data_out[i].d = data_out_q[i]; end end diff --git a/hw/ip/aes/rtl/aes_ctr.sv b/hw/ip/aes/rtl/aes_ctr.sv index 9453c4f6ed123..d41e20947ffde 100644 --- a/hw/ip/aes/rtl/aes_ctr.sv +++ b/hw/ip/aes/rtl/aes_ctr.sv @@ -25,7 +25,7 @@ module aes_ctr import aes_pkg::*; // Reverse byte order function automatic logic [15:0][7:0] aes_rev_order_byte(logic [15:0][7:0] in); logic [15:0][7:0] out; - for (int i=0; i<16; i++) begin + for (int i = 0; i < 16; i++) begin out[i] = in[15-i]; end return out; @@ -34,7 +34,7 @@ module aes_ctr import aes_pkg::*; // Reverse sp2v order function automatic sp2v_e [7:0] aes_rev_order_sp2v(sp2v_e [7:0] in); sp2v_e [7:0] out; - for (int i=0; i<8; i++) begin + for (int i = 0; i < 8; i++) begin out[i] = in[7-i]; end return out; diff --git a/hw/ip/aes/rtl/aes_key_expand.sv b/hw/ip/aes/rtl/aes_key_expand.sv index 8ec886e742cf8..936cc3edcfc77 100644 --- a/hw/ip/aes/rtl/aes_key_expand.sv +++ b/hw/ip/aes/rtl/aes_key_expand.sv @@ -260,13 +260,13 @@ module aes_key_expand import aes_pkg::*; regular[s][0] = irregular[s] ^ key_i[s][0]; unique case (op_i) CIPH_FWD: begin - for (int i=1; i<4; i++) begin + for (int i = 1; i < 4; i++) begin regular[s][i] = regular[s][i-1] ^ key_i[s][i]; end end CIPH_INV: begin - for (int i=1; i<4; i++) begin + for (int i = 1; i < 4; i++) begin regular[s][i] = key_i[s][i-1] ^ key_i[s][i]; end end @@ -295,7 +295,7 @@ module aes_key_expand import aes_pkg::*; // Shift down two upper most words regular[s][1:0] = key_i[s][5:4]; // Generate new upper four words - for (int i=0; i<4; i++) begin + for (int i = 0; i < 4; i++) begin if ((i == 0 && rnd_type[2]) || (i == 2 && rnd_type[3])) begin regular[s][i+2] = irregular[s] ^ key_i[s][i]; @@ -311,14 +311,14 @@ module aes_key_expand import aes_pkg::*; // Shift up four lowest words regular[s][5:2] = key_i[s][3:0]; // Generate Word 44 and 45 - for (int i=0; i<2; i++) begin + for (int i = 0; i < 2; i++) begin regular[s][i] = key_i[s][3+i] ^ key_i[s][3+i+1]; end end else begin // Shift up two lowest words regular[s][5:4] = key_i[s][1:0]; // Generate new lower four words - for (int i=0; i<4; i++) begin + for (int i = 0; i < 4; i++) begin if ((i == 2 && rnd_type[1]) || (i == 0 && rnd_type[2])) begin regular[s][i] = irregular[s] ^ key_i[s][i+2]; @@ -352,7 +352,7 @@ module aes_key_expand import aes_pkg::*; regular[s][3:0] = key_i[s][7:4]; // Generate new upper half regular[s][4] = irregular[s] ^ key_i[s][0]; - for (int i=1; i<4; i++) begin + for (int i = 1; i < 4; i++) begin regular[s][i+4] = regular[s][i+4-1] ^ key_i[s][i]; end end // rnd == 0 @@ -368,7 +368,7 @@ module aes_key_expand import aes_pkg::*; regular[s][7:4] = key_i[s][3:0]; // Generate new lower half regular[s][0] = irregular[s] ^ key_i[s][4]; - for (int i=0; i<3; i++) begin + for (int i = 0; i < 3; i++) begin regular[s][i+1] = key_i[s][4+i] ^ key_i[s][4+i+1]; end end // rnd == 0 diff --git a/hw/ip/aes/rtl/aes_pkg.sv b/hw/ip/aes/rtl/aes_pkg.sv index 0ee8a844d503f..15be9fe754f3e 100644 --- a/hw/ip/aes/rtl/aes_pkg.sv +++ b/hw/ip/aes/rtl/aes_pkg.sv @@ -353,8 +353,8 @@ endfunction function automatic logic [3:0][3:0][7:0] aes_transpose(logic [3:0][3:0][7:0] in); logic [3:0][3:0][7:0] transpose; transpose = '0; - for (int j=0; j<4; j++) begin - for (int i=0; i<4; i++) begin + for (int j = 0; j < 4; j++) begin + for (int i = 0; i < 4; i++) begin transpose[i][j] = in[j][i]; end end @@ -364,7 +364,7 @@ endfunction // Extract single column from state matrix function automatic logic [3:0][7:0] aes_col_get(logic [3:0][3:0][7:0] in, logic [1:0] idx); logic [3:0][7:0] out; - for (int i=0; i<4; i++) begin + for (int i = 0; i < 4; i++) begin out[i] = in[i][idx]; end return out; @@ -377,8 +377,8 @@ function automatic logic [7:0] aes_mvm( ); logic [7:0] vec_c; vec_c = '0; - for (int i=0; i<8; i++) begin - for (int j=0; j<8; j++) begin + for (int i = 0; i < 8; i++) begin + for (int j = 0; j < 8; j++) begin vec_c[i] = vec_c[i] ^ (mat_a[j][i] & vec_b[7-j]); end end @@ -416,7 +416,7 @@ function automatic logic [3:0][7:0] aes_prd_get_lsbs( logic [(4*WidthPRDSBox)-1:0] in ); logic [3:0][7:0] prd_lsbs; - for (int i=0; i<4; i++) begin + for (int i = 0; i < 4; i++) begin prd_lsbs[i] = in[i*WidthPRDSBox +: 8]; end return prd_lsbs;