diff --git a/hw/dv/verilator/cpp/scrambled_ecc32_mem_area.cc b/hw/dv/verilator/cpp/scrambled_ecc32_mem_area.cc index c67a92917b9cd..5c20fcda30e38 100644 --- a/hw/dv/verilator/cpp/scrambled_ecc32_mem_area.cc +++ b/hw/dv/verilator/cpp/scrambled_ecc32_mem_area.cc @@ -117,10 +117,10 @@ std::vector ScrambledEcc32MemArea::GetScrambleNonce() const { ScrambledEcc32MemArea::ScrambledEcc32MemArea(const std::string &scope, uint32_t size, uint32_t width_32, bool repeat_keystream) - : Ecc32MemArea( - SVScoped::join_sv_scopes( - scope, "u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic"), - size, width_32), + : Ecc32MemArea(SVScoped::join_sv_scopes(scope, + "u_prim_ram_1p_adv.gen_ram_inst[0]." + "u_mem.gen_generic.u_impl_generic"), + size, width_32), scr_scope_(scope) { addr_width_ = vbits(size); repeat_keystream_ = repeat_keystream; diff --git a/hw/ip/otbn/dv/uvm/tb.sv b/hw/ip/otbn/dv/uvm/tb.sv index 80999b90d5d03..2ab78d91d48c1 100644 --- a/hw/ip/otbn/dv/uvm/tb.sv +++ b/hw/ip/otbn/dv/uvm/tb.sv @@ -345,7 +345,7 @@ module tb; // // Note that n_bits is the number of bits in the memory, including ECC check bits. imem_util = new(.name ("imem_util"), - .path ({"tb.dut.u_imem.u_prim_ram_1p_adv.", + .path ({"tb.dut.u_imem.u_prim_ram_1p_adv.gen_ram_inst[0].", "u_mem.gen_generic.u_impl_generic.mem"}), .depth (ImemSizeByte / 4), .n_bits (ImemSizeByte / 4 * 39), @@ -353,7 +353,7 @@ module tb; // DMEM is twice as big as the bus-accessible part dmem_util = new(.name ("dmem_util"), - .path ({"tb.dut.u_dmem.u_prim_ram_1p_adv.", + .path ({"tb.dut.u_dmem.u_prim_ram_1p_adv.gen_ram_inst[0].", "u_mem.gen_generic.u_impl_generic.mem"}), .depth (DmemSizeByte / 32), .n_bits (DmemSizeByte / 32 * 312), diff --git a/hw/ip/otbn/dv/verilator/otbn_top_sim.sv b/hw/ip/otbn/dv/verilator/otbn_top_sim.sv index 7fe7eb5bfc966..ea40156dca11b 100644 --- a/hw/ip/otbn/dv/verilator/otbn_top_sim.sv +++ b/hw/ip/otbn/dv/verilator/otbn_top_sim.sv @@ -252,6 +252,7 @@ module otbn_top_sim ( prim_ram_1p_scr #( .Width ( ExtWLEN ), .Depth ( DmemSizeWords ), + .InstDepth ( DmemSizeWords ), .DataBitsPerMask ( 39 ), .EnableParity ( 0 ), .ReplicateKeyStream ( 1 ) @@ -299,6 +300,7 @@ module otbn_top_sim ( prim_ram_1p_scr #( .Width ( 39 ), .Depth ( ImemSizeWords ), + .InstDepth ( ImemSizeWords ), .DataBitsPerMask ( 39 ), .EnableParity ( 0 ) ) u_imem ( diff --git a/hw/ip/otbn/rtl/otbn.sv b/hw/ip/otbn/rtl/otbn.sv index b57b860cbae7c..5214121f820b9 100644 --- a/hw/ip/otbn/rtl/otbn.sv +++ b/hw/ip/otbn/rtl/otbn.sv @@ -336,6 +336,7 @@ module otbn prim_ram_1p_scr #( .Width (39), .Depth (ImemSizeWords), + .InstDepth (ImemSizeWords), .DataBitsPerMask(39), .EnableParity (0) ) u_imem ( @@ -551,6 +552,7 @@ module otbn prim_ram_1p_scr #( .Width (ExtWLEN), .Depth (DmemSizeWords), + .InstDepth (DmemSizeWords), .DataBitsPerMask (39), .EnableParity (0), .ReplicateKeyStream(1) diff --git a/hw/ip/otp_ctrl/dv/tb.sv b/hw/ip/otp_ctrl/dv/tb.sv index e1b2664699ee9..1daafcc30e559 100644 --- a/hw/ip/otp_ctrl/dv/tb.sv +++ b/hw/ip/otp_ctrl/dv/tb.sv @@ -180,7 +180,7 @@ module tb; if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_impl_generic `define MEM_MODULE_PATH \ - tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv + tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv.gen_ram_inst[0] `define MEM_ARRAY_PATH \ `MEM_MODULE_PATH.u_mem.gen_generic.u_impl_generic.mem diff --git a/hw/ip/prim/rtl/prim_ram_1p_adv.sv b/hw/ip/prim/rtl/prim_ram_1p_adv.sv index 60ed16b995f66..64a3b50ba69af 100644 --- a/hw/ip/prim/rtl/prim_ram_1p_adv.sv +++ b/hw/ip/prim/rtl/prim_ram_1p_adv.sv @@ -17,6 +17,9 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #( parameter int Depth = 512, + // Setting InstDepth to a smaller value than Depth enables RAM tiling. RAM is tiled to + // ceil(Depth/InstDepth) prim_ram_1p instances, each InstDepth deep. + parameter int InstDepth = Depth, parameter int Width = 32, parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask parameter MemInitFile = "", // VMEM file to initialize the memory with @@ -32,26 +35,29 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #( // since this results in a more compact and faster implementation. parameter bit HammingECC = 0, - localparam int Aw = prim_util_pkg::vbits(Depth) + localparam int Aw = prim_util_pkg::vbits(Depth), + // Compute RAM tiling + localparam int NumRamInst = int'($ceil(Depth / real'(InstDepth))), + localparam int InstAw = prim_util_pkg::vbits(InstDepth) ) ( input clk_i, input rst_ni, - input req_i, - input write_i, - input [Aw-1:0] addr_i, - input [Width-1:0] wdata_i, - input [Width-1:0] wmask_i, - output logic [Width-1:0] rdata_o, - output logic rvalid_o, // read response (rdata_o) is valid - output logic [1:0] rerror_o, // Bit1: Uncorrectable, Bit0: Correctable + input req_i, + input write_i, + input [Aw-1:0] addr_i, + input [Width-1:0] wdata_i, + input [Width-1:0] wmask_i, + output logic [Width-1:0] rdata_o, + output logic rvalid_o, // read response (rdata_o) is valid + output logic [1:0] rerror_o, // Bit1: Uncorrectable, Bit0: Correctable // config - input ram_1p_cfg_t cfg_i, - output ram_1p_cfg_rsp_t cfg_rsp_o, + input ram_1p_cfg_t [NumRamInst-1:0] cfg_i, + output ram_1p_cfg_rsp_t [NumRamInst-1:0] cfg_rsp_o, // When detecting multi-bit encoding errors, raise alert. - output logic alert_o + output logic alert_o ); import prim_mubi_pkg::mubi4_t; @@ -59,6 +65,7 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #( import prim_mubi_pkg::mubi4_bool_to_mubi; import prim_mubi_pkg::mubi4_test_invalid; import prim_mubi_pkg::mubi4_test_true_loose; + import prim_mubi_pkg::mubi4_test_true_strict; import prim_mubi_pkg::MuBi4True; import prim_mubi_pkg::MuBi4False; import prim_mubi_pkg::MuBi4Width; @@ -103,25 +110,80 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #( assign req_q_b = mubi4_test_true_loose(req_q); assign write_q_b = mubi4_test_true_loose(write_q); - prim_ram_1p #( - .MemInitFile (MemInitFile), - - .Width (TotalWidth), - .Depth (Depth), - .DataBitsPerMask (LocalDataBitsPerMask) - ) u_mem ( - .clk_i, - .rst_ni, - - .req_i (req_q_b), - .write_i (write_q_b), - .addr_i (addr_q), - .wdata_i (wdata_q), - .wmask_i (wmask_q), - .rdata_o (rdata_sram), - .cfg_i, - .cfg_rsp_o - ); + logic [NumRamInst-1:0] inst_req_d, inst_req_q, rvalid_inst; + logic [InstAw-1:0] inst_addr; + logic [NumRamInst-1:0] [Width-1:0] inst_rdata; + + // The lower InstAw bits of the address are used to address within one RAM primitive + assign inst_addr = addr_q[InstAw-1:0]; + + // The upper bits Aw-1:InstAw of the address select which RAM instance is selected. A special case + // is needed when no tiling is performed and only a single RAM macro is instantiated. Here, we + // can directly use the request signal and no demuxing is needed. + if (NumRamInst == 1) begin : gen_single_inst_req + assign inst_req_d[0] = req_q_b; + end else begin : gen_multi_inst_req + always_comb begin + inst_req_d = '0; + + for (int i = 0; i < NumRamInst; i++) begin + if (req_q_b && (i == addr_q[Aw-1:InstAw])) begin + inst_req_d[i] = 1'b1; + end + end + end + end + + // Flop the instance request signal to know to know which + // tile to select for read data on the next cycle + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + inst_req_q <= '0; + end else begin + inst_req_q <= inst_req_d; + end + end + + // Ensure that only one RAM instance gets activated + `ASSERT(OneHotInstReq_A, $onehot0(inst_req_d)) + + for (genvar i = 0; i < NumRamInst; i++) begin : gen_ram_inst + prim_ram_1p #( + .MemInitFile (MemInitFile), + + .Width (TotalWidth), + .Depth (InstDepth), + .DataBitsPerMask (LocalDataBitsPerMask) + ) u_mem ( + .clk_i, + .rst_ni, + + .req_i (inst_req_d[i]), + .write_i (write_q_b), + .addr_i (inst_addr), + .wdata_i (wdata_q), + .wmask_i (wmask_q), + .rdata_o (inst_rdata[i]), + .cfg_i (cfg_i[i]), + .cfg_rsp_o (cfg_rsp_o[i]) + ); + end + + // Mux output data + always_comb begin + rdata_sram = '0; + + for (int i = 0; i < NumRamInst; i++) begin + // Determine which RAM tile we accessed based on the floped inst_req signal and we really + // got an rvalid. This determines if we mux the output data of that particular RAM tile. + rvalid_inst[i] = mubi4_test_true_strict( + mubi4_and_hi(mubi4_bool_to_mubi(inst_req_q[i]), rvalid_sram_q)); + + if(rvalid_inst[i]) begin + rdata_sram = inst_rdata[i]; + end + end + end assign rvalid_sram_d = mubi4_and_hi(req_q, mubi4_t'(~write_q)); diff --git a/hw/ip/prim/rtl/prim_ram_1p_scr.sv b/hw/ip/prim/rtl/prim_ram_1p_scr.sv index 554c99b9d9886..a229a1ae74e3b 100644 --- a/hw/ip/prim/rtl/prim_ram_1p_scr.sv +++ b/hw/ip/prim/rtl/prim_ram_1p_scr.sv @@ -25,6 +25,7 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #( parameter int Depth = 16*1024, // Needs to be a power of 2 if NumAddrScrRounds > 0. + parameter int InstDepth = Depth, parameter int Width = 32, // Needs to be byte aligned if byte parity is enabled. parameter int DataBitsPerMask = 8, // Needs to be set to 8 in case of byte parity. parameter bit EnableParity = 1, // Enable byte parity. @@ -58,41 +59,43 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #( // use the same key, but they use a different IV localparam int DataKeyWidth = 128, // Each 64 bit scrambling primitive requires a 64bit IV - localparam int NonceWidth = 64 * NumParScr + localparam int NonceWidth = 64 * NumParScr, + // Compute RAM tiling + localparam int NumRamInst = int'($ceil(Depth / real'(InstDepth))) ) ( - input clk_i, - input rst_ni, + input clk_i, + input rst_ni, // Key interface. Memory requests will not be granted if key_valid is set to 0. - input key_valid_i, - input [DataKeyWidth-1:0] key_i, - input [NonceWidth-1:0] nonce_i, + input key_valid_i, + input [DataKeyWidth-1:0] key_i, + input [NonceWidth-1:0] nonce_i, // Interface to TL-UL SRAM adapter - input req_i, - output logic gnt_o, - input write_i, - input [AddrWidth-1:0] addr_i, - input [Width-1:0] wdata_i, - input [Width-1:0] wmask_i, // Needs to be byte-aligned for parity + input req_i, + output logic gnt_o, + input write_i, + input [AddrWidth-1:0] addr_i, + input [Width-1:0] wdata_i, + input [Width-1:0] wmask_i, // Needs to be byte-aligned for parity // On integrity errors, the primitive surpresses any real transaction to the memory. - input intg_error_i, - output logic [Width-1:0] rdata_o, - output logic rvalid_o, // Read response (rdata_o) is valid - output logic [1:0] rerror_o, // Bit1: Uncorrectable, Bit0: Correctable - output logic [31:0] raddr_o, // Read address for error reporting. + input intg_error_i, + output logic [Width-1:0] rdata_o, + output logic rvalid_o, // Read response (rdata_o) is valid + output logic [1:0] rerror_o, // Bit1: Uncorrectable, Bit0: Correctable + output logic [31:0] raddr_o, // Read address for error reporting. // config - input ram_1p_cfg_t cfg_i, - output ram_1p_cfg_rsp_t cfg_rsp_o, + input ram_1p_cfg_t [NumRamInst-1:0] cfg_i, + output ram_1p_cfg_rsp_t [NumRamInst-1:0] cfg_rsp_o, // Write currently pending inside this module. - output logic wr_collision_o, - output logic write_pending_o, + output logic wr_collision_o, + output logic write_pending_o, // When detecting multi-bit encoding errors, raise alert. - output logic alert_o + output logic alert_o ); import prim_mubi_pkg::mubi4_t; @@ -483,6 +486,7 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #( prim_ram_1p_adv #( .Depth(Depth), + .InstDepth(InstDepth), .Width(Width), .DataBitsPerMask(DataBitsPerMask), .EnableECC(1'b0), diff --git a/hw/ip/sram_ctrl/data/sram_ctrl.hjson b/hw/ip/sram_ctrl/data/sram_ctrl.hjson index 38f64c16e1455..9ff904dc01cbc 100644 --- a/hw/ip/sram_ctrl/data/sram_ctrl.hjson +++ b/hw/ip/sram_ctrl/data/sram_ctrl.hjson @@ -79,6 +79,20 @@ type: "int", default: "0x1000" }, + { name: "InstSize", + desc: "Memory size of a single RAM tile (in bytes).", + type: "int", + default: "4096" + local: "false" + expose: "true" + }, + { name: "NumRamInst", + desc: "Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) .", + type: "int", + default: "1" + local: "false" + expose: "true" + }, { name: "InstrExec", desc: "Support execution from SRAM", type: "bit", @@ -155,6 +169,7 @@ type: "uni" name: "cfg" act: "rcv" + width: "NumRamInst", default: "'0" package: "prim_ram_1p_pkg" }, @@ -162,6 +177,7 @@ type: "uni" name: "cfg_rsp" act: "req" + width: "NumRamInst", default: "'0" package: "prim_ram_1p_pkg" }, diff --git a/hw/ip/sram_ctrl/doc/interfaces.md b/hw/ip/sram_ctrl/doc/interfaces.md index 7d1fd085de785..fedbd0898cc04 100644 --- a/hw/ip/sram_ctrl/doc/interfaces.md +++ b/hw/ip/sram_ctrl/doc/interfaces.md @@ -27,16 +27,16 @@ Referring to the [Comportable guideline for peripheral device functionality](htt ## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) -| Port Name | Package::Struct | Type | Act | Width | Description | -|:-------------------|:--------------------------------|:--------|:------|--------:|:--------------| -| sram_otp_key | otp_ctrl_pkg::sram_otp_key | req_rsp | req | 1 | | -| cfg | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | | -| cfg_rsp | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | 1 | | -| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| otp_en_sram_ifetch | prim_mubi_pkg::mubi8 | uni | rcv | 1 | | -| regs_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | -| ram_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | +| Port Name | Package::Struct | Type | Act | Width | Description | +|:-------------------|:--------------------------------|:--------|:------|:-----------|:--------------| +| sram_otp_key | otp_ctrl_pkg::sram_otp_key | req_rsp | req | 1 | | +| cfg | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | NumRamInst | | +| cfg_rsp | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | NumRamInst | | +| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| otp_en_sram_ifetch | prim_mubi_pkg::mubi8 | uni | rcv | 1 | | +| regs_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | +| ram_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | ## Security Alerts diff --git a/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_ram_cfg_vseq.sv b/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_ram_cfg_vseq.sv index d6dd8d934e55f..760d31737a434 100644 --- a/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_ram_cfg_vseq.sv +++ b/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_ram_cfg_vseq.sv @@ -11,8 +11,8 @@ class sram_ctrl_ram_cfg_vseq extends sram_ctrl_base_vseq; virtual task body(); prim_ram_1p_pkg::ram_1p_cfg_t src_ram_cfg, dst_ram_cfg; string src_path = "tb.dut.cfg_i"; - string dst_path = - "tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.cfg_i"; + string dst_path = {"tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].", + "u_mem.gen_generic.u_impl_generic.cfg_i"}; repeat (100) begin `DV_CHECK_STD_RANDOMIZE_FATAL(src_ram_cfg) diff --git a/hw/ip/sram_ctrl/dv/tb.sv b/hw/ip/sram_ctrl/dv/tb.sv index b9c596dbd7b40..b71eabbe66109 100644 --- a/hw/ip/sram_ctrl/dv/tb.sv +++ b/hw/ip/sram_ctrl/dv/tb.sv @@ -104,7 +104,7 @@ module tb; // Instantitate the memory backdoor util instance. `define SRAM_CTRL_MEM_HIER \ - tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic.mem + tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.gen_generic.u_impl_generic.mem initial begin mem_bkdr_util m_mem_bkdr_util; diff --git a/hw/ip/sram_ctrl/rtl/sram_ctrl.sv b/hw/ip/sram_ctrl/rtl/sram_ctrl.sv index 3bb8ead518492..6e128634c0397 100644 --- a/hw/ip/sram_ctrl/rtl/sram_ctrl.sv +++ b/hw/ip/sram_ctrl/rtl/sram_ctrl.sv @@ -12,7 +12,9 @@ module sram_ctrl import sram_ctrl_reg_pkg::*; #( // Number of words stored in the SRAM. - parameter int MemSizeRam = 32'h1000, + parameter int MemSizeRam = 32'h1000, + parameter int InstSize = MemSizeRam, + parameter int NumRamInst = 1, // Enable asynchronous transitions on alerts. parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, // Enables the execute from SRAM feature. @@ -23,41 +25,41 @@ module sram_ctrl // Setting this to 3 lowers this to approximately 7 effective rounds. parameter int NumPrinceRoundsHalf = 3, // Random netlist constants - parameter otp_ctrl_pkg::sram_key_t RndCnstSramKey = RndCnstSramKeyDefault, - parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramNonce = RndCnstSramNonceDefault, - parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, - parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault + parameter otp_ctrl_pkg::sram_key_t RndCnstSramKey = RndCnstSramKeyDefault, + parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramNonce = RndCnstSramNonceDefault, + parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, + parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault ) ( // SRAM Clock - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // OTP Clock (for key interface) - input logic clk_otp_i, - input logic rst_otp_ni, + input logic clk_otp_i, + input logic rst_otp_ni, // Bus Interface (device) for SRAM - input tlul_pkg::tl_h2d_t ram_tl_i, - output tlul_pkg::tl_d2h_t ram_tl_o, + input tlul_pkg::tl_h2d_t ram_tl_i, + output tlul_pkg::tl_d2h_t ram_tl_o, // Bus Interface (device) for CSRs - input tlul_pkg::tl_h2d_t regs_tl_i, - output tlul_pkg::tl_d2h_t regs_tl_o, + input tlul_pkg::tl_h2d_t regs_tl_i, + output tlul_pkg::tl_d2h_t regs_tl_o, // Alert outputs. - input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, - output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, // Life-cycle escalation input (scraps the scrambling keys) // SEC_CM: LC_ESCALATE_EN.INTERSIG.MUBI - input lc_ctrl_pkg::lc_tx_t lc_escalate_en_i, + input lc_ctrl_pkg::lc_tx_t lc_escalate_en_i, // SEC_CM: LC_HW_DEBUG_EN.INTERSIG.MUBI - input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, + input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, // Otp configuration for sram execution // SEC_CM: EXEC.INTERSIG.MUBI - input prim_mubi_pkg::mubi8_t otp_en_sram_ifetch_i, + input prim_mubi_pkg::mubi8_t otp_en_sram_ifetch_i, // Key request to OTP (running on clk_fixed) // SEC_CM: SCRAMBLE.KEY.SIDELOAD - output otp_ctrl_pkg::sram_otp_key_req_t sram_otp_key_o, - input otp_ctrl_pkg::sram_otp_key_rsp_t sram_otp_key_i, + output otp_ctrl_pkg::sram_otp_key_req_t sram_otp_key_o, + input otp_ctrl_pkg::sram_otp_key_rsp_t sram_otp_key_i, // config - input prim_ram_1p_pkg::ram_1p_cfg_t cfg_i, - output prim_ram_1p_pkg::ram_1p_cfg_rsp_t cfg_rsp_o + input prim_ram_1p_pkg::ram_1p_cfg_t [NumRamInst-1:0] cfg_i, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [NumRamInst-1:0] cfg_rsp_o ); import lc_ctrl_pkg::lc_tx_t; @@ -74,8 +76,11 @@ module sram_ctrl // This is later on pruned to the correct width at the SRAM wrapper interface. parameter int unsigned Depth = MemSizeRam >> 2; + parameter int unsigned InstDepth = InstSize >> 2; parameter int unsigned AddrWidth = prim_util_pkg::vbits(Depth); + `ASSERT_INIT(NumRamInstSameAsComputed_A, NumRamInst == int'($ceil(MemSizeRam / real'(InstSize)))) + `ASSERT_INIT(NonceWidthsLessThanSource_A, NonceWidth + LfsrWidth <= otp_ctrl_pkg::SramNonceWidth) @@ -542,6 +547,7 @@ module sram_ctrl prim_ram_1p_scr #( .Width(DataWidth), .Depth(Depth), + .InstDepth(InstDepth), .EnableParity(0), .DataBitsPerMask(DataWidth), .NumPrinceRoundsHalf(NumPrinceRoundsHalf) diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index 83d4ad5447791..d7c77e51d2a70 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -4067,6 +4067,24 @@ name_top: MemSizeSramCtrlRetAonRam default: 4096 } + { + name: InstSize + desc: Memory size of a single RAM tile (in bytes). + type: int + default: "4096" + local: "false" + expose: "true" + name_top: SramCtrlRetAonInstSize + } + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + type: int + default: 1 + local: "false" + expose: "true" + name_top: SramCtrlRetAonNumRamInst + } { name: InstrExec desc: Support execution from SRAM @@ -4106,7 +4124,17 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } default: "'0" inst_name: sram_ctrl_ret_aon top_signame: ast_ram_1p_cfg @@ -4118,7 +4146,17 @@ package: prim_ram_1p_pkg type: uni act: req - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } default: "'0" inst_name: sram_ctrl_ret_aon external: true @@ -6265,6 +6303,24 @@ name_top: MemSizeSramCtrlMainRam default: 65536 } + { + name: InstSize + desc: Memory size of a single RAM tile (in bytes). + type: int + default: "4096" + local: "false" + expose: "true" + name_top: SramCtrlMainInstSize + } + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + type: int + default: 1 + local: "false" + expose: "true" + name_top: SramCtrlMainNumRamInst + } { name: InstrExec desc: Support execution from SRAM @@ -6304,7 +6360,17 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } default: "'0" inst_name: sram_ctrl_main top_signame: ast_ram_1p_cfg @@ -6316,7 +6382,17 @@ package: prim_ram_1p_pkg type: uni act: req - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } default: "'0" inst_name: sram_ctrl_main external: true @@ -6496,6 +6572,24 @@ name_top: MemSizeSramCtrlMboxRam default: 4096 } + { + name: InstSize + desc: Memory size of a single RAM tile (in bytes). + type: int + default: "4096" + local: "false" + expose: "true" + name_top: SramCtrlMboxInstSize + } + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + type: int + default: 1 + local: "false" + expose: "true" + name_top: SramCtrlMboxNumRamInst + } { name: InstrExec desc: Support execution from SRAM @@ -6535,7 +6629,17 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMboxNumRamInst + } default: "'0" inst_name: sram_ctrl_mbox top_signame: ast_ram_1p_cfg @@ -6547,7 +6651,17 @@ package: prim_ram_1p_pkg type: uni act: req - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMboxNumRamInst + } default: "'0" inst_name: sram_ctrl_mbox external: true @@ -20579,7 +20693,17 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } default: "'0" inst_name: sram_ctrl_ret_aon top_signame: ast_ram_1p_cfg @@ -20591,7 +20715,17 @@ package: prim_ram_1p_pkg type: uni act: req - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } default: "'0" inst_name: sram_ctrl_ret_aon external: true @@ -21674,7 +21808,17 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } default: "'0" inst_name: sram_ctrl_main top_signame: ast_ram_1p_cfg @@ -21686,7 +21830,17 @@ package: prim_ram_1p_pkg type: uni act: req - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } default: "'0" inst_name: sram_ctrl_main external: true @@ -21774,7 +21928,17 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMboxNumRamInst + } default: "'0" inst_name: sram_ctrl_mbox top_signame: ast_ram_1p_cfg @@ -21786,7 +21950,17 @@ package: prim_ram_1p_pkg type: uni act: req - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMboxNumRamInst + } default: "'0" inst_name: sram_ctrl_mbox external: true @@ -24727,7 +24901,17 @@ package: prim_ram_1p_pkg struct: ram_1p_cfg_rsp signame: sram_ctrl_ret_aon_ram_1p_cfg_rsp_o - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } type: uni default: "'0" direction: out @@ -24739,7 +24923,17 @@ package: prim_ram_1p_pkg struct: ram_1p_cfg_rsp signame: sram_ctrl_main_ram_1p_cfg_rsp_o - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } type: uni default: "'0" direction: out @@ -24751,7 +24945,17 @@ package: prim_ram_1p_pkg struct: ram_1p_cfg_rsp signame: sram_ctrl_mbox_ram_1p_cfg_rsp_o - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMboxNumRamInst + } type: uni default: "'0" direction: out diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv index 2b4437360a483..9dd8dcc8c3b1c 100644 --- a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv @@ -47,6 +47,8 @@ module top_darjeeling #( // parameters for sensor_ctrl // parameters for soc_proxy // parameters for sram_ctrl_ret_aon + parameter int SramCtrlRetAonInstSize = 4096, + parameter int SramCtrlRetAonNumRamInst = 1, parameter bit SramCtrlRetAonInstrExec = 0, parameter int SramCtrlRetAonNumPrinceRoundsHalf = 3, // parameters for rv_dm @@ -84,9 +86,13 @@ module top_darjeeling #( // parameters for edn0 // parameters for edn1 // parameters for sram_ctrl_main + parameter int SramCtrlMainInstSize = 4096, + parameter int SramCtrlMainNumRamInst = 1, parameter bit SramCtrlMainInstrExec = 1, parameter int SramCtrlMainNumPrinceRoundsHalf = 3, // parameters for sram_ctrl_mbox + parameter int SramCtrlMboxInstSize = 4096, + parameter int SramCtrlMboxNumRamInst = 1, parameter bit SramCtrlMboxInstrExec = 0, parameter int SramCtrlMboxNumPrinceRoundsHalf = 3, // parameters for rom_ctrl0 @@ -166,9 +172,9 @@ module top_darjeeling #( input prim_ram_2p_pkg::ram_2p_cfg_t spi_ram_2p_cfg_i, input prim_rom_pkg::rom_cfg_t rom_cfg_i, output prim_ram_1p_pkg::ram_1p_cfg_rsp_t i2c_ram_1p_cfg_rsp_o, - output prim_ram_1p_pkg::ram_1p_cfg_rsp_t sram_ctrl_ret_aon_ram_1p_cfg_rsp_o, - output prim_ram_1p_pkg::ram_1p_cfg_rsp_t sram_ctrl_main_ram_1p_cfg_rsp_o, - output prim_ram_1p_pkg::ram_1p_cfg_rsp_t sram_ctrl_mbox_ram_1p_cfg_rsp_o, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [SramCtrlRetAonNumRamInst-1:0] sram_ctrl_ret_aon_ram_1p_cfg_rsp_o, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [SramCtrlMainNumRamInst-1:0] sram_ctrl_main_ram_1p_cfg_rsp_o, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [SramCtrlMboxNumRamInst-1:0] sram_ctrl_mbox_ram_1p_cfg_rsp_o, output prim_ram_1p_pkg::ram_1p_cfg_rsp_t otbn_imem_ram_1p_cfg_rsp_o, output prim_ram_1p_pkg::ram_1p_cfg_rsp_t otbn_dmem_ram_1p_cfg_rsp_o, output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [RvCoreIbexICacheNWays-1:0] rv_core_ibex_icache_tag_ram_1p_cfg_rsp_o, @@ -1655,6 +1661,8 @@ module top_darjeeling #( .RndCnstLfsrSeed(RndCnstSramCtrlRetAonLfsrSeed), .RndCnstLfsrPerm(RndCnstSramCtrlRetAonLfsrPerm), .MemSizeRam(4096), + .InstSize(SramCtrlRetAonInstSize), + .NumRamInst(SramCtrlRetAonNumRamInst), .InstrExec(SramCtrlRetAonInstrExec), .NumPrinceRoundsHalf(SramCtrlRetAonNumPrinceRoundsHalf) ) u_sram_ctrl_ret_aon ( @@ -2020,6 +2028,8 @@ module top_darjeeling #( .RndCnstLfsrSeed(RndCnstSramCtrlMainLfsrSeed), .RndCnstLfsrPerm(RndCnstSramCtrlMainLfsrPerm), .MemSizeRam(65536), + .InstSize(SramCtrlMainInstSize), + .NumRamInst(SramCtrlMainNumRamInst), .InstrExec(SramCtrlMainInstrExec), .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf) ) u_sram_ctrl_main ( @@ -2053,6 +2063,8 @@ module top_darjeeling #( .RndCnstLfsrSeed(RndCnstSramCtrlMboxLfsrSeed), .RndCnstLfsrPerm(RndCnstSramCtrlMboxLfsrPerm), .MemSizeRam(4096), + .InstSize(SramCtrlMboxInstSize), + .NumRamInst(SramCtrlMboxNumRamInst), .InstrExec(SramCtrlMboxInstrExec), .NumPrinceRoundsHalf(SramCtrlMboxNumPrinceRoundsHalf) ) u_sram_ctrl_mbox ( diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 70590f4395ea7..1da912571ac7b 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -5149,6 +5149,7 @@ param_decl: { InstrExec: "0" + InstSize: "4096" } base_addrs: { @@ -5227,6 +5228,24 @@ name_top: MemSizeSramCtrlRetAonRam default: 4096 } + { + name: InstSize + desc: Memory size of a single RAM tile (in bytes). + type: int + default: "4096" + local: "false" + expose: "true" + name_top: SramCtrlRetAonInstSize + } + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + type: int + default: 1 + local: "false" + expose: "true" + name_top: SramCtrlRetAonNumRamInst + } { name: InstrExec desc: Support execution from SRAM @@ -5266,10 +5285,22 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } default: "'0" inst_name: sram_ctrl_ret_aon - top_signame: ast_ram_1p_cfg + external: true + top_signame: sram_ctrl_ret_aon_cfg + conn_type: false index: -1 } { @@ -5278,7 +5309,17 @@ package: prim_ram_1p_pkg type: uni act: req - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } default: "'0" inst_name: sram_ctrl_ret_aon index: -1 @@ -8003,6 +8044,7 @@ { InstrExec: "1" NumPrinceRoundsHalf: "2" + InstSize: "131072" } base_addrs: { @@ -8085,6 +8127,24 @@ name_top: MemSizeSramCtrlMainRam default: 131072 } + { + name: InstSize + desc: Memory size of a single RAM tile (in bytes). + type: int + default: "131072" + local: "false" + expose: "true" + name_top: SramCtrlMainInstSize + } + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + type: int + default: 1 + local: "false" + expose: "true" + name_top: SramCtrlMainNumRamInst + } { name: InstrExec desc: Support execution from SRAM @@ -8124,10 +8184,22 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } default: "'0" inst_name: sram_ctrl_main - top_signame: ast_ram_1p_cfg + external: true + top_signame: sram_ctrl_main_cfg + conn_type: false index: -1 } { @@ -8136,7 +8208,17 @@ package: prim_ram_1p_pkg type: uni act: req - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } default: "'0" inst_name: sram_ctrl_main index: -1 @@ -9240,8 +9322,6 @@ i2c0.ram_cfg i2c1.ram_cfg i2c2.ram_cfg - sram_ctrl_main.cfg - sram_ctrl_ret_aon.cfg rv_core_ibex.ram_cfg_icache_tag rv_core_ibex.ram_cfg_icache_data ] @@ -9838,6 +9918,8 @@ ast.lc_dft_en: "" ast.obs_ctrl: obs_ctrl ast.ram_1p_cfg: ram_1p_cfg + sram_ctrl_main.cfg: sram_ctrl_main_cfg + sram_ctrl_ret_aon.cfg: sram_ctrl_ret_aon_cfg ast.spi_ram_2p_cfg: spi_ram_2p_cfg ast.usb_ram_1p_cfg: usb_ram_1p_cfg ast.rom_cfg: rom_cfg @@ -20141,10 +20223,22 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } default: "'0" inst_name: sram_ctrl_ret_aon - top_signame: ast_ram_1p_cfg + external: true + top_signame: sram_ctrl_ret_aon_cfg + conn_type: false index: -1 } { @@ -20153,7 +20247,17 @@ package: prim_ram_1p_pkg type: uni act: req - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } default: "'0" inst_name: sram_ctrl_ret_aon index: -1 @@ -21629,10 +21733,22 @@ package: prim_ram_1p_pkg type: uni act: rcv - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } default: "'0" inst_name: sram_ctrl_main - top_signame: ast_ram_1p_cfg + external: true + top_signame: sram_ctrl_main_cfg + conn_type: false index: -1 } { @@ -21641,7 +21757,17 @@ package: prim_ram_1p_pkg type: uni act: req - width: 1 + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } default: "'0" inst_name: sram_ctrl_main index: -1 @@ -22955,6 +23081,50 @@ index: -1 netname: ast_ram_1p_cfg } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg + signame: sram_ctrl_main_cfg_i + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } + type: uni + default: "'0" + direction: in + conn_type: false + index: -1 + netname: sram_ctrl_main_cfg + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg + signame: sram_ctrl_ret_aon_cfg_i + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } + type: uni + default: "'0" + direction: in + conn_type: false + index: -1 + netname: sram_ctrl_ret_aon_cfg + } { package: prim_ram_2p_pkg struct: ram_2p_cfg diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index 71fda39321b37..3adf456afa8f9 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -713,6 +713,7 @@ domain: ["Aon"], param_decl: { InstrExec: "0", + InstSize: "4096", } base_addrs: { regs: {hart: "0x40500000"}, @@ -896,6 +897,7 @@ param_decl: { InstrExec: "1", NumPrinceRoundsHalf: "2", + InstSize: "131072", }, base_addrs: { regs: {hart: "0x411C0000"}, @@ -1083,8 +1085,6 @@ 'i2c0.ram_cfg', 'i2c1.ram_cfg', 'i2c2.ram_cfg', - 'sram_ctrl_main.cfg', - 'sram_ctrl_ret_aon.cfg', 'rv_core_ibex.ram_cfg_icache_tag', 'rv_core_ibex.ram_cfg_icache_data'], 'ast.spi_ram_2p_cfg' : ['spi_device.ram_cfg_sys2spi', @@ -1293,6 +1293,8 @@ 'ast.lc_dft_en' : '', 'ast.obs_ctrl' : 'obs_ctrl', 'ast.ram_1p_cfg' : 'ram_1p_cfg', + 'sram_ctrl_main.cfg' : 'sram_ctrl_main_cfg' + 'sram_ctrl_ret_aon.cfg' : 'sram_ctrl_ret_aon_cfg' 'ast.spi_ram_2p_cfg' : 'spi_ram_2p_cfg', 'ast.usb_ram_1p_cfg' : 'usb_ram_1p_cfg', 'ast.rom_cfg' : 'rom_cfg', diff --git a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh index ebb9c8fda1c0e..3b92a1f624625 100644 --- a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh +++ b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh @@ -49,15 +49,15 @@ `define FLASH1_INFO_MEM_HIER `FLASH_BANK1_HIER.gen_info_types[0].u_info_mem.`MEM_ARRAY_SUB `define ICACHE_WAY0_HIER `CPU_CORE_HIER.gen_rams.gen_rams_inner[0].gen_scramble_rams `define ICACHE_WAY1_HIER `CPU_CORE_HIER.gen_rams.gen_rams_inner[1].gen_scramble_rams -`define ICACHE0_TAG_MEM_HIER `ICACHE_WAY0_HIER.tag_bank.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB -`define ICACHE1_TAG_MEM_HIER `ICACHE_WAY1_HIER.tag_bank.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB -`define ICACHE0_DATA_MEM_HIER `ICACHE_WAY0_HIER.data_bank.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB -`define ICACHE1_DATA_MEM_HIER `ICACHE_WAY1_HIER.data_bank.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB -`define RAM_MAIN_MEM_HIER `RAM_MAIN_HIER.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB -`define RAM_RET_MEM_HIER `RAM_RET_HIER.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB +`define ICACHE0_TAG_MEM_HIER `ICACHE_WAY0_HIER.tag_bank.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define ICACHE1_TAG_MEM_HIER `ICACHE_WAY1_HIER.tag_bank.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define ICACHE0_DATA_MEM_HIER `ICACHE_WAY0_HIER.data_bank.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define ICACHE1_DATA_MEM_HIER `ICACHE_WAY1_HIER.data_bank.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define RAM_MAIN_MEM_HIER `RAM_MAIN_HIER.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define RAM_RET_MEM_HIER `RAM_RET_HIER.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB `define ROM_MEM_HIER `ROM_CTRL_HIER.`ROM_CTRL_INT_PATH `define OTP_GENERIC_HIER `OTP_CTRL_HIER.u_otp.gen_generic.u_impl_generic -`define OTP_MEM_HIER `OTP_GENERIC_HIER.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB -`define OTBN_IMEM_HIER `OTBN_HIER.u_imem.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB -`define OTBN_DMEM_HIER `OTBN_HIER.u_dmem.u_prim_ram_1p_adv.u_mem.`MEM_ARRAY_SUB -`define USBDEV_BUF_HIER `USBDEV_HIER.gen_no_stubbed_memory.u_memory_1p.u_mem.`MEM_ARRAY_SUB +`define OTP_MEM_HIER `OTP_GENERIC_HIER.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define OTBN_IMEM_HIER `OTBN_HIER.u_imem.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define OTBN_DMEM_HIER `OTBN_HIER.u_dmem.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define USBDEV_BUF_HIER `USBDEV_HIER.gen_no_stubbed_memory.u_memory_1p.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB diff --git a/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc b/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc index c8625a7d7c072..6c832e3415a22 100644 --- a/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc +++ b/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc @@ -20,7 +20,7 @@ int main(int argc, char **argv) { std::string top_scope("TOP.chip_sim_tb.u_dut.top_earlgrey"); std::string ram1p_adv_scope( - "u_prim_ram_1p_adv.u_mem." + "u_prim_ram_1p_adv.gen_ram_inst[0].u_mem." "gen_generic.u_impl_generic"); MemArea rom(top_scope + (".u_rom_ctrl.gen_rom_scramble_enabled.u_rom.u_rom." diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv index c9020b93947bf..dd4e9259565df 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv @@ -1233,6 +1233,8 @@ module chip_earlgrey_asic #( // Memory attributes .ram_1p_cfg_i ( ram_1p_cfg ), + .sram_ctrl_main_cfg_i ( '{ram_1p_cfg} ), + .sram_ctrl_ret_aon_cfg_i ( '{ram_1p_cfg} ), .spi_ram_2p_cfg_i ( spi_ram_2p_cfg ), .usb_ram_1p_cfg_i ( usb_ram_1p_cfg ), diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 68df8c8880f78..bcede3620361b 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -60,6 +60,8 @@ module top_earlgrey #( // parameters for aon_timer_aon // parameters for sensor_ctrl_aon // parameters for sram_ctrl_ret_aon + parameter int SramCtrlRetAonInstSize = 4096, + parameter int SramCtrlRetAonNumRamInst = 1, parameter bit SramCtrlRetAonInstrExec = 0, parameter int SramCtrlRetAonNumPrinceRoundsHalf = 3, // parameters for flash_ctrl @@ -103,6 +105,8 @@ module top_earlgrey #( // parameters for edn0 // parameters for edn1 // parameters for sram_ctrl_main + parameter int SramCtrlMainInstSize = 131072, + parameter int SramCtrlMainNumRamInst = 1, parameter bit SramCtrlMainInstrExec = 1, parameter int SramCtrlMainNumPrinceRoundsHalf = 2, // parameters for rom_ctrl @@ -160,6 +164,8 @@ module top_earlgrey #( output lc_ctrl_pkg::lc_tx_t ast_lc_dft_en_o, input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, input prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg_i, + input prim_ram_1p_pkg::ram_1p_cfg_t [SramCtrlMainNumRamInst-1:0] sram_ctrl_main_cfg_i, + input prim_ram_1p_pkg::ram_1p_cfg_t [SramCtrlRetAonNumRamInst-1:0] sram_ctrl_ret_aon_cfg_i, input prim_ram_2p_pkg::ram_2p_cfg_t spi_ram_2p_cfg_i, input prim_ram_1p_pkg::ram_1p_cfg_t usb_ram_1p_cfg_i, input prim_rom_pkg::rom_cfg_t rom_cfg_i, @@ -2115,6 +2121,8 @@ module top_earlgrey #( .RndCnstLfsrSeed(RndCnstSramCtrlRetAonLfsrSeed), .RndCnstLfsrPerm(RndCnstSramCtrlRetAonLfsrPerm), .MemSizeRam(4096), + .InstSize(SramCtrlRetAonInstSize), + .NumRamInst(SramCtrlRetAonNumRamInst), .InstrExec(SramCtrlRetAonInstrExec), .NumPrinceRoundsHalf(SramCtrlRetAonNumPrinceRoundsHalf) ) u_sram_ctrl_ret_aon ( @@ -2125,7 +2133,7 @@ module top_earlgrey #( // Inter-module signals .sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]), .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[1]), - .cfg_i(ast_ram_1p_cfg), + .cfg_i(sram_ctrl_ret_aon_cfg_i), .cfg_rsp_o(), .lc_escalate_en_i(lc_ctrl_lc_escalate_en), .lc_hw_debug_en_i(lc_ctrl_pkg::Off), @@ -2597,6 +2605,8 @@ module top_earlgrey #( .RndCnstLfsrSeed(RndCnstSramCtrlMainLfsrSeed), .RndCnstLfsrPerm(RndCnstSramCtrlMainLfsrPerm), .MemSizeRam(131072), + .InstSize(SramCtrlMainInstSize), + .NumRamInst(SramCtrlMainNumRamInst), .InstrExec(SramCtrlMainInstrExec), .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf) ) u_sram_ctrl_main ( @@ -2607,7 +2617,7 @@ module top_earlgrey #( // Inter-module signals .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]), .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[0]), - .cfg_i(ast_ram_1p_cfg), + .cfg_i(sram_ctrl_main_cfg_i), .cfg_rsp_o(), .lc_escalate_en_i(lc_ctrl_lc_escalate_en), .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), diff --git a/hw/top_earlgrey/templates/chiplevel.sv.tpl b/hw/top_earlgrey/templates/chiplevel.sv.tpl index e07d3252e3d64..fdfb0a1165d14 100644 --- a/hw/top_earlgrey/templates/chiplevel.sv.tpl +++ b/hw/top_earlgrey/templates/chiplevel.sv.tpl @@ -1068,6 +1068,8 @@ module chip_${top["name"]}_${target["name"]} #( // Memory attributes .ram_1p_cfg_i ( ram_1p_cfg ), + .sram_ctrl_main_cfg_i ( '{ram_1p_cfg} ), + .sram_ctrl_ret_aon_cfg_i ( '{ram_1p_cfg} ), .spi_ram_2p_cfg_i ( spi_ram_2p_cfg ), .usb_ram_1p_cfg_i ( usb_ram_1p_cfg ),