diff --git a/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson b/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson index 69eca7873306c..8c91f0c426f40 100644 --- a/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson +++ b/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson @@ -69,11 +69,34 @@ { struct: "ram_1p_cfg", type: "uni", - name: "ram_cfg", + name: "ram_cfg_icache_tag", act: "rcv", package: "prim_ram_1p_pkg", }, + { struct: "ram_1p_cfg_rsp", + type: "uni", + name: "ram_cfg_rsp_icache_tag", + width: "ICacheNWays", + act: "req", + package: "prim_ram_1p_pkg", + }, + + { struct: "ram_1p_cfg", + type: "uni", + name: "ram_cfg_icache_data", + act: "rcv", + package: "prim_ram_1p_pkg", + }, + + { struct: "ram_1p_cfg_rsp", + type: "uni", + name: "ram_cfg_rsp_icache_data", + width: "ICacheNWays", + act: "req", + package: "prim_ram_1p_pkg", + }, + { struct: "logic", type: "uni", name: "hart_id", @@ -367,6 +390,14 @@ expose: "true" }, + { name: "ICacheNWays" + type: "int unsigned" + default: "2" + desc: "Number of instruction cache ways" + local: "true" + expose: "true" + }, + { name: "BranchPredictor" type: "bit" default: "0" diff --git a/hw/ip/rv_core_ibex/doc/interfaces.md b/hw/ip/rv_core_ibex/doc/interfaces.md index 1b648cf9c993d..bb33d0f309a1f 100644 --- a/hw/ip/rv_core_ibex/doc/interfaces.md +++ b/hw/ip/rv_core_ibex/doc/interfaces.md @@ -13,29 +13,32 @@ Referring to the [Comportable guideline for peripheral device functionality](htt ## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) -| Port Name | Package::Struct | Type | Act | Width | Description | -|:---------------|:---------------------------------|:--------|:------|--------:|:--------------| -| rst_cpu_n | logic | uni | req | 1 | | -| ram_cfg | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | | -| hart_id | logic | uni | rcv | 32 | | -| boot_addr | logic | uni | rcv | 32 | | -| irq_software | logic | uni | rcv | 1 | | -| irq_timer | logic | uni | rcv | 1 | | -| irq_external | logic | uni | rcv | 1 | | -| esc_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | | -| esc_rx | prim_esc_pkg::esc_rx | uni | req | 1 | | -| debug_req | logic | uni | rcv | 1 | | -| crash_dump | rv_core_ibex_pkg::cpu_crash_dump | uni | req | 1 | | -| lc_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| pwrmgr_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| pwrmgr | rv_core_ibex_pkg::cpu_pwrmgr | uni | req | 1 | | -| nmi_wdog | logic | uni | rcv | 1 | | -| edn | edn_pkg::edn | req_rsp | req | 1 | | -| icache_otp_key | otp_ctrl_pkg::sram_otp_key | req_rsp | req | 1 | | -| fpga_info | logic | uni | rcv | 32 | | -| corei_tl_h | tlul_pkg::tl | req_rsp | req | 1 | | -| cored_tl_h | tlul_pkg::tl | req_rsp | req | 1 | | -| cfg_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | | +| Port Name | Package::Struct | Type | Act | Width | Description | +|:------------------------|:---------------------------------|:--------|:------|:------------|:--------------| +| rst_cpu_n | logic | uni | req | 1 | | +| ram_cfg_icache_tag | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | | +| ram_cfg_rsp_icache_tag | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | ICacheNWays | | +| ram_cfg_icache_data | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | | +| ram_cfg_rsp_icache_data | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | ICacheNWays | | +| hart_id | logic | uni | rcv | 32 | | +| boot_addr | logic | uni | rcv | 32 | | +| irq_software | logic | uni | rcv | 1 | | +| irq_timer | logic | uni | rcv | 1 | | +| irq_external | logic | uni | rcv | 1 | | +| esc_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | | +| esc_rx | prim_esc_pkg::esc_rx | uni | req | 1 | | +| debug_req | logic | uni | rcv | 1 | | +| crash_dump | rv_core_ibex_pkg::cpu_crash_dump | uni | req | 1 | | +| lc_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| pwrmgr_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| pwrmgr | rv_core_ibex_pkg::cpu_pwrmgr | uni | req | 1 | | +| nmi_wdog | logic | uni | rcv | 1 | | +| edn | edn_pkg::edn | req_rsp | req | 1 | | +| icache_otp_key | otp_ctrl_pkg::sram_otp_key | req_rsp | req | 1 | | +| fpga_info | logic | uni | rcv | 32 | | +| corei_tl_h | tlul_pkg::tl | req_rsp | req | 1 | | +| cored_tl_h | tlul_pkg::tl | req_rsp | req | 1 | | +| cfg_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | | ## Security Alerts diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv index e5a33e40e15f7..f64b2a2912efc 100644 --- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv +++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv @@ -30,6 +30,7 @@ module rv_core_ibex parameter bit ICache = 1'b1, parameter bit ICacheECC = 1'b1, parameter bit ICacheScramble = 1'b1, + parameter int unsigned ICacheNWays = 2, parameter bit BranchPredictor = 1'b0, parameter bit DbgTriggerEn = 1'b1, parameter int unsigned DbgHwBreakNum = 4, @@ -60,7 +61,10 @@ module rv_core_ibex // Reset feedback to rstmgr output logic rst_cpu_n_o, - input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i, + input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_icache_tag_i, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ICacheNWays-1:0] ram_cfg_rsp_icache_tag_o, + input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_icache_data_i, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ICacheNWays-1:0] ram_cfg_rsp_icache_data_o, input logic [31:0] hart_id_i, input logic [31:0] boot_addr_i, @@ -423,7 +427,10 @@ module rv_core_ibex .test_en_i (prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)), .scan_rst_ni, - .ram_cfg_i, + .ram_cfg_icache_tag_i, + .ram_cfg_rsp_icache_tag_o, + .ram_cfg_icache_data_i, + .ram_cfg_rsp_icache_data_o, .hart_id_i, .boot_addr_i, @@ -907,6 +914,8 @@ module rv_core_ibex .tl_h_o(tl_win_d2h_err_rsp) ); + `ASSERT_INIT(ICacheNWaysCorrect_A, ICacheNWays == ibex_pkg::IC_NUM_WAYS) + // Assertions for CPU enable // Allow 2 or 3 cycles for input to enable due to synchronizers `ASSERT(FpvSecCmIbexFetchEnable0_A, diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index bfb709e4936ec..83d4ad5447791 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -8990,6 +8990,15 @@ expose: "true" name_top: RvCoreIbexICacheScramble } + { + name: ICacheNWays + desc: Number of instruction cache ways + type: int unsigned + default: 2 + local: "true" + expose: "true" + name_top: RvCoreIbexICacheNWays + } { name: BranchPredictor desc: Branch predictor @@ -9084,7 +9093,7 @@ index: -1 } { - name: ram_cfg + name: ram_cfg_icache_tag struct: ram_1p_cfg package: prim_ram_1p_pkg type: uni @@ -9095,6 +9104,66 @@ top_signame: ast_ram_1p_cfg index: -1 } + { + name: ram_cfg_rsp_icache_tag + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: ICacheNWays + desc: Number of instruction cache ways + param_type: int unsigned + unpacked_dimensions: null + default: 2 + local: true + expose: true + name_top: RvCoreIbexICacheNWays + } + inst_name: rv_core_ibex + default: "" + external: true + top_signame: rv_core_ibex_icache_tag_ram_1p_cfg_rsp + conn_type: false + index: -1 + } + { + name: ram_cfg_icache_data + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: ram_cfg_rsp_icache_data + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: ICacheNWays + desc: Number of instruction cache ways + param_type: int unsigned + unpacked_dimensions: null + default: 2 + local: true + expose: true + name_top: RvCoreIbexICacheNWays + } + inst_name: rv_core_ibex + default: "" + external: true + top_signame: rv_core_ibex_icache_data_ram_1p_cfg_rsp + conn_type: false + index: -1 + } { name: hart_id struct: logic @@ -9472,7 +9541,8 @@ sram_ctrl_main.cfg sram_ctrl_ret_aon.cfg sram_ctrl_mbox.cfg - rv_core_ibex.ram_cfg + rv_core_ibex.ram_cfg_icache_tag + rv_core_ibex.ram_cfg_icache_data ] ast.spi_ram_2p_cfg: [ @@ -10122,6 +10192,8 @@ sram_ctrl_mbox.cfg_rsp: sram_ctrl_mbox_ram_1p_cfg_rsp otbn.ram_cfg_rsp_imem: otbn_imem_ram_1p_cfg_rsp otbn.ram_cfg_rsp_dmem: otbn_dmem_ram_1p_cfg_rsp + rv_core_ibex.ram_cfg_rsp_icache_tag: rv_core_ibex_icache_tag_ram_1p_cfg_rsp + rv_core_ibex.ram_cfg_rsp_icache_data: rv_core_ibex_icache_data_ram_1p_cfg_rsp spi_device.ram_cfg_rsp_sys2spi: spi_device_ram_2p_cfg_rsp_sys2spi spi_device.ram_cfg_rsp_spi2sys: spi_device_ram_2p_cfg_rsp_spi2sys pwrmgr_aon.boot_status: pwrmgr_boot_status @@ -23099,7 +23171,7 @@ index: -1 } { - name: ram_cfg + name: ram_cfg_icache_tag struct: ram_1p_cfg package: prim_ram_1p_pkg type: uni @@ -23110,6 +23182,66 @@ top_signame: ast_ram_1p_cfg index: -1 } + { + name: ram_cfg_rsp_icache_tag + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: ICacheNWays + desc: Number of instruction cache ways + param_type: int unsigned + unpacked_dimensions: null + default: 2 + local: true + expose: true + name_top: RvCoreIbexICacheNWays + } + inst_name: rv_core_ibex + default: "" + external: true + top_signame: rv_core_ibex_icache_tag_ram_1p_cfg_rsp + conn_type: false + index: -1 + } + { + name: ram_cfg_icache_data + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: ram_cfg_rsp_icache_data + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: ICacheNWays + desc: Number of instruction cache ways + param_type: int unsigned + unpacked_dimensions: null + default: 2 + local: true + expose: true + name_top: RvCoreIbexICacheNWays + } + inst_name: rv_core_ibex + default: "" + external: true + top_signame: rv_core_ibex_icache_data_ram_1p_cfg_rsp + conn_type: false + index: -1 + } { name: hart_id struct: logic @@ -24651,6 +24783,50 @@ index: -1 netname: otbn_dmem_ram_1p_cfg_rsp } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg_rsp + signame: rv_core_ibex_icache_tag_ram_1p_cfg_rsp_o + width: + { + name: ICacheNWays + desc: Number of instruction cache ways + param_type: int unsigned + unpacked_dimensions: null + default: 2 + local: true + expose: true + name_top: RvCoreIbexICacheNWays + } + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: rv_core_ibex_icache_tag_ram_1p_cfg_rsp + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg_rsp + signame: rv_core_ibex_icache_data_ram_1p_cfg_rsp_o + width: + { + name: ICacheNWays + desc: Number of instruction cache ways + param_type: int unsigned + unpacked_dimensions: null + default: 2 + local: true + expose: true + name_top: RvCoreIbexICacheNWays + } + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: rv_core_ibex_icache_data_ram_1p_cfg_rsp + } { package: prim_ram_2p_pkg struct: ram_2p_cfg diff --git a/hw/top_darjeeling/data/top_darjeeling.hjson b/hw/top_darjeeling/data/top_darjeeling.hjson index d68a3aed0e681..ce9f7a427a77f 100644 --- a/hw/top_darjeeling/data/top_darjeeling.hjson +++ b/hw/top_darjeeling/data/top_darjeeling.hjson @@ -1119,7 +1119,8 @@ 'sram_ctrl_main.cfg', 'sram_ctrl_ret_aon.cfg', 'sram_ctrl_mbox.cfg', - 'rv_core_ibex.ram_cfg'], + 'rv_core_ibex.ram_cfg_icache_tag', + 'rv_core_ibex.ram_cfg_icache_data'], 'ast.spi_ram_2p_cfg' : ['spi_device.ram_cfg_sys2spi', 'spi_device.ram_cfg_spi2sys'] 'ast.rom_cfg' : ['rom_ctrl0.rom_cfg', @@ -1303,101 +1304,103 @@ // ext is to create port in the top. 'external': { - 'ast.edn' : '', - 'ast.lc_dft_en' : '', - 'ast.lc_hw_debug_en' : '', - 'ast.obs_ctrl' : 'obs_ctrl', - 'ast.ram_1p_cfg' : 'ram_1p_cfg', - 'ast.spi_ram_2p_cfg' : 'spi_ram_2p_cfg', - 'ast.rom_cfg' : 'rom_cfg', - 'i2c0.ram_cfg_rsp' : 'i2c_ram_1p_cfg_rsp', - 'sram_ctrl_ret_aon.cfg_rsp' : 'sram_ctrl_ret_aon_ram_1p_cfg_rsp', - 'sram_ctrl_main.cfg_rsp' : 'sram_ctrl_main_ram_1p_cfg_rsp', - 'sram_ctrl_mbox.cfg_rsp' : 'sram_ctrl_mbox_ram_1p_cfg_rsp', - 'otbn.ram_cfg_rsp_imem' : 'otbn_imem_ram_1p_cfg_rsp', - 'otbn.ram_cfg_rsp_dmem' : 'otbn_dmem_ram_1p_cfg_rsp', - 'spi_device.ram_cfg_rsp_sys2spi' : 'spi_device_ram_2p_cfg_rsp_sys2spi', - 'spi_device.ram_cfg_rsp_spi2sys' : 'spi_device_ram_2p_cfg_rsp_spi2sys', - 'pwrmgr_aon.boot_status' : 'pwrmgr_boot_status', - 'clkmgr_aon.jitter_en' : 'clk_main_jitter_en', - 'clkmgr_aon.io_clk_byp_req' : 'io_clk_byp_req', - 'clkmgr_aon.io_clk_byp_ack' : 'io_clk_byp_ack', - 'clkmgr_aon.all_clk_byp_req' : 'all_clk_byp_req', - 'clkmgr_aon.all_clk_byp_ack' : 'all_clk_byp_ack', - 'clkmgr_aon.hi_speed_sel' : 'hi_speed_sel', - 'clkmgr_aon.div_step_down_req' : 'div_step_down_req', - 'clkmgr_aon.calib_rdy' : 'calib_rdy', - 'csrng.entropy_src_hw_if' : 'entropy_src_hw_if', - 'dma.sys' : 'dma_sys', - 'dma.ctn_tl_h2d' : 'dma_ctn_tl_h2d', - 'dma.ctn_tl_d2h' : 'dma_ctn_tl_d2h', - 'mbx.tl_mbx' : 'mbx_tl', - 'mbx0.doe_intr' : 'mbx0_doe_intr', - 'mbx0.doe_intr_en' : 'mbx0_doe_intr_en', - 'mbx0.doe_intr_support' : 'mbx0_doe_intr_support', - 'mbx0.doe_async_msg_support' : 'mbx0_doe_async_msg_support', - 'mbx1.doe_intr' : 'mbx1_doe_intr', - 'mbx1.doe_intr_en' : 'mbx1_doe_intr_en', - 'mbx1.doe_intr_support' : 'mbx1_doe_intr_support', - 'mbx1.doe_async_msg_support' : 'mbx1_doe_async_msg_support', - 'mbx2.doe_intr' : 'mbx2_doe_intr', - 'mbx2.doe_intr_en' : 'mbx2_doe_intr_en', - 'mbx2.doe_intr_support' : 'mbx2_doe_intr_support', - 'mbx2.doe_async_msg_support' : 'mbx2_doe_async_msg_support', - 'mbx3.doe_intr' : 'mbx3_doe_intr', - 'mbx3.doe_intr_en' : 'mbx3_doe_intr_en', - 'mbx3.doe_intr_support' : 'mbx3_doe_intr_support', - 'mbx3.doe_async_msg_support' : 'mbx3_doe_async_msg_support', - 'mbx4.doe_intr' : 'mbx4_doe_intr', - 'mbx4.doe_intr_en' : 'mbx4_doe_intr_en', - 'mbx4.doe_intr_support' : 'mbx4_doe_intr_support', - 'mbx4.doe_async_msg_support' : 'mbx4_doe_async_msg_support', - 'mbx5.doe_intr' : 'mbx5_doe_intr', - 'mbx5.doe_intr_en' : 'mbx5_doe_intr_en', - 'mbx5.doe_intr_support' : 'mbx5_doe_intr_support', - 'mbx5.doe_async_msg_support' : 'mbx5_doe_async_msg_support', - 'mbx6.doe_intr' : 'mbx6_doe_intr', - 'mbx6.doe_intr_en' : 'mbx6_doe_intr_en', - 'mbx6.doe_intr_support' : 'mbx6_doe_intr_support', - 'mbx6.doe_async_msg_support' : 'mbx6_doe_async_msg_support', - 'mbx_jtag.doe_intr' : 'mbx_jtag_doe_intr', - 'mbx_jtag.doe_intr_en' : 'mbx_jtag_doe_intr_en', - 'mbx_jtag.doe_intr_support' : 'mbx_jtag_doe_intr_support', - 'mbx_jtag.doe_async_msg_support' : 'mbx_jtag_doe_async_msg_support', - 'mbx_pcie0.doe_intr' : 'mbx_pcie0_doe_intr', - 'mbx_pcie0.doe_intr_en' : 'mbx_pcie0_doe_intr_en', - 'mbx_pcie0.doe_intr_support' : 'mbx_pcie0_doe_intr_support', - 'mbx_pcie0.doe_async_msg_support' : 'mbx_pcie0_doe_async_msg_support', - 'mbx_pcie1.doe_intr' : 'mbx_pcie1_doe_intr', - 'mbx_pcie1.doe_intr_en' : 'mbx_pcie1_doe_intr_en', - 'mbx_pcie1.doe_intr_support' : 'mbx_pcie1_doe_intr_support', - 'mbx_pcie1.doe_async_msg_support' : 'mbx_pcie1_doe_async_msg_support', - 'dbg.tl_dbg' : 'dbg_tl', - 'rv_dm.next_dm_addr' : 'rv_dm_next_dm_addr', - 'peri.tl_ast' : 'ast_tl', - 'pwrmgr_aon.pwr_ast' : 'pwrmgr_ast', - 'otp_ctrl.otp_ast_pwr_seq' : '', - 'otp_ctrl.otp_ast_pwr_seq_h' : '', - 'otp_ctrl.otp_ext_voltage_h' : 'otp_ext_voltage_h', - 'otp_ctrl.otp_obs' : 'otp_obs', - 'rstmgr_aon.por_n' : 'por_n' - 'rv_core_ibex.fpga_info' : 'fpga_info' - 'sensor_ctrl.ast_alert' : 'sensor_ctrl_ast_alert', - 'sensor_ctrl.ast_status' : 'sensor_ctrl_ast_status', - 'sensor_ctrl.ast_init_done' : 'ast_init_done', - 'soc_proxy.ctn_tl_h2d' : 'ctn_tl_h2d', - 'soc_proxy.ctn_tl_d2h' : 'ctn_tl_d2h', - 'soc_proxy.soc_fatal_alert' : 'soc_fatal_alert', - 'soc_proxy.soc_recov_alert' : 'soc_recov_alert', - 'soc_proxy.soc_wkup_async' : 'soc_wkup_async', - 'soc_proxy.soc_rst_req_async' : 'soc_rst_req_async', - 'soc_proxy.soc_intr_async' : 'soc_intr_async', - 'soc_proxy.soc_lsio_trigger' : 'soc_lsio_trigger', - 'soc_proxy.soc_gpi_async' : 'soc_gpi_async', - 'soc_proxy.soc_gpo_async' : 'soc_gpo_async', - 'spi_device.sck_monitor' : 'sck_monitor', - 'soc_dbg_ctrl.soc_dbg_policy_bus' : 'soc_dbg_policy_bus', - 'soc_dbg_ctrl.halt_cpu_boot' : 'debug_halt_cpu_boot', + 'ast.edn' : '', + 'ast.lc_dft_en' : '', + 'ast.lc_hw_debug_en' : '', + 'ast.obs_ctrl' : 'obs_ctrl', + 'ast.ram_1p_cfg' : 'ram_1p_cfg', + 'ast.spi_ram_2p_cfg' : 'spi_ram_2p_cfg', + 'ast.rom_cfg' : 'rom_cfg', + 'i2c0.ram_cfg_rsp' : 'i2c_ram_1p_cfg_rsp', + 'sram_ctrl_ret_aon.cfg_rsp' : 'sram_ctrl_ret_aon_ram_1p_cfg_rsp', + 'sram_ctrl_main.cfg_rsp' : 'sram_ctrl_main_ram_1p_cfg_rsp', + 'sram_ctrl_mbox.cfg_rsp' : 'sram_ctrl_mbox_ram_1p_cfg_rsp', + 'otbn.ram_cfg_rsp_imem' : 'otbn_imem_ram_1p_cfg_rsp', + 'otbn.ram_cfg_rsp_dmem' : 'otbn_dmem_ram_1p_cfg_rsp', + 'rv_core_ibex.ram_cfg_rsp_icache_tag' : 'rv_core_ibex_icache_tag_ram_1p_cfg_rsp', + 'rv_core_ibex.ram_cfg_rsp_icache_data' : 'rv_core_ibex_icache_data_ram_1p_cfg_rsp', + 'spi_device.ram_cfg_rsp_sys2spi' : 'spi_device_ram_2p_cfg_rsp_sys2spi', + 'spi_device.ram_cfg_rsp_spi2sys' : 'spi_device_ram_2p_cfg_rsp_spi2sys', + 'pwrmgr_aon.boot_status' : 'pwrmgr_boot_status', + 'clkmgr_aon.jitter_en' : 'clk_main_jitter_en', + 'clkmgr_aon.io_clk_byp_req' : 'io_clk_byp_req', + 'clkmgr_aon.io_clk_byp_ack' : 'io_clk_byp_ack', + 'clkmgr_aon.all_clk_byp_req' : 'all_clk_byp_req', + 'clkmgr_aon.all_clk_byp_ack' : 'all_clk_byp_ack', + 'clkmgr_aon.hi_speed_sel' : 'hi_speed_sel', + 'clkmgr_aon.div_step_down_req' : 'div_step_down_req', + 'clkmgr_aon.calib_rdy' : 'calib_rdy', + 'csrng.entropy_src_hw_if' : 'entropy_src_hw_if', + 'dma.sys' : 'dma_sys', + 'dma.ctn_tl_h2d' : 'dma_ctn_tl_h2d', + 'dma.ctn_tl_d2h' : 'dma_ctn_tl_d2h', + 'mbx.tl_mbx' : 'mbx_tl', + 'mbx0.doe_intr' : 'mbx0_doe_intr', + 'mbx0.doe_intr_en' : 'mbx0_doe_intr_en', + 'mbx0.doe_intr_support' : 'mbx0_doe_intr_support', + 'mbx0.doe_async_msg_support' : 'mbx0_doe_async_msg_support', + 'mbx1.doe_intr' : 'mbx1_doe_intr', + 'mbx1.doe_intr_en' : 'mbx1_doe_intr_en', + 'mbx1.doe_intr_support' : 'mbx1_doe_intr_support', + 'mbx1.doe_async_msg_support' : 'mbx1_doe_async_msg_support', + 'mbx2.doe_intr' : 'mbx2_doe_intr', + 'mbx2.doe_intr_en' : 'mbx2_doe_intr_en', + 'mbx2.doe_intr_support' : 'mbx2_doe_intr_support', + 'mbx2.doe_async_msg_support' : 'mbx2_doe_async_msg_support', + 'mbx3.doe_intr' : 'mbx3_doe_intr', + 'mbx3.doe_intr_en' : 'mbx3_doe_intr_en', + 'mbx3.doe_intr_support' : 'mbx3_doe_intr_support', + 'mbx3.doe_async_msg_support' : 'mbx3_doe_async_msg_support', + 'mbx4.doe_intr' : 'mbx4_doe_intr', + 'mbx4.doe_intr_en' : 'mbx4_doe_intr_en', + 'mbx4.doe_intr_support' : 'mbx4_doe_intr_support', + 'mbx4.doe_async_msg_support' : 'mbx4_doe_async_msg_support', + 'mbx5.doe_intr' : 'mbx5_doe_intr', + 'mbx5.doe_intr_en' : 'mbx5_doe_intr_en', + 'mbx5.doe_intr_support' : 'mbx5_doe_intr_support', + 'mbx5.doe_async_msg_support' : 'mbx5_doe_async_msg_support', + 'mbx6.doe_intr' : 'mbx6_doe_intr', + 'mbx6.doe_intr_en' : 'mbx6_doe_intr_en', + 'mbx6.doe_intr_support' : 'mbx6_doe_intr_support', + 'mbx6.doe_async_msg_support' : 'mbx6_doe_async_msg_support', + 'mbx_jtag.doe_intr' : 'mbx_jtag_doe_intr', + 'mbx_jtag.doe_intr_en' : 'mbx_jtag_doe_intr_en', + 'mbx_jtag.doe_intr_support' : 'mbx_jtag_doe_intr_support', + 'mbx_jtag.doe_async_msg_support' : 'mbx_jtag_doe_async_msg_support', + 'mbx_pcie0.doe_intr' : 'mbx_pcie0_doe_intr', + 'mbx_pcie0.doe_intr_en' : 'mbx_pcie0_doe_intr_en', + 'mbx_pcie0.doe_intr_support' : 'mbx_pcie0_doe_intr_support', + 'mbx_pcie0.doe_async_msg_support' : 'mbx_pcie0_doe_async_msg_support', + 'mbx_pcie1.doe_intr' : 'mbx_pcie1_doe_intr', + 'mbx_pcie1.doe_intr_en' : 'mbx_pcie1_doe_intr_en', + 'mbx_pcie1.doe_intr_support' : 'mbx_pcie1_doe_intr_support', + 'mbx_pcie1.doe_async_msg_support' : 'mbx_pcie1_doe_async_msg_support', + 'dbg.tl_dbg' : 'dbg_tl', + 'rv_dm.next_dm_addr' : 'rv_dm_next_dm_addr', + 'peri.tl_ast' : 'ast_tl', + 'pwrmgr_aon.pwr_ast' : 'pwrmgr_ast', + 'otp_ctrl.otp_ast_pwr_seq' : '', + 'otp_ctrl.otp_ast_pwr_seq_h' : '', + 'otp_ctrl.otp_ext_voltage_h' : 'otp_ext_voltage_h', + 'otp_ctrl.otp_obs' : 'otp_obs', + 'rstmgr_aon.por_n' : 'por_n' + 'rv_core_ibex.fpga_info' : 'fpga_info' + 'sensor_ctrl.ast_alert' : 'sensor_ctrl_ast_alert', + 'sensor_ctrl.ast_status' : 'sensor_ctrl_ast_status', + 'sensor_ctrl.ast_init_done' : 'ast_init_done', + 'soc_proxy.ctn_tl_h2d' : 'ctn_tl_h2d', + 'soc_proxy.ctn_tl_d2h' : 'ctn_tl_d2h', + 'soc_proxy.soc_fatal_alert' : 'soc_fatal_alert', + 'soc_proxy.soc_recov_alert' : 'soc_recov_alert', + 'soc_proxy.soc_wkup_async' : 'soc_wkup_async', + 'soc_proxy.soc_rst_req_async' : 'soc_rst_req_async', + 'soc_proxy.soc_intr_async' : 'soc_intr_async', + 'soc_proxy.soc_lsio_trigger' : 'soc_lsio_trigger', + 'soc_proxy.soc_gpi_async' : 'soc_gpi_async', + 'soc_proxy.soc_gpo_async' : 'soc_gpo_async', + 'spi_device.sck_monitor' : 'sck_monitor', + 'soc_dbg_ctrl.soc_dbg_policy_bus' : 'soc_dbg_policy_bus', + 'soc_dbg_ctrl.halt_cpu_boot' : 'debug_halt_cpu_boot', }, }, diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv index afa81def82486..2b4437360a483 100644 --- a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv @@ -171,6 +171,8 @@ module top_darjeeling #( output prim_ram_1p_pkg::ram_1p_cfg_rsp_t sram_ctrl_mbox_ram_1p_cfg_rsp_o, output prim_ram_1p_pkg::ram_1p_cfg_rsp_t otbn_imem_ram_1p_cfg_rsp_o, output prim_ram_1p_pkg::ram_1p_cfg_rsp_t otbn_dmem_ram_1p_cfg_rsp_o, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [RvCoreIbexICacheNWays-1:0] rv_core_ibex_icache_tag_ram_1p_cfg_rsp_o, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [RvCoreIbexICacheNWays-1:0] rv_core_ibex_icache_data_ram_1p_cfg_rsp_o, output prim_ram_2p_pkg::ram_2p_cfg_t spi_device_ram_2p_cfg_rsp_sys2spi_o, output prim_ram_2p_pkg::ram_2p_cfg_t spi_device_ram_2p_cfg_rsp_spi2sys_o, output pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status_o, @@ -292,6 +294,7 @@ module top_darjeeling #( // local parameters for rv_core_ibex localparam int unsigned RvCoreIbexNEscalationSeverities = alert_handler_reg_pkg::N_ESC_SEV; localparam int unsigned RvCoreIbexWidthPingCounter = alert_handler_reg_pkg::PING_CNT_DW; + localparam int unsigned RvCoreIbexICacheNWays = 2; // Signals logic [3:0] mio_p2d; @@ -2505,6 +2508,7 @@ module top_darjeeling #( .ICache(RvCoreIbexICache), .ICacheECC(RvCoreIbexICacheECC), .ICacheScramble(RvCoreIbexICacheScramble), + .ICacheNWays(RvCoreIbexICacheNWays), .BranchPredictor(RvCoreIbexBranchPredictor), .DbgTriggerEn(RvCoreIbexDbgTriggerEn), .DbgHwBreakNum(RvCoreIbexDbgHwBreakNum), @@ -2524,7 +2528,10 @@ module top_darjeeling #( // Inter-module signals .rst_cpu_n_o(), - .ram_cfg_i(ast_ram_1p_cfg), + .ram_cfg_icache_tag_i(ast_ram_1p_cfg), + .ram_cfg_rsp_icache_tag_o(rv_core_ibex_icache_tag_ram_1p_cfg_rsp_o), + .ram_cfg_icache_data_i(ast_ram_1p_cfg), + .ram_cfg_rsp_icache_data_o(rv_core_ibex_icache_data_ram_1p_cfg_rsp_o), .hart_id_i(rv_core_ibex_hart_id), .boot_addr_i(rv_core_ibex_boot_addr), .irq_software_i(rv_plic_msip), diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index bd7b88b1534e9..70590f4395ea7 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -8694,6 +8694,15 @@ expose: "true" name_top: RvCoreIbexICacheScramble } + { + name: ICacheNWays + desc: Number of instruction cache ways + type: int unsigned + default: 2 + local: "true" + expose: "true" + name_top: RvCoreIbexICacheNWays + } { name: BranchPredictor desc: Branch predictor @@ -8788,7 +8797,7 @@ index: -1 } { - name: ram_cfg + name: ram_cfg_icache_tag struct: ram_1p_cfg package: prim_ram_1p_pkg type: uni @@ -8799,6 +8808,58 @@ top_signame: ast_ram_1p_cfg index: -1 } + { + name: ram_cfg_rsp_icache_tag + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: ICacheNWays + desc: Number of instruction cache ways + param_type: int unsigned + unpacked_dimensions: null + default: 2 + local: true + expose: true + name_top: RvCoreIbexICacheNWays + } + inst_name: rv_core_ibex + index: -1 + } + { + name: ram_cfg_icache_data + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: ram_cfg_rsp_icache_data + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: ICacheNWays + desc: Number of instruction cache ways + param_type: int unsigned + unpacked_dimensions: null + default: 2 + local: true + expose: true + name_top: RvCoreIbexICacheNWays + } + inst_name: rv_core_ibex + index: -1 + } { name: hart_id struct: logic @@ -9181,7 +9242,8 @@ i2c2.ram_cfg sram_ctrl_main.cfg sram_ctrl_ret_aon.cfg - rv_core_ibex.ram_cfg + rv_core_ibex.ram_cfg_icache_tag + rv_core_ibex.ram_cfg_icache_data ] ast.spi_ram_2p_cfg: [ @@ -21734,7 +21796,39 @@ index: -1 } { - name: ram_cfg + name: ram_cfg_icache_tag + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: ram_cfg_rsp_icache_tag + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: ICacheNWays + desc: Number of instruction cache ways + param_type: int unsigned + unpacked_dimensions: null + default: 2 + local: true + expose: true + name_top: RvCoreIbexICacheNWays + } + inst_name: rv_core_ibex + index: -1 + } + { + name: ram_cfg_icache_data struct: ram_1p_cfg package: prim_ram_1p_pkg type: uni @@ -21745,6 +21839,26 @@ top_signame: ast_ram_1p_cfg index: -1 } + { + name: ram_cfg_rsp_icache_data + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: ICacheNWays + desc: Number of instruction cache ways + param_type: int unsigned + unpacked_dimensions: null + default: 2 + local: true + expose: true + name_top: RvCoreIbexICacheNWays + } + inst_name: rv_core_ibex + index: -1 + } { name: hart_id struct: logic diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index e8ea8df3f2ac3..71fda39321b37 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -1085,7 +1085,8 @@ 'i2c2.ram_cfg', 'sram_ctrl_main.cfg', 'sram_ctrl_ret_aon.cfg', - 'rv_core_ibex.ram_cfg'], + 'rv_core_ibex.ram_cfg_icache_tag', + 'rv_core_ibex.ram_cfg_icache_data'], 'ast.spi_ram_2p_cfg' : ['spi_device.ram_cfg_sys2spi', 'spi_device.ram_cfg_spi2sys'] 'ast.usb_ram_1p_cfg' : ['usbdev.ram_cfg'], diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 933c89a70169d..68df8c8880f78 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -238,6 +238,7 @@ module top_earlgrey #( // local parameters for rv_core_ibex localparam int unsigned RvCoreIbexNEscalationSeverities = alert_handler_reg_pkg::N_ESC_SEV; localparam int unsigned RvCoreIbexWidthPingCounter = alert_handler_reg_pkg::PING_CNT_DW; + localparam int unsigned RvCoreIbexICacheNWays = 2; // Signals logic [56:0] mio_p2d; @@ -2674,6 +2675,7 @@ module top_earlgrey #( .ICache(RvCoreIbexICache), .ICacheECC(RvCoreIbexICacheECC), .ICacheScramble(RvCoreIbexICacheScramble), + .ICacheNWays(RvCoreIbexICacheNWays), .BranchPredictor(RvCoreIbexBranchPredictor), .DbgTriggerEn(RvCoreIbexDbgTriggerEn), .DbgHwBreakNum(RvCoreIbexDbgHwBreakNum), @@ -2693,7 +2695,10 @@ module top_earlgrey #( // Inter-module signals .rst_cpu_n_o(), - .ram_cfg_i(ast_ram_1p_cfg), + .ram_cfg_icache_tag_i(ast_ram_1p_cfg), + .ram_cfg_rsp_icache_tag_o(), + .ram_cfg_icache_data_i(ast_ram_1p_cfg), + .ram_cfg_rsp_icache_data_o(), .hart_id_i(rv_core_ibex_hart_id), .boot_addr_i(rv_core_ibex_boot_addr), .irq_software_i(rv_plic_msip), diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_top.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_top.sv index a90fee0e668bc..085e80eeb7713 100644 --- a/hw/vendor/lowrisc_ibex/rtl/ibex_top.sv +++ b/hw/vendor/lowrisc_ibex/rtl/ibex_top.sv @@ -46,105 +46,110 @@ module ibex_top import ibex_pkg::*; #( parameter logic [SCRAMBLE_NONCE_W-1:0] RndCnstIbexNonce = RndCnstIbexNonceDefault ) ( // Clock and Reset - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, - input logic test_en_i, // enable all clock gates for testing - input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i, + // enable all clock gates for testing + input logic test_en_i, + input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_icache_tag_i, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_rsp_icache_tag_o, + input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_icache_data_i, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_rsp_icache_data_o, - input logic [31:0] hart_id_i, - input logic [31:0] boot_addr_i, + input logic [31:0] hart_id_i, + input logic [31:0] boot_addr_i, // Instruction memory interface - output logic instr_req_o, - input logic instr_gnt_i, - input logic instr_rvalid_i, - output logic [31:0] instr_addr_o, - input logic [31:0] instr_rdata_i, - input logic [6:0] instr_rdata_intg_i, - input logic instr_err_i, + output logic instr_req_o, + input logic instr_gnt_i, + input logic instr_rvalid_i, + output logic [31:0] instr_addr_o, + input logic [31:0] instr_rdata_i, + input logic [6:0] instr_rdata_intg_i, + input logic instr_err_i, // Data memory interface - output logic data_req_o, - input logic data_gnt_i, - input logic data_rvalid_i, - output logic data_we_o, - output logic [3:0] data_be_o, - output logic [31:0] data_addr_o, - output logic [31:0] data_wdata_o, - output logic [6:0] data_wdata_intg_o, - input logic [31:0] data_rdata_i, - input logic [6:0] data_rdata_intg_i, - input logic data_err_i, + output logic data_req_o, + input logic data_gnt_i, + input logic data_rvalid_i, + output logic data_we_o, + output logic [3:0] data_be_o, + output logic [31:0] data_addr_o, + output logic [31:0] data_wdata_o, + output logic [6:0] data_wdata_intg_o, + input logic [31:0] data_rdata_i, + input logic [6:0] data_rdata_intg_i, + input logic data_err_i, // Interrupt inputs - input logic irq_software_i, - input logic irq_timer_i, - input logic irq_external_i, - input logic [14:0] irq_fast_i, - input logic irq_nm_i, // non-maskeable interrupt + input logic irq_software_i, + input logic irq_timer_i, + input logic irq_external_i, + input logic [14:0] irq_fast_i, + // non-maskeable interrupt + input logic irq_nm_i, // Scrambling Interface - input logic scramble_key_valid_i, - input logic [SCRAMBLE_KEY_W-1:0] scramble_key_i, - input logic [SCRAMBLE_NONCE_W-1:0] scramble_nonce_i, - output logic scramble_req_o, + input logic scramble_key_valid_i, + input logic [SCRAMBLE_KEY_W-1:0] scramble_key_i, + input logic [SCRAMBLE_NONCE_W-1:0] scramble_nonce_i, + output logic scramble_req_o, // Debug Interface - input logic debug_req_i, - output crash_dump_t crash_dump_o, - output logic double_fault_seen_o, + input logic debug_req_i, + output crash_dump_t crash_dump_o, + output logic double_fault_seen_o, // RISC-V Formal Interface // Does not comply with the coding standards of _i/_o suffixes, but follows // the convention of RISC-V Formal Interface Specification. `ifdef RVFI - output logic rvfi_valid, - output logic [63:0] rvfi_order, - output logic [31:0] rvfi_insn, - output logic rvfi_trap, - output logic rvfi_halt, - output logic rvfi_intr, - output logic [ 1:0] rvfi_mode, - output logic [ 1:0] rvfi_ixl, - output logic [ 4:0] rvfi_rs1_addr, - output logic [ 4:0] rvfi_rs2_addr, - output logic [ 4:0] rvfi_rs3_addr, - output logic [31:0] rvfi_rs1_rdata, - output logic [31:0] rvfi_rs2_rdata, - output logic [31:0] rvfi_rs3_rdata, - output logic [ 4:0] rvfi_rd_addr, - output logic [31:0] rvfi_rd_wdata, - output logic [31:0] rvfi_pc_rdata, - output logic [31:0] rvfi_pc_wdata, - output logic [31:0] rvfi_mem_addr, - output logic [ 3:0] rvfi_mem_rmask, - output logic [ 3:0] rvfi_mem_wmask, - output logic [31:0] rvfi_mem_rdata, - output logic [31:0] rvfi_mem_wdata, - output logic [31:0] rvfi_ext_pre_mip, - output logic [31:0] rvfi_ext_post_mip, - output logic rvfi_ext_nmi, - output logic rvfi_ext_nmi_int, - output logic rvfi_ext_debug_req, - output logic rvfi_ext_debug_mode, - output logic rvfi_ext_rf_wr_suppress, - output logic [63:0] rvfi_ext_mcycle, - output logic [31:0] rvfi_ext_mhpmcounters [10], - output logic [31:0] rvfi_ext_mhpmcountersh [10], - output logic rvfi_ext_ic_scr_key_valid, - output logic rvfi_ext_irq_valid, + output logic rvfi_valid, + output logic [63:0] rvfi_order, + output logic [31:0] rvfi_insn, + output logic rvfi_trap, + output logic rvfi_halt, + output logic rvfi_intr, + output logic [ 1:0] rvfi_mode, + output logic [ 1:0] rvfi_ixl, + output logic [ 4:0] rvfi_rs1_addr, + output logic [ 4:0] rvfi_rs2_addr, + output logic [ 4:0] rvfi_rs3_addr, + output logic [31:0] rvfi_rs1_rdata, + output logic [31:0] rvfi_rs2_rdata, + output logic [31:0] rvfi_rs3_rdata, + output logic [ 4:0] rvfi_rd_addr, + output logic [31:0] rvfi_rd_wdata, + output logic [31:0] rvfi_pc_rdata, + output logic [31:0] rvfi_pc_wdata, + output logic [31:0] rvfi_mem_addr, + output logic [ 3:0] rvfi_mem_rmask, + output logic [ 3:0] rvfi_mem_wmask, + output logic [31:0] rvfi_mem_rdata, + output logic [31:0] rvfi_mem_wdata, + output logic [31:0] rvfi_ext_pre_mip, + output logic [31:0] rvfi_ext_post_mip, + output logic rvfi_ext_nmi, + output logic rvfi_ext_nmi_int, + output logic rvfi_ext_debug_req, + output logic rvfi_ext_debug_mode, + output logic rvfi_ext_rf_wr_suppress, + output logic [63:0] rvfi_ext_mcycle, + output logic [31:0] rvfi_ext_mhpmcounters [10], + output logic [31:0] rvfi_ext_mhpmcountersh [10], + output logic rvfi_ext_ic_scr_key_valid, + output logic rvfi_ext_irq_valid, `endif // CPU Control Signals - input ibex_mubi_t fetch_enable_i, - output logic alert_minor_o, - output logic alert_major_internal_o, - output logic alert_major_bus_o, - output logic core_sleep_o, + input ibex_mubi_t fetch_enable_i, + output logic alert_minor_o, + output logic alert_major_internal_o, + output logic alert_major_bus_o, + output logic core_sleep_o, // DFT bypass controls - input logic scan_rst_ni + input logic scan_rst_ni ); localparam bit Lockstep = SecureIbex; @@ -603,7 +608,8 @@ module ibex_top import ibex_pkg::*; #( .rvalid_o (), .raddr_o (), .rerror_o (), - .cfg_i (ram_cfg_i), + .cfg_i (ram_cfg_icache_tag_i), + .cfg_rsp_o (ram_cfg_rsp_icache_tag_o[way]), .wr_collision_o (), .write_pending_o (), @@ -640,7 +646,8 @@ module ibex_top import ibex_pkg::*; #( .rvalid_o (), .raddr_o (), .rerror_o (), - .cfg_i (ram_cfg_i), + .cfg_i (ram_cfg_icache_data_i), + .cfg_rsp_o (ram_cfg_rsp_icache_data_o[way]), .wr_collision_o (), .write_pending_o (), @@ -695,7 +702,8 @@ module ibex_top import ibex_pkg::*; #( .wmask_i ({TagSizeECC{1'b1}}), .rdata_o (ic_tag_rdata[way]), - .cfg_i (ram_cfg_i) + .cfg_i (ram_cfg_icache_tag_i), + .cfg_rsp_o (ram_cfg_rsp_icache_tag_o[way]) ); // Data RAM instantiation @@ -714,7 +722,8 @@ module ibex_top import ibex_pkg::*; #( .wmask_i ({LineSizeECC{1'b1}}), .rdata_o (ic_data_rdata[way]), - .cfg_i (ram_cfg_i) + .cfg_i (ram_cfg_icache_data_i), + .cfg_rsp_o (ram_cfg_rsp_icache_data_o[way]) ); assign icache_tag_alert = '{default:'b0}; @@ -727,7 +736,9 @@ module ibex_top import ibex_pkg::*; #( prim_ram_1p_pkg::ram_1p_cfg_t unused_ram_cfg; logic unused_ram_inputs; - assign unused_ram_cfg = ram_cfg_i; + assign unused_ram_cfg = |{ram_cfg_icache_tag_i, ram_cfg_icache_data_i}; + assign ram_cfg_rsp_icache_tag_o = '0; + assign ram_cfg_rsp_icache_data_o = '0; assign unused_ram_inputs = (|ic_tag_req) & ic_tag_write & (|ic_tag_addr) & (|ic_tag_wdata) & (|ic_data_req) & ic_data_write & (|ic_data_addr) & (|ic_data_wdata) & (|scramble_key_q) & (|scramble_nonce_q) & scramble_key_valid_q & @@ -1147,7 +1158,8 @@ module ibex_top import ibex_pkg::*; #( // X check for top-level inputs `ASSERT_KNOWN(IbexTestEnX, test_en_i) - `ASSERT_KNOWN(IbexRamCfgX, ram_cfg_i) + `ASSERT_KNOWN(IbexRamCfgTagX, ram_cfg_icache_tag_i) + `ASSERT_KNOWN(IbexRamCfgDataX, ram_cfg_icache_data_i) `ASSERT_KNOWN(IbexHartIdX, hart_id_i) `ASSERT_KNOWN(IbexBootAddrX, boot_addr_i) diff --git a/hw/vendor/patches/lowrisc_ibex/rtl/0001-PATCH-Change-RAM-DFT-signals.patch b/hw/vendor/patches/lowrisc_ibex/rtl/0001-PATCH-Change-RAM-DFT-signals.patch new file mode 100644 index 0000000000000..f81fdab8acf8b --- /dev/null +++ b/hw/vendor/patches/lowrisc_ibex/rtl/0001-PATCH-Change-RAM-DFT-signals.patch @@ -0,0 +1,277 @@ +From eb4e416c1b7d9695155bda26ee83c36f9d592caf Mon Sep 17 00:00:00 2001 +From: Robert Schilling +Date: Mon, 23 Dec 2024 09:19:39 +0100 +Subject: [PATCH 1/1] [PATCH] Change RAM DFT signals + +This is to break a vendoring-cycle, in which modules provided by +OpenTitan and used by Ibex get updated, but for that change to land on + of the OpenTitan repository, either (a) Ibex needs to be +re-vendored with the instances of the changed modules updated, or (b) +Ibex in OpenTitan gets patched to allow OpenTitan to move forward. + +As re-vendoring the updates from OpenTitan into Ibex would require +basing the vendored IPs on the PR branch and the diff is quite +large, option (b) is faster, hence implemented in this patch. + +Co-authored-by: Andreas Kurth +Signed-off-by: Robert Schilling +--- + ibex_top.sv | 178 ++++++++++++++++++++++++++---------------------- + 1 file changed, 95 insertions(+), 83 deletions(-) + +diff --git a/ibex_top.sv b/ibex_top.sv +index a90fee0e..085e80ee 100644 +--- a/ibex_top.sv ++++ b/ibex_top.sv +@@ -46,105 +46,110 @@ module ibex_top import ibex_pkg::*; #( + parameter logic [SCRAMBLE_NONCE_W-1:0] RndCnstIbexNonce = RndCnstIbexNonceDefault + ) ( + // Clock and Reset +- input logic clk_i, +- input logic rst_ni, ++ input logic clk_i, ++ input logic rst_ni, + +- input logic test_en_i, // enable all clock gates for testing +- input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i, ++ // enable all clock gates for testing ++ input logic test_en_i, ++ input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_icache_tag_i, ++ output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_rsp_icache_tag_o, ++ input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_icache_data_i, ++ output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_rsp_icache_data_o, + +- input logic [31:0] hart_id_i, +- input logic [31:0] boot_addr_i, ++ input logic [31:0] hart_id_i, ++ input logic [31:0] boot_addr_i, + + // Instruction memory interface +- output logic instr_req_o, +- input logic instr_gnt_i, +- input logic instr_rvalid_i, +- output logic [31:0] instr_addr_o, +- input logic [31:0] instr_rdata_i, +- input logic [6:0] instr_rdata_intg_i, +- input logic instr_err_i, ++ output logic instr_req_o, ++ input logic instr_gnt_i, ++ input logic instr_rvalid_i, ++ output logic [31:0] instr_addr_o, ++ input logic [31:0] instr_rdata_i, ++ input logic [6:0] instr_rdata_intg_i, ++ input logic instr_err_i, + + // Data memory interface +- output logic data_req_o, +- input logic data_gnt_i, +- input logic data_rvalid_i, +- output logic data_we_o, +- output logic [3:0] data_be_o, +- output logic [31:0] data_addr_o, +- output logic [31:0] data_wdata_o, +- output logic [6:0] data_wdata_intg_o, +- input logic [31:0] data_rdata_i, +- input logic [6:0] data_rdata_intg_i, +- input logic data_err_i, ++ output logic data_req_o, ++ input logic data_gnt_i, ++ input logic data_rvalid_i, ++ output logic data_we_o, ++ output logic [3:0] data_be_o, ++ output logic [31:0] data_addr_o, ++ output logic [31:0] data_wdata_o, ++ output logic [6:0] data_wdata_intg_o, ++ input logic [31:0] data_rdata_i, ++ input logic [6:0] data_rdata_intg_i, ++ input logic data_err_i, + + // Interrupt inputs +- input logic irq_software_i, +- input logic irq_timer_i, +- input logic irq_external_i, +- input logic [14:0] irq_fast_i, +- input logic irq_nm_i, // non-maskeable interrupt ++ input logic irq_software_i, ++ input logic irq_timer_i, ++ input logic irq_external_i, ++ input logic [14:0] irq_fast_i, ++ // non-maskeable interrupt ++ input logic irq_nm_i, + + // Scrambling Interface +- input logic scramble_key_valid_i, +- input logic [SCRAMBLE_KEY_W-1:0] scramble_key_i, +- input logic [SCRAMBLE_NONCE_W-1:0] scramble_nonce_i, +- output logic scramble_req_o, ++ input logic scramble_key_valid_i, ++ input logic [SCRAMBLE_KEY_W-1:0] scramble_key_i, ++ input logic [SCRAMBLE_NONCE_W-1:0] scramble_nonce_i, ++ output logic scramble_req_o, + + // Debug Interface +- input logic debug_req_i, +- output crash_dump_t crash_dump_o, +- output logic double_fault_seen_o, ++ input logic debug_req_i, ++ output crash_dump_t crash_dump_o, ++ output logic double_fault_seen_o, + + // RISC-V Formal Interface + // Does not comply with the coding standards of _i/_o suffixes, but follows + // the convention of RISC-V Formal Interface Specification. + `ifdef RVFI +- output logic rvfi_valid, +- output logic [63:0] rvfi_order, +- output logic [31:0] rvfi_insn, +- output logic rvfi_trap, +- output logic rvfi_halt, +- output logic rvfi_intr, +- output logic [ 1:0] rvfi_mode, +- output logic [ 1:0] rvfi_ixl, +- output logic [ 4:0] rvfi_rs1_addr, +- output logic [ 4:0] rvfi_rs2_addr, +- output logic [ 4:0] rvfi_rs3_addr, +- output logic [31:0] rvfi_rs1_rdata, +- output logic [31:0] rvfi_rs2_rdata, +- output logic [31:0] rvfi_rs3_rdata, +- output logic [ 4:0] rvfi_rd_addr, +- output logic [31:0] rvfi_rd_wdata, +- output logic [31:0] rvfi_pc_rdata, +- output logic [31:0] rvfi_pc_wdata, +- output logic [31:0] rvfi_mem_addr, +- output logic [ 3:0] rvfi_mem_rmask, +- output logic [ 3:0] rvfi_mem_wmask, +- output logic [31:0] rvfi_mem_rdata, +- output logic [31:0] rvfi_mem_wdata, +- output logic [31:0] rvfi_ext_pre_mip, +- output logic [31:0] rvfi_ext_post_mip, +- output logic rvfi_ext_nmi, +- output logic rvfi_ext_nmi_int, +- output logic rvfi_ext_debug_req, +- output logic rvfi_ext_debug_mode, +- output logic rvfi_ext_rf_wr_suppress, +- output logic [63:0] rvfi_ext_mcycle, +- output logic [31:0] rvfi_ext_mhpmcounters [10], +- output logic [31:0] rvfi_ext_mhpmcountersh [10], +- output logic rvfi_ext_ic_scr_key_valid, +- output logic rvfi_ext_irq_valid, ++ output logic rvfi_valid, ++ output logic [63:0] rvfi_order, ++ output logic [31:0] rvfi_insn, ++ output logic rvfi_trap, ++ output logic rvfi_halt, ++ output logic rvfi_intr, ++ output logic [ 1:0] rvfi_mode, ++ output logic [ 1:0] rvfi_ixl, ++ output logic [ 4:0] rvfi_rs1_addr, ++ output logic [ 4:0] rvfi_rs2_addr, ++ output logic [ 4:0] rvfi_rs3_addr, ++ output logic [31:0] rvfi_rs1_rdata, ++ output logic [31:0] rvfi_rs2_rdata, ++ output logic [31:0] rvfi_rs3_rdata, ++ output logic [ 4:0] rvfi_rd_addr, ++ output logic [31:0] rvfi_rd_wdata, ++ output logic [31:0] rvfi_pc_rdata, ++ output logic [31:0] rvfi_pc_wdata, ++ output logic [31:0] rvfi_mem_addr, ++ output logic [ 3:0] rvfi_mem_rmask, ++ output logic [ 3:0] rvfi_mem_wmask, ++ output logic [31:0] rvfi_mem_rdata, ++ output logic [31:0] rvfi_mem_wdata, ++ output logic [31:0] rvfi_ext_pre_mip, ++ output logic [31:0] rvfi_ext_post_mip, ++ output logic rvfi_ext_nmi, ++ output logic rvfi_ext_nmi_int, ++ output logic rvfi_ext_debug_req, ++ output logic rvfi_ext_debug_mode, ++ output logic rvfi_ext_rf_wr_suppress, ++ output logic [63:0] rvfi_ext_mcycle, ++ output logic [31:0] rvfi_ext_mhpmcounters [10], ++ output logic [31:0] rvfi_ext_mhpmcountersh [10], ++ output logic rvfi_ext_ic_scr_key_valid, ++ output logic rvfi_ext_irq_valid, + `endif + + // CPU Control Signals +- input ibex_mubi_t fetch_enable_i, +- output logic alert_minor_o, +- output logic alert_major_internal_o, +- output logic alert_major_bus_o, +- output logic core_sleep_o, ++ input ibex_mubi_t fetch_enable_i, ++ output logic alert_minor_o, ++ output logic alert_major_internal_o, ++ output logic alert_major_bus_o, ++ output logic core_sleep_o, + + // DFT bypass controls +- input logic scan_rst_ni ++ input logic scan_rst_ni + ); + + localparam bit Lockstep = SecureIbex; +@@ -603,7 +608,8 @@ module ibex_top import ibex_pkg::*; #( + .rvalid_o (), + .raddr_o (), + .rerror_o (), +- .cfg_i (ram_cfg_i), ++ .cfg_i (ram_cfg_icache_tag_i), ++ .cfg_rsp_o (ram_cfg_rsp_icache_tag_o[way]), + .wr_collision_o (), + .write_pending_o (), + +@@ -640,7 +646,8 @@ module ibex_top import ibex_pkg::*; #( + .rvalid_o (), + .raddr_o (), + .rerror_o (), +- .cfg_i (ram_cfg_i), ++ .cfg_i (ram_cfg_icache_data_i), ++ .cfg_rsp_o (ram_cfg_rsp_icache_data_o[way]), + .wr_collision_o (), + .write_pending_o (), + +@@ -695,7 +702,8 @@ module ibex_top import ibex_pkg::*; #( + .wmask_i ({TagSizeECC{1'b1}}), + + .rdata_o (ic_tag_rdata[way]), +- .cfg_i (ram_cfg_i) ++ .cfg_i (ram_cfg_icache_tag_i), ++ .cfg_rsp_o (ram_cfg_rsp_icache_tag_o[way]) + ); + + // Data RAM instantiation +@@ -714,7 +722,8 @@ module ibex_top import ibex_pkg::*; #( + .wmask_i ({LineSizeECC{1'b1}}), + + .rdata_o (ic_data_rdata[way]), +- .cfg_i (ram_cfg_i) ++ .cfg_i (ram_cfg_icache_data_i), ++ .cfg_rsp_o (ram_cfg_rsp_icache_data_o[way]) + ); + + assign icache_tag_alert = '{default:'b0}; +@@ -727,7 +736,9 @@ module ibex_top import ibex_pkg::*; #( + prim_ram_1p_pkg::ram_1p_cfg_t unused_ram_cfg; + logic unused_ram_inputs; + +- assign unused_ram_cfg = ram_cfg_i; ++ assign unused_ram_cfg = |{ram_cfg_icache_tag_i, ram_cfg_icache_data_i}; ++ assign ram_cfg_rsp_icache_tag_o = '0; ++ assign ram_cfg_rsp_icache_data_o = '0; + assign unused_ram_inputs = (|ic_tag_req) & ic_tag_write & (|ic_tag_addr) & (|ic_tag_wdata) & + (|ic_data_req) & ic_data_write & (|ic_data_addr) & (|ic_data_wdata) & + (|scramble_key_q) & (|scramble_nonce_q) & scramble_key_valid_q & +@@ -1147,7 +1158,8 @@ module ibex_top import ibex_pkg::*; #( + + // X check for top-level inputs + `ASSERT_KNOWN(IbexTestEnX, test_en_i) +- `ASSERT_KNOWN(IbexRamCfgX, ram_cfg_i) ++ `ASSERT_KNOWN(IbexRamCfgTagX, ram_cfg_icache_tag_i) ++ `ASSERT_KNOWN(IbexRamCfgDataX, ram_cfg_icache_data_i) + `ASSERT_KNOWN(IbexHartIdX, hart_id_i) + `ASSERT_KNOWN(IbexBootAddrX, boot_addr_i) + +-- +2.47.0 +