From c0e02864c3c46d6841b1bdec3c5b8e5d3abbf09f Mon Sep 17 00:00:00 2001 From: Timothy Trippel Date: Sat, 25 Sep 2021 06:45:26 +0000 Subject: [PATCH] [dif/gpio] migrate srcs to use autogen'd IRQ DIFs This partially addresses #8142. Signed-off-by: Timothy Trippel --- sw/device/boot_rom/bootstrap.c | 7 +- sw/device/examples/demos.c | 10 +- .../examples/hello_usbdev/hello_usbdev.c | 12 +- sw/device/examples/hello_world/hello_world.c | 10 +- sw/device/lib/dif/autogen/meson.build | 14 + sw/device/lib/dif/dif_base.h | 8 +- sw/device/lib/dif/dif_gpio.c | 351 +++++------------- sw/device/lib/dif/dif_gpio.h | 237 ++---------- sw/device/lib/dif/dif_gpio_unittest.cc | 217 ++++------- sw/device/lib/dif/meson.build | 7 +- sw/device/sca/lib/sca.c | 5 +- sw/device/tests/gpio_smoketest.c | 13 +- sw/device/tests/sim_dv/gpio_test.c | 45 ++- 13 files changed, 260 insertions(+), 676 deletions(-) diff --git a/sw/device/boot_rom/bootstrap.c b/sw/device/boot_rom/bootstrap.c index d84f3f87c8674..6f442fb59ed36 100644 --- a/sw/device/boot_rom/bootstrap.c +++ b/sw/device/boot_rom/bootstrap.c @@ -38,12 +38,11 @@ static bool bootstrap_requested(void) { // Initialize GPIO device. dif_gpio_t gpio; - dif_gpio_params_t gpio_params = { - .base_addr = mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR)}; - CHECK(dif_gpio_init(gpio_params, &gpio) == kDifGpioOk); + CHECK(dif_gpio_init(mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR), + &gpio) == kDifOk); dif_gpio_state_t gpio_in; - CHECK(dif_gpio_read_all(&gpio, &gpio_in) == kDifGpioOk); + CHECK(dif_gpio_read_all(&gpio, &gpio_in) == kDifOk); return (gpio_in & GPIO_BOOTSTRAP_BIT_MASK) != 0; } diff --git a/sw/device/examples/demos.c b/sw/device/examples/demos.c index bb5db563f9471..802f9e2adbb54 100644 --- a/sw/device/examples/demos.c +++ b/sw/device/examples/demos.c @@ -18,12 +18,12 @@ void demo_gpio_startup(dif_gpio_t *gpio) { LOG_INFO("Watch the LEDs!"); // Give a LED pattern as startup indicator for 5 seconds. - CHECK(dif_gpio_write_all(gpio, 0xff00) == kDifGpioOk); + CHECK(dif_gpio_write_all(gpio, 0xff00) == kDifOk); for (int i = 0; i < 32; ++i) { usleep(5 * 1000); // 5 ms - CHECK(dif_gpio_write(gpio, 8 + (i % 8), (i / 8) % 2) == kDifGpioOk); + CHECK(dif_gpio_write(gpio, 8 + (i % 8), (i / 8) % 2) == kDifOk); } - CHECK(dif_gpio_write_all(gpio, 0x0000) == kDifGpioOk); // All LEDs off. + CHECK(dif_gpio_write_all(gpio, 0x0000) == kDifOk); // All LEDs off. } /** @@ -39,7 +39,7 @@ static const uint32_t kFtdiMask = 0x10000; uint32_t demo_gpio_to_log_echo(dif_gpio_t *gpio, uint32_t prev_gpio_state) { uint32_t gpio_state; - CHECK(dif_gpio_read_all(gpio, &gpio_state) == kDifGpioOk); + CHECK(dif_gpio_read_all(gpio, &gpio_state) == kDifOk); gpio_state &= kGpioMask; uint32_t state_delta = prev_gpio_state ^ gpio_state; @@ -86,6 +86,6 @@ void demo_uart_to_uart_and_gpio_echo(dif_uart_t *uart, dif_gpio_t *gpio) { uint8_t rcv_char; CHECK(dif_uart_bytes_receive(uart, 1, &rcv_char, NULL) == kDifOk); CHECK(dif_uart_byte_send_polled(uart, rcv_char) == kDifOk); - CHECK(dif_gpio_write_all(gpio, rcv_char << 8) == kDifGpioOk); + CHECK(dif_gpio_write_all(gpio, rcv_char << 8) == kDifOk); } } diff --git a/sw/device/examples/hello_usbdev/hello_usbdev.c b/sw/device/examples/hello_usbdev/hello_usbdev.c index 576ec67c15a45..0c808c50dc474 100644 --- a/sw/device/examples/hello_usbdev/hello_usbdev.c +++ b/sw/device/examples/hello_usbdev/hello_usbdev.c @@ -137,12 +137,10 @@ int main(int argc, char **argv) { .tx_fifo_len = kDifSpiDeviceBufferLen / 2, }) == kDifSpiDeviceOk); - dif_gpio_params_t gpio_params = { - .base_addr = mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR), - }; - CHECK(dif_gpio_init(gpio_params, &gpio) == kDifGpioOk); + CHECK(dif_gpio_init(mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR), + &gpio) == kDifOk); // Enable GPIO: 0-7 and 16 is input; 8-15 is output. - CHECK(dif_gpio_output_set_enabled_all(&gpio, 0x0ff00) == kDifGpioOk); + CHECK(dif_gpio_output_set_enabled_all(&gpio, 0x0ff00) == kDifOk); LOG_INFO("Hello, USB!"); LOG_INFO("Built at: " __DATE__ ", " __TIME__); @@ -153,7 +151,7 @@ int main(int argc, char **argv) { // simulation has finished all of the printing, which takes a while // if `--trace` was passed in. uint32_t gpio_state; - CHECK(dif_gpio_read_all(&gpio, &gpio_state) == kDifGpioOk); + CHECK(dif_gpio_read_all(&gpio, &gpio_state) == kDifOk); bool pinflip = gpio_state & kPinflipMask ? true : false; bool differential = gpio_state & kDiffMask ? true : false; bool uphy = gpio_state & kUPhyMask ? true : false; @@ -189,7 +187,7 @@ int main(int argc, char **argv) { CHECK(dif_uart_bytes_receive(&uart, 1, &rcv_char, NULL) == kDifOk); CHECK(dif_uart_byte_send_polled(&uart, rcv_char) == kDifOk); - CHECK(dif_gpio_write_all(&gpio, rcv_char << 8) == kDifGpioOk); + CHECK(dif_gpio_write_all(&gpio, rcv_char << 8) == kDifOk); if (rcv_char == '/') { uint32_t usb_irq_state = diff --git a/sw/device/examples/hello_world/hello_world.c b/sw/device/examples/hello_world/hello_world.c index c4c555d3ad04e..593c4e954302b 100644 --- a/sw/device/examples/hello_world/hello_world.c +++ b/sw/device/examples/hello_world/hello_world.c @@ -50,12 +50,10 @@ int main(int argc, char **argv) { .tx_fifo_len = kDifSpiDeviceBufferLen / 2, }) == kDifSpiDeviceOk); - dif_gpio_params_t gpio_params = { - .base_addr = mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR), - }; - CHECK(dif_gpio_init(gpio_params, &gpio) == kDifGpioOk); + CHECK(dif_gpio_init(mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR), + &gpio) == kDifOk); // Enable GPIO: 0-7 and 16 is input; 8-15 is output. - CHECK(dif_gpio_output_set_enabled_all(&gpio, 0x0ff00) == kDifGpioOk); + CHECK(dif_gpio_output_set_enabled_all(&gpio, 0x0ff00) == kDifOk); // Add DATE and TIME because I keep fooling myself with old versions LOG_INFO("Hello World!"); @@ -65,7 +63,7 @@ int main(int argc, char **argv) { // Now have UART <-> Buttons/LEDs demo // all LEDs off - CHECK(dif_gpio_write_all(&gpio, 0x0000) == kDifGpioOk); + CHECK(dif_gpio_write_all(&gpio, 0x0000) == kDifOk); LOG_INFO("Try out the switches on the board"); LOG_INFO("or type anything into the console window."); LOG_INFO("The LEDs show the ASCII code of the last character."); diff --git a/sw/device/lib/dif/autogen/meson.build b/sw/device/lib/dif/autogen/meson.build index 10968c7bbaa76..b3f9cf58c1558 100644 --- a/sw/device/lib/dif/autogen/meson.build +++ b/sw/device/lib/dif/autogen/meson.build @@ -2,6 +2,20 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 +# Autogen GPIO DIF library +sw_lib_dif_autogen_gpio = declare_dependency( + link_with: static_library( + 'sw_lib_dif_autogen_gpio', + sources: [ + hw_ip_gpio_reg_h, + 'dif_gpio_autogen.c', + ], + dependencies: [ + sw_lib_mmio, + ], + ) +) + # Autogen AES DIF library sw_lib_dif_autogen_aes = declare_dependency( link_with: static_library( diff --git a/sw/device/lib/dif/dif_base.h b/sw/device/lib/dif/dif_base.h index c2a70d5885856..abe0d7a6edba4 100644 --- a/sw/device/lib/dif/dif_base.h +++ b/sw/device/lib/dif/dif_base.h @@ -63,13 +63,13 @@ typedef enum dif_result { */ typedef enum dif_toggle { /** - * The "enabled" state. + * The "disabled" state. */ - kDifToggleEnabled, + kDifToggleDisabled = 0, /** - * The "disabled" state. + * The "enabled" state. */ - kDifToggleDisabled, + kDifToggleEnabled = 1, } dif_toggle_t; #ifdef __cplusplus diff --git a/sw/device/lib/dif/dif_gpio.c b/sw/device/lib/dif/dif_gpio.c index 642ed7c60205a..e0ba6a4831551 100644 --- a/sw/device/lib/dif/dif_gpio.c +++ b/sw/device/lib/dif/dif_gpio.c @@ -37,26 +37,26 @@ static uint32_t index_to_mask(uint32_t index) { return 1u << index; } * @param val Value to write. */ OT_WARN_UNUSED_RESULT -static dif_gpio_result_t gpio_masked_write(const dif_gpio_t *gpio, - ptrdiff_t reg_lower_offset, - ptrdiff_t reg_upper_offset, - uint32_t mask, uint32_t val) { +static dif_result_t gpio_masked_write(const dif_gpio_t *gpio, + ptrdiff_t reg_lower_offset, + ptrdiff_t reg_upper_offset, uint32_t mask, + uint32_t val) { if (gpio == NULL) { - return kDifGpioBadArg; + return kDifBadArg; } const uint32_t mask_lower_half = mask & 0x0000FFFFu; const uint32_t mask_upper_half = mask & 0xFFFF0000u; if (mask_lower_half != 0) { - mmio_region_write32(gpio->params.base_addr, reg_lower_offset, + mmio_region_write32(gpio->base_addr, reg_lower_offset, (mask_lower_half << 16) | (val & 0x0000FFFFu)); } if (mask_upper_half != 0) { - mmio_region_write32(gpio->params.base_addr, reg_upper_offset, + mmio_region_write32(gpio->base_addr, reg_upper_offset, mask_upper_half | ((val & 0xFFFF0000u) >> 16)); } - return kDifGpioOk; + return kDifOk; } /** @@ -79,12 +79,12 @@ static dif_gpio_result_t gpio_masked_write(const dif_gpio_t *gpio, * @param val Value to write. */ OT_WARN_UNUSED_RESULT -static dif_gpio_result_t gpio_masked_bit_write(const dif_gpio_t *gpio, - ptrdiff_t reg_lower_offset, - ptrdiff_t reg_upper_offset, - uint32_t index, bool val) { +static dif_result_t gpio_masked_bit_write(const dif_gpio_t *gpio, + ptrdiff_t reg_lower_offset, + ptrdiff_t reg_upper_offset, + uint32_t index, bool val) { if (gpio == NULL) { - return kDifGpioBadArg; + return kDifBadArg; } // Write to reg_lower_offset if the bit is in the lower half, write to @@ -93,348 +93,195 @@ static dif_gpio_result_t gpio_masked_bit_write(const dif_gpio_t *gpio, // Since masked access writes to half of a register, index mod 16 gives the // index of the bit in the half-word mask. const uint32_t mask = index_to_mask(index % 16); - mmio_region_write32(gpio->params.base_addr, offset, + mmio_region_write32(gpio->base_addr, offset, (mask << 16) | (val ? mask : 0u)); - return kDifGpioOk; + return kDifOk; } -dif_gpio_result_t dif_gpio_init(dif_gpio_params_t params, dif_gpio_t *gpio) { +dif_result_t dif_gpio_init(mmio_region_t base_addr, dif_gpio_t *gpio) { if (gpio == NULL) { - return kDifGpioBadArg; + return kDifBadArg; } - gpio->params = params; + gpio->base_addr = base_addr; - return kDifGpioOk; + return kDifOk; } -dif_gpio_result_t dif_gpio_reset(const dif_gpio_t *gpio) { +dif_result_t dif_gpio_reset(const dif_gpio_t *gpio) { if (gpio == NULL) { - return kDifGpioBadArg; + return kDifBadArg; } // We don't need to write to `GPIO_MASKED_OE_*` and `GPIO_MASKED_OUT_*` // since we directly reset `GPIO_DIRECT_OE` and `GPIO_DIRECT_OUT` below. - mmio_region_write32(gpio->params.base_addr, GPIO_INTR_ENABLE_REG_OFFSET, 0); - mmio_region_write32(gpio->params.base_addr, GPIO_DIRECT_OE_REG_OFFSET, 0); - mmio_region_write32(gpio->params.base_addr, GPIO_DIRECT_OUT_REG_OFFSET, 0); - mmio_region_write32(gpio->params.base_addr, - GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, 0); - mmio_region_write32(gpio->params.base_addr, - GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, 0); - mmio_region_write32(gpio->params.base_addr, - GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, 0); - mmio_region_write32(gpio->params.base_addr, - GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, 0); - mmio_region_write32(gpio->params.base_addr, - GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, 0); + mmio_region_write32(gpio->base_addr, GPIO_INTR_ENABLE_REG_OFFSET, 0); + mmio_region_write32(gpio->base_addr, GPIO_DIRECT_OE_REG_OFFSET, 0); + mmio_region_write32(gpio->base_addr, GPIO_DIRECT_OUT_REG_OFFSET, 0); + mmio_region_write32(gpio->base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, 0); + mmio_region_write32(gpio->base_addr, GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, 0); + mmio_region_write32(gpio->base_addr, GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, 0); + mmio_region_write32(gpio->base_addr, GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, 0); + mmio_region_write32(gpio->base_addr, GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, 0); // Also clear all pending interrupts - mmio_region_write32(gpio->params.base_addr, GPIO_INTR_STATE_REG_OFFSET, - 0xFFFFFFFFu); + mmio_region_write32(gpio->base_addr, GPIO_INTR_STATE_REG_OFFSET, 0xFFFFFFFFu); - return kDifGpioOk; + return kDifOk; } -dif_gpio_result_t dif_gpio_irq_is_pending(const dif_gpio_t *gpio, - dif_gpio_pin_t pin, - bool *is_pending) { - if (gpio == NULL || is_pending == NULL) { - return kDifGpioBadArg; - } - - *is_pending = mmio_region_get_bit32(gpio->params.base_addr, - GPIO_INTR_STATE_REG_OFFSET, pin); - - return kDifGpioOk; -} - -dif_gpio_result_t dif_gpio_irq_is_pending_all(const dif_gpio_t *gpio, - dif_gpio_state_t *is_pending) { - if (gpio == NULL || is_pending == NULL) { - return kDifGpioBadArg; - } - - *is_pending = - mmio_region_read32(gpio->params.base_addr, GPIO_INTR_STATE_REG_OFFSET); - - return kDifGpioOk; -} - -dif_gpio_result_t dif_gpio_irq_acknowledge(const dif_gpio_t *gpio, - dif_gpio_pin_t pin) { - if (gpio == NULL) { - return kDifGpioBadArg; - } - - mmio_region_write32(gpio->params.base_addr, GPIO_INTR_STATE_REG_OFFSET, - index_to_mask(pin)); - - return kDifGpioOk; -} - -dif_gpio_result_t dif_gpio_irq_get_enabled(const dif_gpio_t *gpio, - dif_gpio_pin_t pin, - dif_gpio_toggle_t *state) { - if (gpio == NULL || state == NULL) { - return kDifGpioBadArg; - } - - bool is_enabled = mmio_region_get_bit32(gpio->params.base_addr, - GPIO_INTR_ENABLE_REG_OFFSET, pin); - *state = is_enabled ? kDifGpioToggleEnabled : kDifGpioToggleDisabled; - - return kDifGpioOk; -} - -dif_gpio_result_t dif_gpio_irq_set_enabled(const dif_gpio_t *gpio, - dif_gpio_pin_t pin, - dif_gpio_toggle_t state) { - if (gpio == NULL) { - return kDifGpioBadArg; - } - - switch (state) { - case kDifGpioToggleEnabled: - mmio_region_nonatomic_set_bit32(gpio->params.base_addr, - GPIO_INTR_ENABLE_REG_OFFSET, pin); - break; - case kDifGpioToggleDisabled: - mmio_region_nonatomic_clear_bit32(gpio->params.base_addr, - GPIO_INTR_ENABLE_REG_OFFSET, pin); - break; - default: - return kDifGpioBadArg; - } - - return kDifGpioOk; -} - -dif_gpio_result_t dif_gpio_irq_set_enabled_masked(const dif_gpio_t *gpio, - dif_gpio_mask_t mask, - dif_gpio_toggle_t state) { +dif_result_t dif_gpio_irq_set_trigger(const dif_gpio_t *gpio, + dif_gpio_mask_t mask, + dif_gpio_irq_trigger_t trigger) { if (gpio == NULL) { - return kDifGpioBadArg; - } - - switch (state) { - case kDifGpioToggleEnabled: - mmio_region_nonatomic_set_mask32(gpio->params.base_addr, - GPIO_INTR_ENABLE_REG_OFFSET, mask, 0); - break; - case kDifGpioToggleDisabled: - mmio_region_nonatomic_clear_mask32(gpio->params.base_addr, - GPIO_INTR_ENABLE_REG_OFFSET, mask, 0); - break; - default: - return kDifGpioBadArg; - } - - return kDifGpioOk; -} - -dif_gpio_result_t dif_gpio_irq_force(const dif_gpio_t *gpio, - dif_gpio_pin_t pin) { - if (gpio == NULL) { - return kDifGpioBadArg; - } - - mmio_region_write32(gpio->params.base_addr, GPIO_INTR_TEST_REG_OFFSET, - index_to_mask(pin)); - - return kDifGpioOk; -} - -dif_gpio_result_t dif_gpio_irq_disable_all(const dif_gpio_t *gpio, - dif_gpio_state_t *snapshot) { - if (gpio == NULL) { - return kDifGpioBadArg; - } - - if (snapshot != NULL) { - *snapshot = - mmio_region_read32(gpio->params.base_addr, GPIO_INTR_ENABLE_REG_OFFSET); - } - mmio_region_write32(gpio->params.base_addr, GPIO_INTR_ENABLE_REG_OFFSET, 0); - - return kDifGpioOk; -} - -dif_gpio_result_t dif_gpio_irq_restore_all(const dif_gpio_t *gpio, - const dif_gpio_state_t *snapshot) { - if (gpio == NULL || snapshot == NULL) { - return kDifGpioBadArg; - } - - mmio_region_write32(gpio->params.base_addr, GPIO_INTR_ENABLE_REG_OFFSET, - *snapshot); - - return kDifGpioOk; -} - -dif_gpio_result_t dif_gpio_irq_set_trigger(const dif_gpio_t *gpio, - dif_gpio_mask_t mask, - dif_gpio_irq_trigger_t trigger) { - if (gpio == NULL) { - return kDifGpioBadArg; + return kDifBadArg; } // Disable all interrupt triggers for the given mask. mmio_region_nonatomic_clear_mask32( - gpio->params.base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0); + gpio->base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0); mmio_region_nonatomic_clear_mask32( - gpio->params.base_addr, GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, mask, 0); + gpio->base_addr, GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, mask, 0); mmio_region_nonatomic_clear_mask32( - gpio->params.base_addr, GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, mask, 0); + gpio->base_addr, GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, mask, 0); mmio_region_nonatomic_clear_mask32( - gpio->params.base_addr, GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, mask, 0); + gpio->base_addr, GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, mask, 0); switch (trigger) { case kDifGpioIrqTriggerEdgeRising: mmio_region_nonatomic_set_mask32( - gpio->params.base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0); + gpio->base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0); break; case kDifGpioIrqTriggerEdgeFalling: - mmio_region_nonatomic_set_mask32(gpio->params.base_addr, - GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, - mask, 0); + mmio_region_nonatomic_set_mask32( + gpio->base_addr, GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, mask, 0); break; case kDifGpioIrqTriggerLevelLow: mmio_region_nonatomic_set_mask32( - gpio->params.base_addr, GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, mask, 0); + gpio->base_addr, GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, mask, 0); break; case kDifGpioIrqTriggerLevelHigh: - mmio_region_nonatomic_set_mask32(gpio->params.base_addr, - GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, - mask, 0); + mmio_region_nonatomic_set_mask32( + gpio->base_addr, GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, mask, 0); break; case kDifGpioIrqTriggerEdgeRisingFalling: mmio_region_nonatomic_set_mask32( - gpio->params.base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0); - mmio_region_nonatomic_set_mask32(gpio->params.base_addr, - GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, - mask, 0); + gpio->base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0); + mmio_region_nonatomic_set_mask32( + gpio->base_addr, GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, mask, 0); break; case kDifGpioIrqTriggerEdgeRisingLevelLow: mmio_region_nonatomic_set_mask32( - gpio->params.base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0); + gpio->base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, mask, 0); mmio_region_nonatomic_set_mask32( - gpio->params.base_addr, GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, mask, 0); + gpio->base_addr, GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, mask, 0); break; case kDifGpioIrqTriggerEdgeFallingLevelHigh: - mmio_region_nonatomic_set_mask32(gpio->params.base_addr, - GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, - mask, 0); - mmio_region_nonatomic_set_mask32(gpio->params.base_addr, - GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, - mask, 0); + mmio_region_nonatomic_set_mask32( + gpio->base_addr, GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET, mask, 0); + mmio_region_nonatomic_set_mask32( + gpio->base_addr, GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, mask, 0); break; default: - return kDifGpioError; + return kDifError; } - return kDifGpioOk; + return kDifOk; } -dif_gpio_result_t dif_gpio_read_all(const dif_gpio_t *gpio, - dif_gpio_state_t *state) { +dif_result_t dif_gpio_read_all(const dif_gpio_t *gpio, + dif_gpio_state_t *state) { if (gpio == NULL || state == NULL) { - return kDifGpioBadArg; + return kDifBadArg; } - *state = mmio_region_read32(gpio->params.base_addr, GPIO_DATA_IN_REG_OFFSET); + *state = mmio_region_read32(gpio->base_addr, GPIO_DATA_IN_REG_OFFSET); - return kDifGpioOk; + return kDifOk; } -dif_gpio_result_t dif_gpio_read(const dif_gpio_t *gpio, dif_gpio_pin_t pin, - bool *state) { +dif_result_t dif_gpio_read(const dif_gpio_t *gpio, dif_gpio_pin_t pin, + bool *state) { if (gpio == NULL || state == NULL) { - return kDifGpioBadArg; + return kDifBadArg; } - *state = mmio_region_get_bit32(gpio->params.base_addr, - GPIO_DATA_IN_REG_OFFSET, pin); + *state = mmio_region_get_bit32(gpio->base_addr, GPIO_DATA_IN_REG_OFFSET, pin); - return kDifGpioOk; + return kDifOk; } -dif_gpio_result_t dif_gpio_write_all(const dif_gpio_t *gpio, - dif_gpio_state_t state) { +dif_result_t dif_gpio_write_all(const dif_gpio_t *gpio, + dif_gpio_state_t state) { if (gpio == NULL) { - return kDifGpioBadArg; + return kDifBadArg; } - mmio_region_write32(gpio->params.base_addr, GPIO_DIRECT_OUT_REG_OFFSET, - state); + mmio_region_write32(gpio->base_addr, GPIO_DIRECT_OUT_REG_OFFSET, state); - return kDifGpioOk; + return kDifOk; } -dif_gpio_result_t dif_gpio_write(const dif_gpio_t *gpio, dif_gpio_pin_t pin, - bool state) { +dif_result_t dif_gpio_write(const dif_gpio_t *gpio, dif_gpio_pin_t pin, + bool state) { return gpio_masked_bit_write(gpio, GPIO_MASKED_OUT_LOWER_REG_OFFSET, GPIO_MASKED_OUT_UPPER_REG_OFFSET, pin, state); } -dif_gpio_result_t dif_gpio_write_masked(const dif_gpio_t *gpio, - dif_gpio_mask_t mask, - dif_gpio_state_t state) { +dif_result_t dif_gpio_write_masked(const dif_gpio_t *gpio, dif_gpio_mask_t mask, + dif_gpio_state_t state) { return gpio_masked_write(gpio, GPIO_MASKED_OUT_LOWER_REG_OFFSET, GPIO_MASKED_OUT_UPPER_REG_OFFSET, mask, state); } -dif_gpio_result_t dif_gpio_output_set_enabled_all(const dif_gpio_t *gpio, - dif_gpio_state_t state) { +dif_result_t dif_gpio_output_set_enabled_all(const dif_gpio_t *gpio, + dif_gpio_state_t state) { if (gpio == NULL) { - return kDifGpioBadArg; + return kDifBadArg; } - mmio_region_write32(gpio->params.base_addr, GPIO_DIRECT_OE_REG_OFFSET, state); + mmio_region_write32(gpio->base_addr, GPIO_DIRECT_OE_REG_OFFSET, state); - return kDifGpioOk; + return kDifOk; } -dif_gpio_result_t dif_gpio_output_set_enabled(const dif_gpio_t *gpio, - dif_gpio_pin_t pin, - dif_gpio_toggle_t state) { +dif_result_t dif_gpio_output_set_enabled(const dif_gpio_t *gpio, + dif_gpio_pin_t pin, + dif_toggle_t state) { if (gpio == NULL) { - return kDifGpioBadArg; + return kDifBadArg; } return gpio_masked_bit_write(gpio, GPIO_MASKED_OE_LOWER_REG_OFFSET, GPIO_MASKED_OE_UPPER_REG_OFFSET, pin, state); - - return kDifGpioOk; } -dif_gpio_result_t dif_gpio_output_set_enabled_masked(const dif_gpio_t *gpio, - dif_gpio_mask_t mask, - dif_gpio_state_t state) { +dif_result_t dif_gpio_output_set_enabled_masked(const dif_gpio_t *gpio, + dif_gpio_mask_t mask, + dif_gpio_state_t state) { return gpio_masked_write(gpio, GPIO_MASKED_OE_LOWER_REG_OFFSET, GPIO_MASKED_OE_UPPER_REG_OFFSET, mask, state); } -dif_gpio_result_t dif_gpio_input_noise_filter_set_enabled( - const dif_gpio_t *gpio, dif_gpio_mask_t mask, dif_gpio_toggle_t state) { +dif_result_t dif_gpio_input_noise_filter_set_enabled(const dif_gpio_t *gpio, + dif_gpio_mask_t mask, + dif_toggle_t state) { if (gpio == NULL) { - return kDifGpioBadArg; + return kDifBadArg; } switch (state) { - case kDifGpioToggleEnabled: - mmio_region_nonatomic_set_mask32(gpio->params.base_addr, - GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, - mask, 0); + case kDifToggleEnabled: + mmio_region_nonatomic_set_mask32( + gpio->base_addr, GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, mask, 0); break; - case kDifGpioToggleDisabled: - mmio_region_nonatomic_clear_mask32(gpio->params.base_addr, - GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, - mask, 0); + case kDifToggleDisabled: + mmio_region_nonatomic_clear_mask32( + gpio->base_addr, GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, mask, 0); break; default: - return kDifGpioBadArg; + return kDifBadArg; } - return kDifGpioOk; + return kDifOk; } diff --git a/sw/device/lib/dif/dif_gpio.h b/sw/device/lib/dif/dif_gpio.h index f8a10d8e0a42f..1a1c789d0b69c 100644 --- a/sw/device/lib/dif/dif_gpio.h +++ b/sw/device/lib/dif/dif_gpio.h @@ -15,76 +15,14 @@ #include "sw/device/lib/base/macros.h" #include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/dif_base.h" + +#include "sw/device/lib/dif/autogen/dif_gpio_autogen.h" #ifdef __cplusplus extern "C" { #endif // __cplusplus -/** - * A toggle state: enabled, or disabled. - * - * This enum may be used instead of a `bool` when describing an enabled/disabled - * state. - * - * This enum may be used with `dif_gpio_toggle_vec_t` to set individual bits - * within it; `dif_gpio_toggle_t`'s variants are guaranteed to be compatible - * with `dif_gpio_toggle_vec_t`. - */ -typedef enum dif_gpio_toggle { - /* - * The "enabled" state. - */ - kDifGpioToggleEnabled = true, - /** - * The "disabled" state. - */ - kDifGpioToggleDisabled = false, -} dif_gpio_toggle_t; - -/** - * Hardware instantiation parameters for GPIO. - * - * This struct describes information about the underlying hardware that is - * not determined until the hardware design is used as part of a top-level - * design. - */ -typedef struct dif_gpio_params { - /** - * The base address for the GPIO hardware registers. - */ - mmio_region_t base_addr; -} dif_gpio_params_t; - -/** - * A handle to GPIO. - * - * This type should be treated as opaque by users. - */ -typedef struct dif_gpio { - dif_gpio_params_t params; -} dif_gpio_t; - -/** - * The result of a GPIO operation. - */ -typedef enum dif_gpio_result { - /** - * Indicates that the operation succeeded. - */ - kDifGpioOk = 0, - /** - * Indicates some unspecified failure. - */ - kDifGpioError = 1, - /** - * Indicates that some parameter passed into a function failed a - * precondition. - * - * When this value is returned, no hardware operations occurred. - */ - kDifGpioBadArg = 2, -} dif_gpio_result_t; - /** * A GPIO interrupt request trigger. * @@ -137,12 +75,9 @@ typedef uint32_t dif_gpio_pin_t; * * The Nth bit represents the state of the Nth pin. * - * This type is also used as a vector of `dif_gpio_toggle_t`s, to indicate + * This type is also used as a vector of `dif_toggle_t`s, to indicate * toggle state across all 32 pins. A set bit corresponds to * `kDifGpioToggleEnabled`. - * - * It is also used with `dif_gpio_irq_disable_all()` and - * `dif_gpio_irq_restore_all()`. */ typedef uint32_t dif_gpio_state_t; @@ -163,7 +98,7 @@ typedef uint32_t dif_gpio_mask_t; * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_init(dif_gpio_params_t params, dif_gpio_t *gpio); +dif_result_t dif_gpio_init(mmio_region_t base_addr, dif_gpio_t *gpio); /** * Resets a GPIO device. @@ -175,121 +110,7 @@ dif_gpio_result_t dif_gpio_init(dif_gpio_params_t params, dif_gpio_t *gpio); * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_reset(const dif_gpio_t *gpio); - -/** - * Returns whether a particular pin's interrupt is currently pending. - * - * @param gpio A GPIO handle. - * @param pin A GPIO pin. - * @param[out] is_pending Out-param for whether the interrupt is pending. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_irq_is_pending(const dif_gpio_t *gpio, - dif_gpio_pin_t pin, bool *is_pending); - -/** - * Returns a GPIO state representing which pins have interrupts enabled. - * - * @param gpio A GPIO handle. - * @param[out] is_pending Out-param for which interrupts are pending. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_irq_is_pending_all(const dif_gpio_t *gpio, - dif_gpio_state_t *is_pending); - -/** - * Acknowledges a particular pin's interrupt, indicating to the hardware that it - * has - * been successfully serviced. - * - * @param gpio A GPIO handle. - * @param pin A GPIO pin. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_irq_acknowledge(const dif_gpio_t *gpio, - dif_gpio_pin_t pin); - -/** - * Checks whether a particular pin's interrupt is currently enabled or disabled. - * - * @param gpio A GPIO handle. - * @param pin A GPIO pin. - * @param[out] state Out-param toggle state of the interrupt. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_irq_get_enabled(const dif_gpio_t *gpio, - dif_gpio_pin_t pin, - dif_gpio_toggle_t *state); - -/** - * Sets whether a particular pin's interrupt is currently enabled or disabled. - * - * @param gpio A GPIO handle. - * @param pin A GPIO pin. - * @param state The new toggle state for the interrupt. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_irq_set_enabled(const dif_gpio_t *gpio, - dif_gpio_pin_t pin, - dif_gpio_toggle_t state); - -/** - * Sets whether a particular pin's interrupt is currently enabled or disabled. - * - * @param gpio A GPIO handle. - * @param mask Mask that identifies the pins whose interrupt triggers will be - * configured. - * @param state The new toggle state for the interrupt. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_irq_set_enabled_masked(const dif_gpio_t *gpio, - dif_gpio_mask_t mask, - dif_gpio_toggle_t state); - -/** - * Forces a particular pin's interrupt, causing it to be serviced as if hardware - * had asserted it. - * - * @param gpio A GPIO handle. - * @param pin A GPIO pin. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_irq_force(const dif_gpio_t *gpio, - dif_gpio_pin_t pin); - -/** - * Disables all interrupts, optionally snapshotting all toggle state for later - * restoration. - * - * @param gpio A GPIO handle. - * @param[out] snapshot Out-param for the snapshot; may be `NULL`. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_irq_disable_all(const dif_gpio_t *gpio, - dif_gpio_state_t *snapshot); - -/** - * Restores interrupts from the given snapshot. - * - * This function can be used with `dif_gpio_irq_disable_all()` to temporary - * interrupt save-and-restore. - * - * @param gpio A GPIO handle. - * @param snapshot A snapshot to restore from. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_irq_restore_all(const dif_gpio_t *gpio, - const dif_gpio_state_t *snapshot); +dif_result_t dif_gpio_reset(const dif_gpio_t *gpio); /** * Configures interrupt triggers for a set of pins. @@ -305,9 +126,9 @@ dif_gpio_result_t dif_gpio_irq_restore_all(const dif_gpio_t *gpio, * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_irq_set_trigger(const dif_gpio_t *gpio, - dif_gpio_mask_t mask, - dif_gpio_irq_trigger_t trigger); +dif_result_t dif_gpio_irq_set_trigger(const dif_gpio_t *gpio, + dif_gpio_mask_t mask, + dif_gpio_irq_trigger_t trigger); /** * Reads from a pin. @@ -322,8 +143,8 @@ dif_gpio_result_t dif_gpio_irq_set_trigger(const dif_gpio_t *gpio, * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_read(const dif_gpio_t *gpio, dif_gpio_pin_t pin, - bool *state); +dif_result_t dif_gpio_read(const dif_gpio_t *gpio, dif_gpio_pin_t pin, + bool *state); /** * Reads from all pins. @@ -337,8 +158,7 @@ dif_gpio_result_t dif_gpio_read(const dif_gpio_t *gpio, dif_gpio_pin_t pin, * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_read_all(const dif_gpio_t *gpio, - dif_gpio_state_t *state); +dif_result_t dif_gpio_read_all(const dif_gpio_t *gpio, dif_gpio_state_t *state); /** * Writes to a pin. @@ -351,8 +171,8 @@ dif_gpio_result_t dif_gpio_read_all(const dif_gpio_t *gpio, * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_write(const dif_gpio_t *gpio, dif_gpio_pin_t pin, - bool state); +dif_result_t dif_gpio_write(const dif_gpio_t *gpio, dif_gpio_pin_t pin, + bool state); /** * Writes to all pins. @@ -364,8 +184,7 @@ dif_gpio_result_t dif_gpio_write(const dif_gpio_t *gpio, dif_gpio_pin_t pin, * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_write_all(const dif_gpio_t *gpio, - dif_gpio_state_t state); +dif_result_t dif_gpio_write_all(const dif_gpio_t *gpio, dif_gpio_state_t state); /** * Writes to the pins identified by a mask. @@ -378,9 +197,8 @@ dif_gpio_result_t dif_gpio_write_all(const dif_gpio_t *gpio, * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_write_masked(const dif_gpio_t *gpio, - dif_gpio_mask_t mask, - dif_gpio_state_t state); +dif_result_t dif_gpio_write_masked(const dif_gpio_t *gpio, dif_gpio_mask_t mask, + dif_gpio_state_t state); /** * Sets output enable mode of a pin. @@ -391,9 +209,9 @@ dif_gpio_result_t dif_gpio_write_masked(const dif_gpio_t *gpio, * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_output_set_enabled(const dif_gpio_t *gpio, - dif_gpio_pin_t pin, - dif_gpio_toggle_t state); +dif_result_t dif_gpio_output_set_enabled(const dif_gpio_t *gpio, + dif_gpio_pin_t pin, + dif_toggle_t state); /** * Sets output modes of all pins. @@ -403,8 +221,8 @@ dif_gpio_result_t dif_gpio_output_set_enabled(const dif_gpio_t *gpio, * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_output_set_enabled_all(const dif_gpio_t *gpio, - dif_gpio_state_t state); +dif_result_t dif_gpio_output_set_enabled_all(const dif_gpio_t *gpio, + dif_gpio_state_t state); /** * Sets the output modes of the pins identified by a mask. @@ -415,9 +233,9 @@ dif_gpio_result_t dif_gpio_output_set_enabled_all(const dif_gpio_t *gpio, * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_output_set_enabled_masked(const dif_gpio_t *gpio, - dif_gpio_mask_t mask, - dif_gpio_state_t state); +dif_result_t dif_gpio_output_set_enabled_masked(const dif_gpio_t *gpio, + dif_gpio_mask_t mask, + dif_gpio_state_t state); /** * Enable noise filter for GPIO inputs. @@ -431,8 +249,9 @@ dif_gpio_result_t dif_gpio_output_set_enabled_masked(const dif_gpio_t *gpio, * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -dif_gpio_result_t dif_gpio_input_noise_filter_set_enabled( - const dif_gpio_t *gpio, dif_gpio_mask_t mask, dif_gpio_toggle_t state); +dif_result_t dif_gpio_input_noise_filter_set_enabled(const dif_gpio_t *gpio, + dif_gpio_mask_t mask, + dif_toggle_t state); #ifdef __cplusplus } // extern "C" diff --git a/sw/device/lib/dif/dif_gpio_unittest.cc b/sw/device/lib/dif/dif_gpio_unittest.cc index 8cc7dbffa50e7..61508f42a0310 100644 --- a/sw/device/lib/dif/dif_gpio_unittest.cc +++ b/sw/device/lib/dif/dif_gpio_unittest.cc @@ -23,36 +23,31 @@ uint32_t AllZerosExcept(uint32_t index) { return 1 << index; } uint32_t AllOnesExcept(uint32_t index) { return ~AllZerosExcept(index); } // Base class for the test fixtures in this file. -class DifGpioTest : public testing::Test, public mock_mmio::MmioTest {}; +class GpioTest : public testing::Test, public mock_mmio::MmioTest {}; // Init tests -class InitTest : public DifGpioTest {}; +class InitTest : public GpioTest {}; TEST_F(InitTest, NullArgs) { - dif_gpio_params_t params{.base_addr = dev().region()}; - - EXPECT_EQ(dif_gpio_init(params, nullptr), kDifGpioBadArg); + EXPECT_EQ(dif_gpio_init(dev().region(), nullptr), kDifBadArg); } TEST_F(InitTest, Init) { - dif_gpio_params_t params{.base_addr = dev().region()}; dif_gpio_t gpio; - EXPECT_EQ(dif_gpio_init(params, &gpio), kDifGpioOk); + EXPECT_EQ(dif_gpio_init(dev().region(), &gpio), kDifOk); } // Base class for the rest of the tests in this file, provides a // `dif_gpio_t` instance. -class DifGpioTestInitialized : public DifGpioTest { +class GpioTestInitialized : public GpioTest { protected: - const dif_gpio_t gpio_ = {.params = {.base_addr = dev().region()}}; + const dif_gpio_t gpio_ = {.base_addr = dev().region()}; }; // Reset tests -class ResetTest : public DifGpioTestInitialized {}; +class ResetTest : public GpioTestInitialized {}; -TEST_F(ResetTest, NullArgs) { - EXPECT_EQ(dif_gpio_reset(nullptr), kDifGpioBadArg); -} +TEST_F(ResetTest, NullArgs) { EXPECT_EQ(dif_gpio_reset(nullptr), kDifBadArg); } TEST_F(ResetTest, Reset) { EXPECT_WRITE32(GPIO_INTR_ENABLE_REG_OFFSET, 0); @@ -65,23 +60,23 @@ TEST_F(ResetTest, Reset) { EXPECT_WRITE32(GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, 0); EXPECT_WRITE32(GPIO_INTR_STATE_REG_OFFSET, kAllOnes); - EXPECT_EQ(dif_gpio_reset(&gpio_), kDifGpioOk); + EXPECT_EQ(dif_gpio_reset(&gpio_), kDifOk); } // Read tests -class ReadTest : public DifGpioTestInitialized {}; +class ReadTest : public GpioTestInitialized {}; TEST_F(ReadTest, NullArgs) { dif_gpio_state_t out_arg_uint32_t; bool out_arg_bool; - EXPECT_EQ(dif_gpio_read_all(nullptr, &out_arg_uint32_t), kDifGpioBadArg); - EXPECT_EQ(dif_gpio_read_all(&gpio_, nullptr), kDifGpioBadArg); - EXPECT_EQ(dif_gpio_read_all(nullptr, nullptr), kDifGpioBadArg); + EXPECT_EQ(dif_gpio_read_all(nullptr, &out_arg_uint32_t), kDifBadArg); + EXPECT_EQ(dif_gpio_read_all(&gpio_, nullptr), kDifBadArg); + EXPECT_EQ(dif_gpio_read_all(nullptr, nullptr), kDifBadArg); - EXPECT_EQ(dif_gpio_read(nullptr, 0, &out_arg_bool), kDifGpioBadArg); - EXPECT_EQ(dif_gpio_read(&gpio_, 0, nullptr), kDifGpioBadArg); - EXPECT_EQ(dif_gpio_read(nullptr, 0, nullptr), kDifGpioBadArg); + EXPECT_EQ(dif_gpio_read(nullptr, 0, &out_arg_bool), kDifBadArg); + EXPECT_EQ(dif_gpio_read(&gpio_, 0, nullptr), kDifBadArg); + EXPECT_EQ(dif_gpio_read(nullptr, 0, nullptr), kDifBadArg); } TEST_F(ReadTest, AllPins) { @@ -89,7 +84,7 @@ TEST_F(ReadTest, AllPins) { EXPECT_READ32(GPIO_DATA_IN_REG_OFFSET, kVal); dif_gpio_state_t pin_values = 0; - EXPECT_EQ(dif_gpio_read_all(&gpio_, &pin_values), kDifGpioOk); + EXPECT_EQ(dif_gpio_read_all(&gpio_, &pin_values), kDifOk); EXPECT_EQ(pin_values, kVal); } @@ -101,26 +96,26 @@ TEST_F(ReadTest, SinglePin) { EXPECT_READ32(GPIO_DATA_IN_REG_OFFSET, reg_val); bool pin_val = !exp_pin_val; - EXPECT_EQ(dif_gpio_read(&gpio_, pin, &pin_val), kDifGpioOk); + EXPECT_EQ(dif_gpio_read(&gpio_, pin, &pin_val), kDifOk); EXPECT_EQ(pin_val, exp_pin_val); } } } // Write tests -class WriteTest : public DifGpioTestInitialized {}; +class WriteTest : public GpioTestInitialized {}; TEST_F(WriteTest, NullArgs) { - EXPECT_EQ(dif_gpio_write_all(nullptr, kAllOnes), kDifGpioBadArg); - EXPECT_EQ(dif_gpio_write(nullptr, 0, true), kDifGpioBadArg); - EXPECT_EQ(dif_gpio_write_masked(nullptr, kAllOnes, kAllOnes), kDifGpioBadArg); + EXPECT_EQ(dif_gpio_write_all(nullptr, kAllOnes), kDifBadArg); + EXPECT_EQ(dif_gpio_write(nullptr, 0, true), kDifBadArg); + EXPECT_EQ(dif_gpio_write_masked(nullptr, kAllOnes, kAllOnes), kDifBadArg); } TEST_F(WriteTest, AllPins) { constexpr uint32_t kVal = 0xA5A5A5A5; EXPECT_WRITE32(GPIO_DIRECT_OUT_REG_OFFSET, kVal); - EXPECT_EQ(dif_gpio_write_all(&gpio_, kVal), kDifGpioOk); + EXPECT_EQ(dif_gpio_write_all(&gpio_, kVal), kDifOk); } // The GPIO device provides masked bit-level atomic writes to its DIRECT_OUT @@ -145,91 +140,89 @@ TEST_F(WriteTest, AllPins) { TEST_F(WriteTest, SinglePin) { EXPECT_WRITE32(GPIO_MASKED_OUT_LOWER_REG_OFFSET, {{16, 1}, {0, 1}}); - EXPECT_EQ(dif_gpio_write(&gpio_, 0, true), kDifGpioOk); + EXPECT_EQ(dif_gpio_write(&gpio_, 0, true), kDifOk); EXPECT_WRITE32(GPIO_MASKED_OUT_LOWER_REG_OFFSET, {{31, 1}, {15, 0}}); - EXPECT_EQ(dif_gpio_write(&gpio_, 15, false), kDifGpioOk); + EXPECT_EQ(dif_gpio_write(&gpio_, 15, false), kDifOk); EXPECT_WRITE32(GPIO_MASKED_OUT_UPPER_REG_OFFSET, {{16, 1}, {0, 1}}); - EXPECT_EQ(dif_gpio_write(&gpio_, 16, true), kDifGpioOk); + EXPECT_EQ(dif_gpio_write(&gpio_, 16, true), kDifOk); EXPECT_WRITE32(GPIO_MASKED_OUT_UPPER_REG_OFFSET, {{31, 1}, {15, 0}}); - EXPECT_EQ(dif_gpio_write(&gpio_, 31, false), kDifGpioOk); + EXPECT_EQ(dif_gpio_write(&gpio_, 31, false), kDifOk); } TEST_F(WriteTest, Masked) { EXPECT_WRITE32(GPIO_MASKED_OUT_LOWER_REG_OFFSET, 0xCDCD3322); EXPECT_WRITE32(GPIO_MASKED_OUT_UPPER_REG_OFFSET, 0xABAB5544); - EXPECT_EQ(dif_gpio_write_masked(&gpio_, 0xABABCDCD, 0x55443322), kDifGpioOk); + EXPECT_EQ(dif_gpio_write_masked(&gpio_, 0xABABCDCD, 0x55443322), kDifOk); EXPECT_WRITE32(GPIO_MASKED_OUT_UPPER_REG_OFFSET, 0xABAB5544); - EXPECT_EQ(dif_gpio_write_masked(&gpio_, 0xABAB0000, 0x55443322), kDifGpioOk); + EXPECT_EQ(dif_gpio_write_masked(&gpio_, 0xABAB0000, 0x55443322), kDifOk); EXPECT_WRITE32(GPIO_MASKED_OUT_LOWER_REG_OFFSET, 0xCDCD3322); - EXPECT_EQ(dif_gpio_write_masked(&gpio_, 0x0000CDCD, 0x55443322), kDifGpioOk); + EXPECT_EQ(dif_gpio_write_masked(&gpio_, 0x0000CDCD, 0x55443322), kDifOk); } // Output mode tests -class OutputModeTest : public DifGpioTestInitialized {}; +class OutputModeTest : public GpioTestInitialized {}; TEST_F(OutputModeTest, NullArgs) { - EXPECT_EQ(dif_gpio_output_set_enabled_all(nullptr, kAllOnes), kDifGpioBadArg); - EXPECT_EQ(dif_gpio_output_set_enabled(nullptr, 0, kDifGpioToggleEnabled), - kDifGpioBadArg); + EXPECT_EQ(dif_gpio_output_set_enabled_all(nullptr, kAllOnes), kDifBadArg); + EXPECT_EQ(dif_gpio_output_set_enabled(nullptr, 0, kDifToggleEnabled), + kDifBadArg); EXPECT_EQ(dif_gpio_output_set_enabled_masked(nullptr, kAllOnes, kAllOnes), - kDifGpioBadArg); + kDifBadArg); } TEST_F(OutputModeTest, AllPins) { constexpr uint32_t kVal = 0xA5A5A5A5; EXPECT_WRITE32(GPIO_DIRECT_OE_REG_OFFSET, kVal); - EXPECT_EQ(dif_gpio_output_set_enabled_all(&gpio_, kVal), kDifGpioOk); + EXPECT_EQ(dif_gpio_output_set_enabled_all(&gpio_, kVal), kDifOk); } TEST_F(OutputModeTest, SinglePin) { EXPECT_WRITE32(GPIO_MASKED_OE_LOWER_REG_OFFSET, {{16, 1}, {0, 1}}); - EXPECT_EQ(dif_gpio_output_set_enabled(&gpio_, 0, kDifGpioToggleEnabled), - kDifGpioOk); + EXPECT_EQ(dif_gpio_output_set_enabled(&gpio_, 0, kDifToggleEnabled), kDifOk); EXPECT_WRITE32(GPIO_MASKED_OE_LOWER_REG_OFFSET, {{31, 1}, {15, 0}}); - EXPECT_EQ(dif_gpio_output_set_enabled(&gpio_, 15, kDifGpioToggleDisabled), - kDifGpioOk); + EXPECT_EQ(dif_gpio_output_set_enabled(&gpio_, 15, kDifToggleDisabled), + kDifOk); EXPECT_WRITE32(GPIO_MASKED_OE_UPPER_REG_OFFSET, {{16, 1}, {0, 1}}); - EXPECT_EQ(dif_gpio_output_set_enabled(&gpio_, 16, kDifGpioToggleEnabled), - kDifGpioOk); + EXPECT_EQ(dif_gpio_output_set_enabled(&gpio_, 16, kDifToggleEnabled), kDifOk); EXPECT_WRITE32(GPIO_MASKED_OE_UPPER_REG_OFFSET, {{31, 1}, {15, 0}}); - EXPECT_EQ(dif_gpio_output_set_enabled(&gpio_, 31, kDifGpioToggleDisabled), - kDifGpioOk); + EXPECT_EQ(dif_gpio_output_set_enabled(&gpio_, 31, kDifToggleDisabled), + kDifOk); } TEST_F(OutputModeTest, Masked) { EXPECT_WRITE32(GPIO_MASKED_OE_LOWER_REG_OFFSET, 0xCDCD3322); EXPECT_WRITE32(GPIO_MASKED_OE_UPPER_REG_OFFSET, 0xABAB5544); EXPECT_EQ(dif_gpio_output_set_enabled_masked(&gpio_, 0xABABCDCD, 0x55443322), - kDifGpioOk); + kDifOk); EXPECT_WRITE32(GPIO_MASKED_OE_LOWER_REG_OFFSET, 0xCDCD3322); EXPECT_EQ(dif_gpio_output_set_enabled_masked(&gpio_, 0x0000CDCD, 0x55443322), - kDifGpioOk); + kDifOk); EXPECT_WRITE32(GPIO_MASKED_OE_UPPER_REG_OFFSET, 0xABAB5544); EXPECT_EQ(dif_gpio_output_set_enabled_masked(&gpio_, 0xABAB0000, 0x55443322), - kDifGpioOk); + kDifOk); } // Input noise filter tests -class InputFilterTest : public DifGpioTestInitialized {}; +class InputFilterTest : public GpioTestInitialized {}; TEST_F(InputFilterTest, NullArgs) { EXPECT_EQ(dif_gpio_input_noise_filter_set_enabled(nullptr, kAllOnes, - kDifGpioToggleEnabled), - kDifGpioBadArg); + kDifToggleEnabled), + kDifBadArg); EXPECT_EQ(dif_gpio_input_noise_filter_set_enabled(nullptr, kAllOnes, - kDifGpioToggleDisabled), - kDifGpioBadArg); + kDifToggleDisabled), + kDifBadArg); } TEST_F(InputFilterTest, MaskedEnable) { @@ -237,9 +230,9 @@ TEST_F(InputFilterTest, MaskedEnable) { EXPECT_READ32(GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, 0x0); EXPECT_WRITE32(GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, kVal); - EXPECT_EQ(dif_gpio_input_noise_filter_set_enabled(&gpio_, kVal, - kDifGpioToggleEnabled), - kDifGpioOk); + EXPECT_EQ( + dif_gpio_input_noise_filter_set_enabled(&gpio_, kVal, kDifToggleEnabled), + kDifOk); } TEST_F(InputFilterTest, MaskedDisable) { @@ -247,12 +240,12 @@ TEST_F(InputFilterTest, MaskedDisable) { EXPECT_READ32(GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, kAllOnes); EXPECT_WRITE32(GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, ~kVal); - EXPECT_EQ(dif_gpio_input_noise_filter_set_enabled(&gpio_, kVal, - kDifGpioToggleDisabled), - kDifGpioOk); + EXPECT_EQ( + dif_gpio_input_noise_filter_set_enabled(&gpio_, kVal, kDifToggleDisabled), + kDifOk); } -class IrqTest : public DifGpioTestInitialized { +class IrqTest : public GpioTestInitialized { protected: // Expectations for disabling the interrupt triggers of the pins given by // `pins`. @@ -268,86 +261,6 @@ class IrqTest : public DifGpioTestInitialized { } }; -TEST_F(IrqTest, NullArgs) { - EXPECT_EQ(dif_gpio_irq_force(nullptr, 0), kDifGpioBadArg); - - dif_gpio_state_t out_arg_uint32_t; - EXPECT_EQ(dif_gpio_irq_is_pending_all(nullptr, &out_arg_uint32_t), - kDifGpioBadArg); - EXPECT_EQ(dif_gpio_irq_is_pending_all(&gpio_, nullptr), kDifGpioBadArg); - EXPECT_EQ(dif_gpio_irq_is_pending_all(nullptr, nullptr), kDifGpioBadArg); - - bool out_arg_bool; - EXPECT_EQ(dif_gpio_irq_is_pending(nullptr, 0, &out_arg_bool), kDifGpioBadArg); - EXPECT_EQ(dif_gpio_irq_is_pending(&gpio_, 0, nullptr), kDifGpioBadArg); - EXPECT_EQ(dif_gpio_irq_is_pending(nullptr, 0, nullptr), kDifGpioBadArg); - - EXPECT_EQ(dif_gpio_irq_acknowledge(nullptr, 0), kDifGpioBadArg); - - EXPECT_EQ( - dif_gpio_irq_set_enabled_masked(nullptr, kAllOnes, kDifGpioToggleEnabled), - kDifGpioBadArg); - - EXPECT_EQ( - dif_gpio_irq_set_trigger(nullptr, kAllOnes, kDifGpioIrqTriggerEdgeRising), - kDifGpioBadArg); -} - -TEST_F(IrqTest, ForceSinglePin) { - for (uint32_t pin = 0; pin < 32; ++pin) { - EXPECT_WRITE32(GPIO_INTR_TEST_REG_OFFSET, {{pin, 1}}); - EXPECT_EQ(dif_gpio_irq_force(&gpio_, pin), kDifGpioOk); - } -} - -TEST_F(IrqTest, ReadAllPins) { - constexpr uint32_t kVal = 0xABABABAB; - EXPECT_READ32(GPIO_INTR_STATE_REG_OFFSET, kVal); - dif_gpio_state_t irq_state = 0; - EXPECT_EQ(dif_gpio_irq_is_pending_all(&gpio_, &irq_state), kDifGpioOk); - EXPECT_EQ(irq_state, kVal); -} - -TEST_F(IrqTest, ReadSinglePin) { - for (uint32_t pin = 0; pin < 32; ++pin) { - for (const bool exp_irq_state : {true, false}) { - const uint32_t reg_val = - exp_irq_state ? AllZerosExcept(pin) : AllOnesExcept(pin); - EXPECT_READ32(GPIO_INTR_STATE_REG_OFFSET, reg_val); - bool irq_state = !exp_irq_state; - EXPECT_EQ(dif_gpio_irq_is_pending(&gpio_, pin, &irq_state), kDifGpioOk); - EXPECT_EQ(irq_state, exp_irq_state); - } - } -} - -TEST_F(IrqTest, ClearSinglePin) { - for (uint32_t pin = 0; pin < 32; ++pin) { - EXPECT_WRITE32(GPIO_INTR_STATE_REG_OFFSET, {{pin, 1}}); - EXPECT_EQ(dif_gpio_irq_acknowledge(&gpio_, pin), kDifGpioOk); - } -} - -TEST_F(IrqTest, MaskedEnable) { - constexpr uint32_t kVal = 0xABABABAB; - EXPECT_READ32(GPIO_INTR_ENABLE_REG_OFFSET, 0x0); - EXPECT_WRITE32(GPIO_INTR_ENABLE_REG_OFFSET, kVal); - - EXPECT_EQ( - dif_gpio_irq_set_enabled_masked(&gpio_, kVal, kDifGpioToggleEnabled), - kDifGpioOk); -} - -TEST_F(IrqTest, MaskedDisable) { - constexpr uint32_t kVal = 0xABABABAB; - EXPECT_READ32(GPIO_INTR_ENABLE_REG_OFFSET, kAllOnes); - EXPECT_WRITE32(GPIO_INTR_ENABLE_REG_OFFSET, ~kVal); - - EXPECT_EQ( - dif_gpio_irq_set_enabled_masked(&gpio_, kVal, kDifGpioToggleDisabled), - kDifGpioOk); -} - TEST_F(IrqTest, MaskedConfigTriggerEdgeRising) { SCOPED_TRACE("IrqTest.MaskedConfigTriggerEdgeRising"); constexpr uint32_t kVal = 0xABABABAB; @@ -357,7 +270,7 @@ TEST_F(IrqTest, MaskedConfigTriggerEdgeRising) { EXPECT_EQ( dif_gpio_irq_set_trigger(&gpio_, kVal, kDifGpioIrqTriggerEdgeRising), - kDifGpioOk); + kDifOk); } TEST_F(IrqTest, MaskedConfigTriggerEdgeFalling) { @@ -369,7 +282,7 @@ TEST_F(IrqTest, MaskedConfigTriggerEdgeFalling) { EXPECT_EQ( dif_gpio_irq_set_trigger(&gpio_, kVal, kDifGpioIrqTriggerEdgeFalling), - kDifGpioOk); + kDifOk); } TEST_F(IrqTest, MaskedConfigTriggerLevelLow) { @@ -380,7 +293,7 @@ TEST_F(IrqTest, MaskedConfigTriggerLevelLow) { EXPECT_WRITE32(GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, kVal); EXPECT_EQ(dif_gpio_irq_set_trigger(&gpio_, kVal, kDifGpioIrqTriggerLevelLow), - kDifGpioOk); + kDifOk); } TEST_F(IrqTest, MaskedConfigTriggerLevelHigh) { @@ -391,7 +304,7 @@ TEST_F(IrqTest, MaskedConfigTriggerLevelHigh) { EXPECT_WRITE32(GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, kVal); EXPECT_EQ(dif_gpio_irq_set_trigger(&gpio_, kVal, kDifGpioIrqTriggerLevelHigh), - kDifGpioOk); + kDifOk); } TEST_F(IrqTest, MaskedConfigTriggerEdgeRisingFalling) { @@ -405,7 +318,7 @@ TEST_F(IrqTest, MaskedConfigTriggerEdgeRisingFalling) { EXPECT_EQ(dif_gpio_irq_set_trigger(&gpio_, kVal, kDifGpioIrqTriggerEdgeRisingFalling), - kDifGpioOk); + kDifOk); } TEST_F(IrqTest, MaskedConfigTriggerEdgeRisingLevelLow) { @@ -419,7 +332,7 @@ TEST_F(IrqTest, MaskedConfigTriggerEdgeRisingLevelLow) { EXPECT_EQ(dif_gpio_irq_set_trigger(&gpio_, kVal, kDifGpioIrqTriggerEdgeRisingLevelLow), - kDifGpioOk); + kDifOk); } TEST_F(IrqTest, MaskedConfigTriggerEdgeFallingLevelHigh) { @@ -433,7 +346,7 @@ TEST_F(IrqTest, MaskedConfigTriggerEdgeFallingLevelHigh) { EXPECT_EQ(dif_gpio_irq_set_trigger(&gpio_, kVal, kDifGpioIrqTriggerEdgeFallingLevelHigh), - kDifGpioOk); + kDifOk); } TEST_F(IrqTest, MaskedConfigTriggerGeneralError) { @@ -443,7 +356,7 @@ TEST_F(IrqTest, MaskedConfigTriggerGeneralError) { EXPECT_EQ(dif_gpio_irq_set_trigger( &gpio_, kVal, static_cast(kAllOnes)), - kDifGpioError); + kDifError); } } // namespace diff --git a/sw/device/lib/dif/meson.build b/sw/device/lib/dif/meson.build index e9b7e9329dae1..476b04830fa61 100644 --- a/sw/device/lib/dif/meson.build +++ b/sw/device/lib/dif/meson.build @@ -161,6 +161,7 @@ sw_lib_dif_gpio = declare_dependency( ], dependencies: [ sw_lib_mmio, + sw_lib_dif_autogen_gpio, ], ) ) @@ -168,9 +169,11 @@ sw_lib_dif_gpio = declare_dependency( test('dif_gpio_unittest', executable( 'dif_gpio_unittest', sources: [ - hw_ip_gpio_reg_h, - meson.source_root() / 'sw/device/lib/dif/dif_gpio.c', 'dif_gpio_unittest.cc', + 'autogen/dif_gpio_autogen_unittest.cc', + meson.source_root() / 'sw/device/lib/dif/dif_gpio.c', + meson.source_root() / 'sw/device/lib/dif/autogen/dif_gpio_autogen.c', + hw_ip_gpio_reg_h, ], dependencies: [ sw_vendor_gtest, diff --git a/sw/device/sca/lib/sca.c b/sw/device/sca/lib/sca.c index 093d215b180a9..ef44435333755 100644 --- a/sw/device/sca/lib/sca.c +++ b/sw/device/sca/lib/sca.c @@ -90,9 +90,8 @@ static void sca_init_uart(void) { * @param trigger Trigger source. */ static void sca_init_gpio(sca_trigger_source_t trigger) { - dif_gpio_params_t gpio_params = { - .base_addr = mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR)}; - IGNORE_RESULT(dif_gpio_init(gpio_params, &gpio)); + IGNORE_RESULT( + dif_gpio_init(mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR), &gpio)); uint32_t select_mask = bitfield_field32_write(0, kTriggerSourceBitfield, UINT32_MAX); diff --git a/sw/device/tests/gpio_smoketest.c b/sw/device/tests/gpio_smoketest.c index 7c9e259f6e7b2..e5202500e0870 100644 --- a/sw/device/tests/gpio_smoketest.c +++ b/sw/device/tests/gpio_smoketest.c @@ -46,10 +46,10 @@ static const uint32_t kGpioMask = 0x0000FFFF; * @param write_val Value to write. */ static void test_gpio_write(uint32_t write_val) { - CHECK(dif_gpio_write_all(&gpio, write_val) == kDifGpioOk); + CHECK(dif_gpio_write_all(&gpio, write_val) == kDifOk); uint32_t read_val = 0; - CHECK(dif_gpio_read_all(&gpio, &read_val) == kDifGpioOk); + CHECK(dif_gpio_read_all(&gpio, &read_val) == kDifOk); uint32_t expected = write_val & kGpioMask; uint32_t actual = read_val & kGpioMask; @@ -63,12 +63,9 @@ static void test_gpio_write(uint32_t write_val) { * NOTE: This test can currently run only on FPGA and DV. */ bool test_main(void) { - CHECK(dif_gpio_init( - (dif_gpio_params_t){ - .base_addr = mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR), - }, - &gpio) == kDifGpioOk); - CHECK(dif_gpio_output_set_enabled_all(&gpio, kGpioMask) == kDifGpioOk); + CHECK(dif_gpio_init(mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR), + &gpio) == kDifOk); + CHECK(dif_gpio_output_set_enabled_all(&gpio, kGpioMask) == kDifOk); for (uint8_t i = 0; i < ARRAYSIZE(kGpioVals); ++i) { test_gpio_write(kGpioVals[i]); diff --git a/sw/device/tests/sim_dv/gpio_test.c b/sw/device/tests/sim_dv/gpio_test.c index 89c13b1771841..0ee3687252417 100644 --- a/sw/device/tests/sim_dv/gpio_test.c +++ b/sw/device/tests/sim_dv/gpio_test.c @@ -102,18 +102,18 @@ static void gpio_output_test(const dif_gpio_t *gpio) { LOG_INFO("Starting GPIO output test"); // Set the GPIOs to be in output mode. - CHECK(dif_gpio_output_set_enabled_all(gpio, kGpiosAllowedMask) == kDifGpioOk, + CHECK(dif_gpio_output_set_enabled_all(gpio, kGpiosAllowedMask) == kDifOk, "dif_gpio_output_set_enabled_all failed"); // Walk 1s - 0001, 0010, 0100, 1000, etc. for (uint32_t i = 0; i < kNumGpios; ++i) { uint32_t gpio_val = 1 << i; - CHECK(dif_gpio_write_all(gpio, gpio_val) == kDifGpioOk, + CHECK(dif_gpio_write_all(gpio, gpio_val) == kDifOk, "dif_gpio_write_all failed"); // Read GPIO_IN to confirm what we wrote. uint32_t read_val; - CHECK(dif_gpio_read_all(gpio, &read_val) == kDifGpioOk, + CHECK(dif_gpio_read_all(gpio, &read_val) == kDifOk, "dif_gpio_read_all failed"); // Check written and read val for correctness. @@ -127,22 +127,22 @@ static void gpio_output_test(const dif_gpio_t *gpio) { } // Write all 0s to the GPIOs. - CHECK(dif_gpio_write_all(gpio, ~kGpiosMask) == kDifGpioOk, + CHECK(dif_gpio_write_all(gpio, ~kGpiosMask) == kDifOk, "dif_gpio_write_all failed"); // Write all 1s to the GPIOs. - CHECK(dif_gpio_write_all(gpio, kGpiosMask) == kDifGpioOk, + CHECK(dif_gpio_write_all(gpio, kGpiosMask) == kDifOk, "dif_gpio_write_all failed"); // Now walk 0s - 1110, 1101, 1011, 0111, etc. for (uint32_t i = 0; i < kNumGpios; ++i) { uint32_t gpio_val = ~(1 << i); - CHECK(dif_gpio_write_all(gpio, gpio_val) == kDifGpioOk, + CHECK(dif_gpio_write_all(gpio, gpio_val) == kDifOk, "dif_gpio_write_all failed"); // Read GPIO_IN to confirm what we wrote. uint32_t read_val; - CHECK(dif_gpio_read_all(gpio, &read_val) == kDifGpioOk, + CHECK(dif_gpio_read_all(gpio, &read_val) == kDifOk, "dif_gpio_read_all failed"); // Check written and read val for correctness. @@ -156,11 +156,11 @@ static void gpio_output_test(const dif_gpio_t *gpio) { } // Write all 1s to the GPIOs. - CHECK(dif_gpio_write_all(gpio, kGpiosMask) == kDifGpioOk, + CHECK(dif_gpio_write_all(gpio, kGpiosMask) == kDifOk, "dif_gpio_write_all failed"); // Write all 0s to the GPIOs. - CHECK(dif_gpio_write_all(gpio, ~kGpiosMask) == kDifGpioOk, + CHECK(dif_gpio_write_all(gpio, ~kGpiosMask) == kDifOk, "dif_gpio_write_all failed"); } @@ -178,23 +178,21 @@ static void gpio_input_test(const dif_gpio_t *gpio) { LOG_INFO("Starting GPIO input test"); // Enable the noise filter on all GPIOs. - CHECK(dif_gpio_input_noise_filter_set_enabled( - gpio, kGpiosAllowedMask, kDifGpioToggleEnabled) == kDifGpioOk, + CHECK(dif_gpio_input_noise_filter_set_enabled(gpio, kGpiosAllowedMask, + kDifToggleEnabled) == kDifOk, "dif_gpio_input_noise_filter_set_enabled failed"); // Configure all GPIOs to be rising and falling edge interrupts. CHECK(dif_gpio_irq_set_trigger(gpio, kGpiosAllowedMask, - kDifGpioIrqTriggerEdgeRisingFalling) == - kDifGpioOk, + kDifGpioIrqTriggerEdgeRisingFalling) == kDifOk, "dif_gpio_irq_set_trigger failed"); // Enable interrupts on all GPIOs. - CHECK(dif_gpio_irq_set_enabled_masked(gpio, kGpiosAllowedMask, - kDifGpioToggleEnabled) == kDifGpioOk, - "dif_gpio_irq_set_enabled_masked failed"); + CHECK(dif_gpio_irq_restore_all(gpio, &kGpiosAllowedMask) == kDifOk, + "dif_gpio_irq_restore_all failed"); // Set the GPIOs to be in input mode. - CHECK(dif_gpio_output_set_enabled_all(gpio, 0u) == kDifGpioOk, + CHECK(dif_gpio_output_set_enabled_all(gpio, 0u) == kDifOk, "dif_gpio_output_set_enabled_all failed"); // Wait for rising edge interrupt on each pin. @@ -242,15 +240,15 @@ void handler_irq_external(void) { // Check if the same interrupt fired at GPIO as well. uint32_t gpio_irqs_status; - CHECK(dif_gpio_irq_is_pending_all(&gpio, &gpio_irqs_status) == kDifGpioOk, - "dif_gpio_irq_is_pending_all failed"); + CHECK(dif_gpio_irq_get_state(&gpio, &gpio_irqs_status) == kDifOk, + "dif_gpio_irq_get_state failed"); CHECK(gpio_irqs_status == (1 << expected_gpio_pin_irq), "Incorrect GPIO irqs status {exp: %x, obs: %x}", (1 << expected_gpio_pin_irq), gpio_irqs_status); // Read the gpio pin value to ensure the right value is being reflected. bool pin_val; - CHECK(dif_gpio_read(&gpio, expected_gpio_pin_irq, &pin_val) == kDifGpioOk, + CHECK(dif_gpio_read(&gpio, expected_gpio_pin_irq, &pin_val) == kDifOk, "dif_gpio_read failed"); // Check if the pin value is set correctly. @@ -258,7 +256,7 @@ void handler_irq_external(void) { expected_gpio_pin_irq, expected_irq_edge); // Clear the interrupt at GPIO. - CHECK(dif_gpio_irq_acknowledge(&gpio, gpio_pin_irq_fired) == kDifGpioOk, + CHECK(dif_gpio_irq_acknowledge(&gpio, gpio_pin_irq_fired) == kDifOk, "dif_gpio_irq_acknowledge failed"); // Complete the IRQ at PLIC. @@ -274,9 +272,8 @@ bool test_main(void) { pinmux_init(); // Initialize the GPIO. - dif_gpio_params_t gpio_params = { - .base_addr = mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR)}; - CHECK(dif_gpio_init(gpio_params, &gpio) == kDifGpioOk, + CHECK(dif_gpio_init(mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR), + &gpio) == kDifOk, "dif_gpio_init failed"); // Initialize the PLIC.