From 664c2aa90a16f550640ff8e970cca7b314098657 Mon Sep 17 00:00:00 2001 From: Greg Chadwick Date: Mon, 28 Oct 2024 15:55:08 +0000 Subject: [PATCH] [rtl] Explicitly set RV32B/RV32M for Ibex This is effectively a no-op change. Before the latest Ibex was vendored we had no bitmanip (the RV32BFull parameter was not fully passed through) and RV32M was the fast multiplier. Sadly the single cycle multiplier seems to be increasing timing pressure. It does just meet timing but greatly increases synthesis times. As it's implemented with in-built FPGA DSP blocks it shouldn't be a big issue to use it so something to examine here but for now leave things as they are. --- rtl/system/sonata_system.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/rtl/system/sonata_system.sv b/rtl/system/sonata_system.sv index 69ef0e704..8846739cd 100644 --- a/rtl/system/sonata_system.sv +++ b/rtl/system/sonata_system.sv @@ -770,7 +770,8 @@ module sonata_system .HeapBase ( tl_main_pkg::ADDR_SPACE_SRAM ), .TSMapBase ( tl_main_pkg::ADDR_SPACE_REV_TAG ), .TSMapSize ( RevTagDepth ), - .RV32B ( ibex_pkg::RV32BFull ), + .RV32M ( ibex_pkg::RV32MFast ), + .RV32B ( ibex_pkg::RV32BNone ), .ICache ( 1'b1 ) ) u_top_tracing ( .clk_i (clk_sys_i),