From aa7d0518ddd55a014d93785c46d031f142f5cb42 Mon Sep 17 00:00:00 2001 From: Elliot Baptist Date: Tue, 29 Oct 2024 17:33:39 +0000 Subject: [PATCH] Spit xbar into two levels Attempt to reduce the depth of xbar logic on critical timing paths to/from the HyperRAM/SRAM by moving most peripherals from the main cross-bar to a new "peri" (peripheral) sub-crossbar. Keeps addresses the same, but some few devices have increased access latency due to being moved to xbar_peri or to improve QoR. Blocks with increased access latency: timer, system_info, & hw_rev. --- .gitattributes | 3 + data/top_config.toml | 2 - data/xbar_main.hjson | 92 +------- data/xbar_main_generated.hjson | 172 +------------- data/xbar_peri.hjson | 132 +++++++++++ data/xbar_peri_generated.hjson | 172 ++++++++++++++ rtl/bus/sonata_xbar_main.sv | 58 +++-- rtl/bus/tl_main_pkg.sv | 110 +++------ rtl/bus/tl_peri_pkg.sv | 60 +++++ rtl/bus/xbar_main.sv | 326 ++++++++------------------ rtl/bus/xbar_peri.core | 24 ++ rtl/bus/xbar_peri.sv | 201 ++++++++++++++++ rtl/templates/sonata_xbar_main.sv.tpl | 40 +++- sonata_system.core | 1 + util/generate_xbar.sh | 1 + util/top_gen/generator.py | 1 + 16 files changed, 824 insertions(+), 571 deletions(-) create mode 100644 data/xbar_peri.hjson create mode 100644 data/xbar_peri_generated.hjson create mode 100644 rtl/bus/tl_peri_pkg.sv create mode 100644 rtl/bus/xbar_peri.core create mode 100644 rtl/bus/xbar_peri.sv diff --git a/.gitattributes b/.gitattributes index e24ca6363..cd18b3709 100644 --- a/.gitattributes +++ b/.gitattributes @@ -2,11 +2,14 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 data/xbar_main_generated.hjson linguist-generated=true +data/xbar_peri_generated.hjson linguist-generated=true doc/ip/pinmux.md linguist-generated=true rtl/bus/sonata_xbar_main.sv linguist-generated=true rtl/bus/tl_main_pkg.sv linguist-generated=true +rtl/bus/tl_peri_pkg.sv linguist-generated=true rtl/bus/tl_ifetch_pkg.sv linguist-generated=true rtl/bus/xbar_main.sv linguist-generated=true +rtl/bus/xbar_peri.sv linguist-generated=true rtl/bus/xbar_ifetch.sv linguist-generated=true rtl/system/pinmux.sv linguist-generated=true rtl/system/sonata_pkg.sv linguist-generated=true diff --git a/data/top_config.toml b/data/top_config.toml index b763c8ad1..3904be695 100644 --- a/data/top_config.toml +++ b/data/top_config.toml @@ -18,7 +18,6 @@ instances = 1 ios = [{ name = "ios", type = "output", length = 6 }] memory_start = 0x80001000 memory_size = 0x00001000 -xbar = { pipeline = "true", req_fifo_pass = "false", rsp_fifo_pass = "false" } [[blocks]] name = "uart" @@ -29,7 +28,6 @@ ios = [ ] memory_start = 0x80100000 memory_size = 0x00001000 -xbar = { pipeline = "true", req_fifo_pass = "false", rsp_fifo_pass = "false" } [[blocks]] name = "i2c" diff --git a/data/xbar_main.hjson b/data/xbar_main.hjson index e7088a61e..e75161203 100644 --- a/data/xbar_main.hjson +++ b/data/xbar_main.hjson @@ -61,90 +61,25 @@ size_byte: "0x00004000", }], }, - { name: "gpio", // General purpose input and output + { name: "peri", type: "device", clock: "clk_sys_i", reset: "rst_sys_ni", - req_fifo_pass: false, - rsp_fifo_pass: false, xbar: false, addr_range: [{ base_addr: "0x80000000", - size_byte: "0x00001000", - }], - pipeline: true, - }, - { name: "pinmux", // Pin multiplexer - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - req_fifo_pass: false, - rsp_fifo_pass: false, - xbar: false, - addr_range: [{ - base_addr: "0x80005000", - size_byte: "0x00001000", - }], - pipeline: true, - }, - { name: "rgbled_ctrl", // RGB LED Controller - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - req_fifo_pass: false, - rsp_fifo_pass: false, - xbar: false, - addr_range: [{ - base_addr: "0x80009000", - size_byte: "0x00001000", + size_byte: "0x00200000", }], pipeline: true, - }, - { name: "hw_rev", // Hardware revoker control register - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - xbar: false, - addr_range: [{ - base_addr: "0x8000A000", - size_byte: "0x00001000", - }], - }, - { name: "xadc", // XADC - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", req_fifo_pass: false, rsp_fifo_pass: false, - xbar: false, - addr_range: [{ - base_addr: "0x8000B000", - size_byte: "0x00001000", - }], - pipeline: true, - }, - { name: "system_info", // System information - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - xbar: false, - addr_range: [{ - base_addr: "0x8000C000", - size_byte: "0x00001000", - }], - }, - { name: "timer", // Interrupt timer - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - xbar: false, - addr_range: [{ - base_addr: "0x80040000", - size_byte: "0x00010000", - }], }, + // I^2C devices included here instead of in peri only because + // address range sizes must be a power of two. + // We can easily tolerate an extra cycle of access latency to them, + // so add pipelining to allow them to be placed further away physically. % for block in config.blocks: - % if not block.name == "gpio": + % if block.name in ["i2c", "spi"]: % for i in range(block.instances): { name: "${f"{block.name}{i}"}", type: "device", @@ -176,15 +111,12 @@ type: "device", clock: "clk_sys_i", reset: "rst_sys_ni", - req_fifo_pass: false, - rsp_fifo_pass: false, xbar: false, addr_range: [{ // This block is overaligned to 0x0800_0000 bytes since OpenTitan RV_PLIC block expects it. base_addr: "0x88000000", size_byte: "0x04000000", }], - pipeline: true, }, ], connections: { @@ -192,15 +124,9 @@ "sram", "hyperram", "rev_tag", - "gpio", - "pinmux", - "system_info", - "rgbled_ctrl", - "hw_rev", - "xadc", - "timer", + "peri", % for block in config.blocks: - % if not block.name == "gpio": + % if block.name in ["i2c", "spi"]: % for i in range(block.instances): "${f"{block.name}{i}"}", % endfor diff --git a/data/xbar_main_generated.hjson b/data/xbar_main_generated.hjson index 120bbaba7..533c964b8 100644 --- a/data/xbar_main_generated.hjson +++ b/data/xbar_main_generated.hjson @@ -61,166 +61,23 @@ size_byte: "0x00004000", }], }, - { name: "gpio", // General purpose input and output + { name: "peri", type: "device", clock: "clk_sys_i", reset: "rst_sys_ni", - req_fifo_pass: false, - rsp_fifo_pass: false, xbar: false, addr_range: [{ base_addr: "0x80000000", - size_byte: "0x00001000", - }], - pipeline: true, - }, - { name: "pinmux", // Pin multiplexer - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - req_fifo_pass: false, - rsp_fifo_pass: false, - xbar: false, - addr_range: [{ - base_addr: "0x80005000", - size_byte: "0x00001000", - }], - pipeline: true, - }, - { name: "rgbled_ctrl", // RGB LED Controller - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - req_fifo_pass: false, - rsp_fifo_pass: false, - xbar: false, - addr_range: [{ - base_addr: "0x80009000", - size_byte: "0x00001000", - }], - pipeline: true, - }, - { name: "hw_rev", // Hardware revoker control register - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - xbar: false, - addr_range: [{ - base_addr: "0x8000A000", - size_byte: "0x00001000", - }], - }, - { name: "xadc", // XADC - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - req_fifo_pass: false, - rsp_fifo_pass: false, - xbar: false, - addr_range: [{ - base_addr: "0x8000B000", - size_byte: "0x00001000", - }], - pipeline: true, - }, - { name: "system_info", // System information - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - xbar: false, - addr_range: [{ - base_addr: "0x8000C000", - size_byte: "0x00001000", - }], - }, - { name: "timer", // Interrupt timer - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - xbar: false, - addr_range: [{ - base_addr: "0x80040000", - size_byte: "0x00010000", - }], - }, - { name: "pwm0", - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - xbar: false, - addr_range: [{ - base_addr: "0x80001000", - size_byte: "0x1000", - }], - pipeline: true, - req_fifo_pass: false, - rsp_fifo_pass: false, - }, - { name: "uart0", - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - xbar: false, - addr_range: [{ - base_addr: "0x80100000", - size_byte: "0x1000", - }], - pipeline: true, - req_fifo_pass: false, - rsp_fifo_pass: false, - }, - { name: "uart1", - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - xbar: false, - addr_range: [{ - base_addr: "0x80101000", - size_byte: "0x1000", - }], - pipeline: true, - req_fifo_pass: false, - rsp_fifo_pass: false, - }, - { name: "uart2", - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - xbar: false, - addr_range: [{ - base_addr: "0x80102000", - size_byte: "0x1000", - }], - pipeline: true, - req_fifo_pass: false, - rsp_fifo_pass: false, - }, - { name: "uart3", - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - xbar: false, - addr_range: [{ - base_addr: "0x80103000", - size_byte: "0x1000", - }], - pipeline: true, - req_fifo_pass: false, - rsp_fifo_pass: false, - }, - { name: "uart4", - type: "device", - clock: "clk_sys_i", - reset: "rst_sys_ni", - xbar: false, - addr_range: [{ - base_addr: "0x80104000", - size_byte: "0x1000", + size_byte: "0x00200000", }], pipeline: true, req_fifo_pass: false, rsp_fifo_pass: false, }, + // I^2C devices included here instead of in peri only because + // address range sizes must be a power of two. + // We can easily tolerate an extra cycle of access latency to them, + // so add pipelining to allow them to be placed further away physically. { name: "i2c0", type: "device", clock: "clk_sys_i", @@ -311,15 +168,12 @@ type: "device", clock: "clk_sys_i", reset: "rst_sys_ni", - req_fifo_pass: false, - rsp_fifo_pass: false, xbar: false, addr_range: [{ // This block is overaligned to 0x0800_0000 bytes since OpenTitan RV_PLIC block expects it. base_addr: "0x88000000", size_byte: "0x04000000", }], - pipeline: true, }, ], connections: { @@ -327,19 +181,7 @@ "sram", "hyperram", "rev_tag", - "gpio", - "pinmux", - "system_info", - "rgbled_ctrl", - "hw_rev", - "xadc", - "timer", - "pwm0", - "uart0", - "uart1", - "uart2", - "uart3", - "uart4", + "peri", "i2c0", "i2c1", "spi0", diff --git a/data/xbar_peri.hjson b/data/xbar_peri.hjson new file mode 100644 index 000000000..c1c00fcbd --- /dev/null +++ b/data/xbar_peri.hjson @@ -0,0 +1,132 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +{ name: "peri", + type: "xbar", + clock: "clk_sys_i", // Main clock, used in sockets + clock_connections: { + clk_sys_i: "main", + }, + reset: "rst_sys_ni", + reset_connections: { + rst_sys_ni: "sys", + }, + nodes: [ + { name: "main", + type: "host", + // addr_space: "hart", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: true, + pipeline: false, + }, + { name: "gpio", // General purpose input and output + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x80000000", + size_byte: "0x00001000", + }], + }, + { name: "pinmux", // Pin multiplexer + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x80005000", + size_byte: "0x00001000", + }], + }, + { name: "rgbled_ctrl", // RGB LED Controller + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x80009000", + size_byte: "0x00001000", + }], + }, + { name: "hw_rev", // Hardware revoker control register + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x8000A000", + size_byte: "0x00001000", + }], + }, + { name: "xadc", // XADC + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x8000B000", + size_byte: "0x00001000", + }], + }, + { name: "system_info", // System information + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x8000C000", + size_byte: "0x00001000", + }], + }, + { name: "timer", // Interrupt timer + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x80040000", + size_byte: "0x00010000", + }], + }, + % for block in config.blocks: + % if block.name not in ["gpio", "i2c", "spi"]: + % for i in range(block.instances): + { name: "${f"{block.name}{i}"}", + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "${hex(block.memory_start + i * block.memory_size)}", + size_byte: "${hex(block.memory_size)}", + }], + % for (setting, value) in block.xbar.items(): + ${setting}: ${value}, + % endfor + }, + % endfor + % endif + % endfor + ], + connections: { + main: [ + "gpio", + "pinmux", + "system_info", + "rgbled_ctrl", + "hw_rev", + "xadc", + "timer", + % for block in config.blocks: + % if block.name not in ["gpio", "i2c", "spi"]: + % for i in range(block.instances): + "${f"{block.name}{i}"}", + % endfor + % endif + % endfor + ], + }, +} diff --git a/data/xbar_peri_generated.hjson b/data/xbar_peri_generated.hjson new file mode 100644 index 000000000..80cec54ae --- /dev/null +++ b/data/xbar_peri_generated.hjson @@ -0,0 +1,172 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +{ name: "peri", + type: "xbar", + clock: "clk_sys_i", // Main clock, used in sockets + clock_connections: { + clk_sys_i: "main", + }, + reset: "rst_sys_ni", + reset_connections: { + rst_sys_ni: "sys", + }, + nodes: [ + { name: "main", + type: "host", + // addr_space: "hart", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: true, + pipeline: false, + }, + { name: "gpio", // General purpose input and output + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x80000000", + size_byte: "0x00001000", + }], + }, + { name: "pinmux", // Pin multiplexer + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x80005000", + size_byte: "0x00001000", + }], + }, + { name: "rgbled_ctrl", // RGB LED Controller + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x80009000", + size_byte: "0x00001000", + }], + }, + { name: "hw_rev", // Hardware revoker control register + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x8000A000", + size_byte: "0x00001000", + }], + }, + { name: "xadc", // XADC + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x8000B000", + size_byte: "0x00001000", + }], + }, + { name: "system_info", // System information + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x8000C000", + size_byte: "0x00001000", + }], + }, + { name: "timer", // Interrupt timer + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x80040000", + size_byte: "0x00010000", + }], + }, + { name: "pwm0", + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x80001000", + size_byte: "0x1000", + }], + }, + { name: "uart0", + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x80100000", + size_byte: "0x1000", + }], + }, + { name: "uart1", + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x80101000", + size_byte: "0x1000", + }], + }, + { name: "uart2", + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x80102000", + size_byte: "0x1000", + }], + }, + { name: "uart3", + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x80103000", + size_byte: "0x1000", + }], + }, + { name: "uart4", + type: "device", + clock: "clk_sys_i", + reset: "rst_sys_ni", + xbar: false, + addr_range: [{ + base_addr: "0x80104000", + size_byte: "0x1000", + }], + }, + ], + connections: { + main: [ + "gpio", + "pinmux", + "system_info", + "rgbled_ctrl", + "hw_rev", + "xadc", + "timer", + "pwm0", + "uart0", + "uart1", + "uart2", + "uart3", + "uart4", + ], + }, +} diff --git a/rtl/bus/sonata_xbar_main.sv b/rtl/bus/sonata_xbar_main.sv index bdc964572..e34ed80b6 100644 --- a/rtl/bus/sonata_xbar_main.sv +++ b/rtl/bus/sonata_xbar_main.sv @@ -55,8 +55,12 @@ module sonata_xbar_main input tlul_pkg::tl_d2h_t tl_rv_plic_i ); + // Inter-xbar interfaces + tlul_pkg::tl_h2d_t tl_main_to_peri; + tlul_pkg::tl_d2h_t tl_peri_to_main; + xbar_main xbar ( - // Clock and reset. + // Clock and reset. .clk_sys_i (clk_sys_i), .rst_sys_ni (rst_sys_ni), .clk_usb_i (clk_usb_i), @@ -75,6 +79,40 @@ module sonata_xbar_main .tl_hyperram_i (tl_hyperram_i), .tl_rev_tag_o (tl_rev_tag_o), .tl_rev_tag_i (tl_rev_tag_i), + .tl_peri_o (tl_main_to_peri), + .tl_peri_i (tl_peri_to_main), + .tl_i2c0_o (tl_i2c_o[0]), + .tl_i2c0_i (tl_i2c_i[0]), + .tl_i2c1_o (tl_i2c_o[1]), + .tl_i2c1_i (tl_i2c_i[1]), + .tl_spi0_o (tl_spi_o[0]), + .tl_spi0_i (tl_spi_i[0]), + .tl_spi1_o (tl_spi_o[1]), + .tl_spi1_i (tl_spi_i[1]), + .tl_spi2_o (tl_spi_o[2]), + .tl_spi2_i (tl_spi_i[2]), + .tl_spi3_o (tl_spi_o[3]), + .tl_spi3_i (tl_spi_i[3]), + .tl_spi4_o (tl_spi_o[4]), + .tl_spi4_i (tl_spi_i[4]), + .tl_usbdev_o (tl_usbdev_o), + .tl_usbdev_i (tl_usbdev_i), + .tl_rv_plic_o (tl_rv_plic_o), + .tl_rv_plic_i (tl_rv_plic_i), + + .scanmode_i (prim_mubi_pkg::MuBi4False) + ); + + xbar_peri xbar2 ( + // Clock and reset. + .clk_sys_i (clk_sys_i), + .rst_sys_ni (rst_sys_ni), + + // Host interfaces. + .tl_main_i (tl_main_to_peri), + .tl_main_o (tl_peri_to_main), + + // Device interfaces. .tl_gpio_o (tl_gpio_o), .tl_gpio_i (tl_gpio_i), .tl_pinmux_o (tl_pinmux_o), @@ -101,24 +139,6 @@ module sonata_xbar_main .tl_uart3_i (tl_uart_i[3]), .tl_uart4_o (tl_uart_o[4]), .tl_uart4_i (tl_uart_i[4]), - .tl_i2c0_o (tl_i2c_o[0]), - .tl_i2c0_i (tl_i2c_i[0]), - .tl_i2c1_o (tl_i2c_o[1]), - .tl_i2c1_i (tl_i2c_i[1]), - .tl_spi0_o (tl_spi_o[0]), - .tl_spi0_i (tl_spi_i[0]), - .tl_spi1_o (tl_spi_o[1]), - .tl_spi1_i (tl_spi_i[1]), - .tl_spi2_o (tl_spi_o[2]), - .tl_spi2_i (tl_spi_i[2]), - .tl_spi3_o (tl_spi_o[3]), - .tl_spi3_i (tl_spi_i[3]), - .tl_spi4_o (tl_spi_o[4]), - .tl_spi4_i (tl_spi_i[4]), - .tl_usbdev_o (tl_usbdev_o), - .tl_usbdev_i (tl_usbdev_i), - .tl_rv_plic_o (tl_rv_plic_o), - .tl_rv_plic_i (tl_rv_plic_i), .scanmode_i (prim_mubi_pkg::MuBi4False) ); diff --git a/rtl/bus/tl_main_pkg.sv b/rtl/bus/tl_main_pkg.sv index ca7d6c4f7..3f8480dcb 100644 --- a/rtl/bus/tl_main_pkg.sv +++ b/rtl/bus/tl_main_pkg.sv @@ -6,87 +6,51 @@ package tl_main_pkg; - localparam logic [31:0] ADDR_SPACE_SRAM = 32'h 00100000; - localparam logic [31:0] ADDR_SPACE_HYPERRAM = 32'h 40000000; - localparam logic [31:0] ADDR_SPACE_REV_TAG = 32'h 30000000; - localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 80000000; - localparam logic [31:0] ADDR_SPACE_PINMUX = 32'h 80005000; - localparam logic [31:0] ADDR_SPACE_RGBLED_CTRL = 32'h 80009000; - localparam logic [31:0] ADDR_SPACE_HW_REV = 32'h 8000a000; - localparam logic [31:0] ADDR_SPACE_XADC = 32'h 8000b000; - localparam logic [31:0] ADDR_SPACE_SYSTEM_INFO = 32'h 8000c000; - localparam logic [31:0] ADDR_SPACE_TIMER = 32'h 80040000; - localparam logic [31:0] ADDR_SPACE_PWM0 = 32'h 80001000; - localparam logic [31:0] ADDR_SPACE_UART0 = 32'h 80100000; - localparam logic [31:0] ADDR_SPACE_UART1 = 32'h 80101000; - localparam logic [31:0] ADDR_SPACE_UART2 = 32'h 80102000; - localparam logic [31:0] ADDR_SPACE_UART3 = 32'h 80103000; - localparam logic [31:0] ADDR_SPACE_UART4 = 32'h 80104000; - localparam logic [31:0] ADDR_SPACE_I2C0 = 32'h 80200000; - localparam logic [31:0] ADDR_SPACE_I2C1 = 32'h 80201000; - localparam logic [31:0] ADDR_SPACE_SPI0 = 32'h 80300000; - localparam logic [31:0] ADDR_SPACE_SPI1 = 32'h 80301000; - localparam logic [31:0] ADDR_SPACE_SPI2 = 32'h 80302000; - localparam logic [31:0] ADDR_SPACE_SPI3 = 32'h 80303000; - localparam logic [31:0] ADDR_SPACE_SPI4 = 32'h 80304000; - localparam logic [31:0] ADDR_SPACE_USBDEV = 32'h 80400000; - localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 88000000; + localparam logic [31:0] ADDR_SPACE_SRAM = 32'h 00100000; + localparam logic [31:0] ADDR_SPACE_HYPERRAM = 32'h 40000000; + localparam logic [31:0] ADDR_SPACE_REV_TAG = 32'h 30000000; + localparam logic [31:0] ADDR_SPACE_PERI = 32'h 80000000; + localparam logic [31:0] ADDR_SPACE_I2C0 = 32'h 80200000; + localparam logic [31:0] ADDR_SPACE_I2C1 = 32'h 80201000; + localparam logic [31:0] ADDR_SPACE_SPI0 = 32'h 80300000; + localparam logic [31:0] ADDR_SPACE_SPI1 = 32'h 80301000; + localparam logic [31:0] ADDR_SPACE_SPI2 = 32'h 80302000; + localparam logic [31:0] ADDR_SPACE_SPI3 = 32'h 80303000; + localparam logic [31:0] ADDR_SPACE_SPI4 = 32'h 80304000; + localparam logic [31:0] ADDR_SPACE_USBDEV = 32'h 80400000; + localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 88000000; - localparam logic [31:0] ADDR_MASK_SRAM = 32'h 0003ffff; - localparam logic [31:0] ADDR_MASK_HYPERRAM = 32'h 000fffff; - localparam logic [31:0] ADDR_MASK_REV_TAG = 32'h 00003fff; - localparam logic [31:0] ADDR_MASK_GPIO = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_PINMUX = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_RGBLED_CTRL = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_HW_REV = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_XADC = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_SYSTEM_INFO = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_TIMER = 32'h 0000ffff; - localparam logic [31:0] ADDR_MASK_PWM0 = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_UART0 = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_UART1 = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_UART2 = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_UART3 = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_UART4 = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_I2C0 = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_I2C1 = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_SPI0 = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_SPI1 = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_SPI2 = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_SPI3 = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_SPI4 = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_USBDEV = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_RV_PLIC = 32'h 03ffffff; + localparam logic [31:0] ADDR_MASK_SRAM = 32'h 0003ffff; + localparam logic [31:0] ADDR_MASK_HYPERRAM = 32'h 000fffff; + localparam logic [31:0] ADDR_MASK_REV_TAG = 32'h 00003fff; + localparam logic [31:0] ADDR_MASK_PERI = 32'h 001fffff; + localparam logic [31:0] ADDR_MASK_I2C0 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_I2C1 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_SPI0 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_SPI1 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_SPI2 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_SPI3 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_SPI4 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_USBDEV = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_RV_PLIC = 32'h 03ffffff; localparam int N_HOST = 2; - localparam int N_DEVICE = 25; + localparam int N_DEVICE = 13; typedef enum int { TlSram = 0, TlHyperram = 1, TlRevTag = 2, - TlGpio = 3, - TlPinmux = 4, - TlRgbledCtrl = 5, - TlHwRev = 6, - TlXadc = 7, - TlSystemInfo = 8, - TlTimer = 9, - TlPwm0 = 10, - TlUart0 = 11, - TlUart1 = 12, - TlUart2 = 13, - TlUart3 = 14, - TlUart4 = 15, - TlI2C0 = 16, - TlI2C1 = 17, - TlSpi0 = 18, - TlSpi1 = 19, - TlSpi2 = 20, - TlSpi3 = 21, - TlSpi4 = 22, - TlUsbdev = 23, - TlRvPlic = 24 + TlPeri = 3, + TlI2C0 = 4, + TlI2C1 = 5, + TlSpi0 = 6, + TlSpi1 = 7, + TlSpi2 = 8, + TlSpi3 = 9, + TlSpi4 = 10, + TlUsbdev = 11, + TlRvPlic = 12 } tl_device_e; typedef enum int { diff --git a/rtl/bus/tl_peri_pkg.sv b/rtl/bus/tl_peri_pkg.sv new file mode 100644 index 000000000..30da29663 --- /dev/null +++ b/rtl/bus/tl_peri_pkg.sv @@ -0,0 +1,60 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tl_peri package generated by `tlgen.py` tool + +package tl_peri_pkg; + + localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 80000000; + localparam logic [31:0] ADDR_SPACE_PINMUX = 32'h 80005000; + localparam logic [31:0] ADDR_SPACE_RGBLED_CTRL = 32'h 80009000; + localparam logic [31:0] ADDR_SPACE_HW_REV = 32'h 8000a000; + localparam logic [31:0] ADDR_SPACE_XADC = 32'h 8000b000; + localparam logic [31:0] ADDR_SPACE_SYSTEM_INFO = 32'h 8000c000; + localparam logic [31:0] ADDR_SPACE_TIMER = 32'h 80040000; + localparam logic [31:0] ADDR_SPACE_PWM0 = 32'h 80001000; + localparam logic [31:0] ADDR_SPACE_UART0 = 32'h 80100000; + localparam logic [31:0] ADDR_SPACE_UART1 = 32'h 80101000; + localparam logic [31:0] ADDR_SPACE_UART2 = 32'h 80102000; + localparam logic [31:0] ADDR_SPACE_UART3 = 32'h 80103000; + localparam logic [31:0] ADDR_SPACE_UART4 = 32'h 80104000; + + localparam logic [31:0] ADDR_MASK_GPIO = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_PINMUX = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_RGBLED_CTRL = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_HW_REV = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_XADC = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_SYSTEM_INFO = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_TIMER = 32'h 0000ffff; + localparam logic [31:0] ADDR_MASK_PWM0 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_UART0 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_UART1 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_UART2 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_UART3 = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_UART4 = 32'h 00000fff; + + localparam int N_HOST = 1; + localparam int N_DEVICE = 13; + + typedef enum int { + TlGpio = 0, + TlPinmux = 1, + TlRgbledCtrl = 2, + TlHwRev = 3, + TlXadc = 4, + TlSystemInfo = 5, + TlTimer = 6, + TlPwm0 = 7, + TlUart0 = 8, + TlUart1 = 9, + TlUart2 = 10, + TlUart3 = 11, + TlUart4 = 12 + } tl_device_e; + + typedef enum int { + TlMain = 0 + } tl_host_e; + +endpackage diff --git a/rtl/bus/xbar_main.sv b/rtl/bus/xbar_main.sv index 927ff2c1e..8b60d4f1c 100644 --- a/rtl/bus/xbar_main.sv +++ b/rtl/bus/xbar_main.sv @@ -7,24 +7,12 @@ // // Interconnect // ibex_lsu -// -> s1n_27 -// -> sm1_28 +// -> s1n_15 +// -> sm1_16 // -> sram // -> hyperram // -> rev_tag -// -> gpio -// -> pinmux -// -> system_info -// -> rgbled_ctrl -// -> hw_rev -// -> xadc -// -> timer -// -> pwm0 -// -> uart0 -// -> uart1 -// -> uart2 -// -> uart3 -// -> uart4 +// -> peri // -> i2c0 // -> i2c1 // -> spi0 @@ -32,11 +20,11 @@ // -> spi2 // -> spi3 // -> spi4 -// -> asf_29 +// -> asf_17 // -> usbdev // -> rv_plic // dbg_host -// -> sm1_28 +// -> sm1_16 // -> sram module xbar_main ( @@ -58,32 +46,8 @@ module xbar_main ( input tlul_pkg::tl_d2h_t tl_hyperram_i, output tlul_pkg::tl_h2d_t tl_rev_tag_o, input tlul_pkg::tl_d2h_t tl_rev_tag_i, - output tlul_pkg::tl_h2d_t tl_gpio_o, - input tlul_pkg::tl_d2h_t tl_gpio_i, - output tlul_pkg::tl_h2d_t tl_pinmux_o, - input tlul_pkg::tl_d2h_t tl_pinmux_i, - output tlul_pkg::tl_h2d_t tl_rgbled_ctrl_o, - input tlul_pkg::tl_d2h_t tl_rgbled_ctrl_i, - output tlul_pkg::tl_h2d_t tl_hw_rev_o, - input tlul_pkg::tl_d2h_t tl_hw_rev_i, - output tlul_pkg::tl_h2d_t tl_xadc_o, - input tlul_pkg::tl_d2h_t tl_xadc_i, - output tlul_pkg::tl_h2d_t tl_system_info_o, - input tlul_pkg::tl_d2h_t tl_system_info_i, - output tlul_pkg::tl_h2d_t tl_timer_o, - input tlul_pkg::tl_d2h_t tl_timer_i, - output tlul_pkg::tl_h2d_t tl_pwm0_o, - input tlul_pkg::tl_d2h_t tl_pwm0_i, - output tlul_pkg::tl_h2d_t tl_uart0_o, - input tlul_pkg::tl_d2h_t tl_uart0_i, - output tlul_pkg::tl_h2d_t tl_uart1_o, - input tlul_pkg::tl_d2h_t tl_uart1_i, - output tlul_pkg::tl_h2d_t tl_uart2_o, - input tlul_pkg::tl_d2h_t tl_uart2_i, - output tlul_pkg::tl_h2d_t tl_uart3_o, - input tlul_pkg::tl_d2h_t tl_uart3_i, - output tlul_pkg::tl_h2d_t tl_uart4_o, - input tlul_pkg::tl_d2h_t tl_uart4_i, + output tlul_pkg::tl_h2d_t tl_peri_o, + input tlul_pkg::tl_d2h_t tl_peri_i, output tlul_pkg::tl_h2d_t tl_i2c0_o, input tlul_pkg::tl_d2h_t tl_i2c0_i, output tlul_pkg::tl_h2d_t tl_i2c1_o, @@ -114,219 +78,135 @@ module xbar_main ( logic unused_scanmode; assign unused_scanmode = ^scanmode_i; - tl_h2d_t tl_s1n_27_us_h2d ; - tl_d2h_t tl_s1n_27_us_d2h ; + tl_h2d_t tl_s1n_15_us_h2d ; + tl_d2h_t tl_s1n_15_us_d2h ; - tl_h2d_t tl_s1n_27_ds_h2d [25]; - tl_d2h_t tl_s1n_27_ds_d2h [25]; + tl_h2d_t tl_s1n_15_ds_h2d [13]; + tl_d2h_t tl_s1n_15_ds_d2h [13]; // Create steering signal - logic [4:0] dev_sel_s1n_27; + logic [3:0] dev_sel_s1n_15; - tl_h2d_t tl_sm1_28_us_h2d [2]; - tl_d2h_t tl_sm1_28_us_d2h [2]; + tl_h2d_t tl_sm1_16_us_h2d [2]; + tl_d2h_t tl_sm1_16_us_d2h [2]; - tl_h2d_t tl_sm1_28_ds_h2d ; - tl_d2h_t tl_sm1_28_ds_d2h ; + tl_h2d_t tl_sm1_16_ds_h2d ; + tl_d2h_t tl_sm1_16_ds_d2h ; - tl_h2d_t tl_asf_29_us_h2d ; - tl_d2h_t tl_asf_29_us_d2h ; - tl_h2d_t tl_asf_29_ds_h2d ; - tl_d2h_t tl_asf_29_ds_d2h ; + tl_h2d_t tl_asf_17_us_h2d ; + tl_d2h_t tl_asf_17_us_d2h ; + tl_h2d_t tl_asf_17_ds_h2d ; + tl_d2h_t tl_asf_17_ds_d2h ; - assign tl_sm1_28_us_h2d[0] = tl_s1n_27_ds_h2d[0]; - assign tl_s1n_27_ds_d2h[0] = tl_sm1_28_us_d2h[0]; + assign tl_sm1_16_us_h2d[0] = tl_s1n_15_ds_h2d[0]; + assign tl_s1n_15_ds_d2h[0] = tl_sm1_16_us_d2h[0]; - assign tl_hyperram_o = tl_s1n_27_ds_h2d[1]; - assign tl_s1n_27_ds_d2h[1] = tl_hyperram_i; + assign tl_hyperram_o = tl_s1n_15_ds_h2d[1]; + assign tl_s1n_15_ds_d2h[1] = tl_hyperram_i; - assign tl_rev_tag_o = tl_s1n_27_ds_h2d[2]; - assign tl_s1n_27_ds_d2h[2] = tl_rev_tag_i; + assign tl_rev_tag_o = tl_s1n_15_ds_h2d[2]; + assign tl_s1n_15_ds_d2h[2] = tl_rev_tag_i; - assign tl_gpio_o = tl_s1n_27_ds_h2d[3]; - assign tl_s1n_27_ds_d2h[3] = tl_gpio_i; + assign tl_peri_o = tl_s1n_15_ds_h2d[3]; + assign tl_s1n_15_ds_d2h[3] = tl_peri_i; - assign tl_pinmux_o = tl_s1n_27_ds_h2d[4]; - assign tl_s1n_27_ds_d2h[4] = tl_pinmux_i; + assign tl_i2c0_o = tl_s1n_15_ds_h2d[4]; + assign tl_s1n_15_ds_d2h[4] = tl_i2c0_i; - assign tl_system_info_o = tl_s1n_27_ds_h2d[5]; - assign tl_s1n_27_ds_d2h[5] = tl_system_info_i; + assign tl_i2c1_o = tl_s1n_15_ds_h2d[5]; + assign tl_s1n_15_ds_d2h[5] = tl_i2c1_i; - assign tl_rgbled_ctrl_o = tl_s1n_27_ds_h2d[6]; - assign tl_s1n_27_ds_d2h[6] = tl_rgbled_ctrl_i; + assign tl_spi0_o = tl_s1n_15_ds_h2d[6]; + assign tl_s1n_15_ds_d2h[6] = tl_spi0_i; - assign tl_hw_rev_o = tl_s1n_27_ds_h2d[7]; - assign tl_s1n_27_ds_d2h[7] = tl_hw_rev_i; + assign tl_spi1_o = tl_s1n_15_ds_h2d[7]; + assign tl_s1n_15_ds_d2h[7] = tl_spi1_i; - assign tl_xadc_o = tl_s1n_27_ds_h2d[8]; - assign tl_s1n_27_ds_d2h[8] = tl_xadc_i; + assign tl_spi2_o = tl_s1n_15_ds_h2d[8]; + assign tl_s1n_15_ds_d2h[8] = tl_spi2_i; - assign tl_timer_o = tl_s1n_27_ds_h2d[9]; - assign tl_s1n_27_ds_d2h[9] = tl_timer_i; + assign tl_spi3_o = tl_s1n_15_ds_h2d[9]; + assign tl_s1n_15_ds_d2h[9] = tl_spi3_i; - assign tl_pwm0_o = tl_s1n_27_ds_h2d[10]; - assign tl_s1n_27_ds_d2h[10] = tl_pwm0_i; + assign tl_spi4_o = tl_s1n_15_ds_h2d[10]; + assign tl_s1n_15_ds_d2h[10] = tl_spi4_i; - assign tl_uart0_o = tl_s1n_27_ds_h2d[11]; - assign tl_s1n_27_ds_d2h[11] = tl_uart0_i; + assign tl_asf_17_us_h2d = tl_s1n_15_ds_h2d[11]; + assign tl_s1n_15_ds_d2h[11] = tl_asf_17_us_d2h; - assign tl_uart1_o = tl_s1n_27_ds_h2d[12]; - assign tl_s1n_27_ds_d2h[12] = tl_uart1_i; + assign tl_rv_plic_o = tl_s1n_15_ds_h2d[12]; + assign tl_s1n_15_ds_d2h[12] = tl_rv_plic_i; - assign tl_uart2_o = tl_s1n_27_ds_h2d[13]; - assign tl_s1n_27_ds_d2h[13] = tl_uart2_i; + assign tl_sm1_16_us_h2d[1] = tl_dbg_host_i; + assign tl_dbg_host_o = tl_sm1_16_us_d2h[1]; - assign tl_uart3_o = tl_s1n_27_ds_h2d[14]; - assign tl_s1n_27_ds_d2h[14] = tl_uart3_i; + assign tl_s1n_15_us_h2d = tl_ibex_lsu_i; + assign tl_ibex_lsu_o = tl_s1n_15_us_d2h; - assign tl_uart4_o = tl_s1n_27_ds_h2d[15]; - assign tl_s1n_27_ds_d2h[15] = tl_uart4_i; + assign tl_sram_o = tl_sm1_16_ds_h2d; + assign tl_sm1_16_ds_d2h = tl_sram_i; - assign tl_i2c0_o = tl_s1n_27_ds_h2d[16]; - assign tl_s1n_27_ds_d2h[16] = tl_i2c0_i; - - assign tl_i2c1_o = tl_s1n_27_ds_h2d[17]; - assign tl_s1n_27_ds_d2h[17] = tl_i2c1_i; - - assign tl_spi0_o = tl_s1n_27_ds_h2d[18]; - assign tl_s1n_27_ds_d2h[18] = tl_spi0_i; - - assign tl_spi1_o = tl_s1n_27_ds_h2d[19]; - assign tl_s1n_27_ds_d2h[19] = tl_spi1_i; - - assign tl_spi2_o = tl_s1n_27_ds_h2d[20]; - assign tl_s1n_27_ds_d2h[20] = tl_spi2_i; - - assign tl_spi3_o = tl_s1n_27_ds_h2d[21]; - assign tl_s1n_27_ds_d2h[21] = tl_spi3_i; - - assign tl_spi4_o = tl_s1n_27_ds_h2d[22]; - assign tl_s1n_27_ds_d2h[22] = tl_spi4_i; - - assign tl_asf_29_us_h2d = tl_s1n_27_ds_h2d[23]; - assign tl_s1n_27_ds_d2h[23] = tl_asf_29_us_d2h; - - assign tl_rv_plic_o = tl_s1n_27_ds_h2d[24]; - assign tl_s1n_27_ds_d2h[24] = tl_rv_plic_i; - - assign tl_sm1_28_us_h2d[1] = tl_dbg_host_i; - assign tl_dbg_host_o = tl_sm1_28_us_d2h[1]; - - assign tl_s1n_27_us_h2d = tl_ibex_lsu_i; - assign tl_ibex_lsu_o = tl_s1n_27_us_d2h; - - assign tl_sram_o = tl_sm1_28_ds_h2d; - assign tl_sm1_28_ds_d2h = tl_sram_i; - - assign tl_usbdev_o = tl_asf_29_ds_h2d; - assign tl_asf_29_ds_d2h = tl_usbdev_i; + assign tl_usbdev_o = tl_asf_17_ds_h2d; + assign tl_asf_17_ds_d2h = tl_usbdev_i; always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_27 = 5'd25; - if ((tl_s1n_27_us_h2d.a_address & + dev_sel_s1n_15 = 4'd13; + if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_SRAM)) == ADDR_SPACE_SRAM) begin - dev_sel_s1n_27 = 5'd0; + dev_sel_s1n_15 = 4'd0; - end else if ((tl_s1n_27_us_h2d.a_address & + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_HYPERRAM)) == ADDR_SPACE_HYPERRAM) begin - dev_sel_s1n_27 = 5'd1; + dev_sel_s1n_15 = 4'd1; - end else if ((tl_s1n_27_us_h2d.a_address & + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_REV_TAG)) == ADDR_SPACE_REV_TAG) begin - dev_sel_s1n_27 = 5'd2; - - end else if ((tl_s1n_27_us_h2d.a_address & - ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin - dev_sel_s1n_27 = 5'd3; - - end else if ((tl_s1n_27_us_h2d.a_address & - ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin - dev_sel_s1n_27 = 5'd4; - - end else if ((tl_s1n_27_us_h2d.a_address & - ~(ADDR_MASK_SYSTEM_INFO)) == ADDR_SPACE_SYSTEM_INFO) begin - dev_sel_s1n_27 = 5'd5; - - end else if ((tl_s1n_27_us_h2d.a_address & - ~(ADDR_MASK_RGBLED_CTRL)) == ADDR_SPACE_RGBLED_CTRL) begin - dev_sel_s1n_27 = 5'd6; - - end else if ((tl_s1n_27_us_h2d.a_address & - ~(ADDR_MASK_HW_REV)) == ADDR_SPACE_HW_REV) begin - dev_sel_s1n_27 = 5'd7; - - end else if ((tl_s1n_27_us_h2d.a_address & - ~(ADDR_MASK_XADC)) == ADDR_SPACE_XADC) begin - dev_sel_s1n_27 = 5'd8; - - end else if ((tl_s1n_27_us_h2d.a_address & - ~(ADDR_MASK_TIMER)) == ADDR_SPACE_TIMER) begin - dev_sel_s1n_27 = 5'd9; - - end else if ((tl_s1n_27_us_h2d.a_address & - ~(ADDR_MASK_PWM0)) == ADDR_SPACE_PWM0) begin - dev_sel_s1n_27 = 5'd10; - - end else if ((tl_s1n_27_us_h2d.a_address & - ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin - dev_sel_s1n_27 = 5'd11; - - end else if ((tl_s1n_27_us_h2d.a_address & - ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin - dev_sel_s1n_27 = 5'd12; - - end else if ((tl_s1n_27_us_h2d.a_address & - ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin - dev_sel_s1n_27 = 5'd13; - - end else if ((tl_s1n_27_us_h2d.a_address & - ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin - dev_sel_s1n_27 = 5'd14; + dev_sel_s1n_15 = 4'd2; - end else if ((tl_s1n_27_us_h2d.a_address & - ~(ADDR_MASK_UART4)) == ADDR_SPACE_UART4) begin - dev_sel_s1n_27 = 5'd15; + end else if ((tl_s1n_15_us_h2d.a_address & + ~(ADDR_MASK_PERI)) == ADDR_SPACE_PERI) begin + dev_sel_s1n_15 = 4'd3; - end else if ((tl_s1n_27_us_h2d.a_address & + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin - dev_sel_s1n_27 = 5'd16; + dev_sel_s1n_15 = 4'd4; - end else if ((tl_s1n_27_us_h2d.a_address & + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_I2C1)) == ADDR_SPACE_I2C1) begin - dev_sel_s1n_27 = 5'd17; + dev_sel_s1n_15 = 4'd5; - end else if ((tl_s1n_27_us_h2d.a_address & + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_SPI0)) == ADDR_SPACE_SPI0) begin - dev_sel_s1n_27 = 5'd18; + dev_sel_s1n_15 = 4'd6; - end else if ((tl_s1n_27_us_h2d.a_address & + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_SPI1)) == ADDR_SPACE_SPI1) begin - dev_sel_s1n_27 = 5'd19; + dev_sel_s1n_15 = 4'd7; - end else if ((tl_s1n_27_us_h2d.a_address & + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_SPI2)) == ADDR_SPACE_SPI2) begin - dev_sel_s1n_27 = 5'd20; + dev_sel_s1n_15 = 4'd8; - end else if ((tl_s1n_27_us_h2d.a_address & + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_SPI3)) == ADDR_SPACE_SPI3) begin - dev_sel_s1n_27 = 5'd21; + dev_sel_s1n_15 = 4'd9; - end else if ((tl_s1n_27_us_h2d.a_address & + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_SPI4)) == ADDR_SPACE_SPI4) begin - dev_sel_s1n_27 = 5'd22; + dev_sel_s1n_15 = 4'd10; - end else if ((tl_s1n_27_us_h2d.a_address & + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin - dev_sel_s1n_27 = 5'd23; + dev_sel_s1n_15 = 4'd11; - end else if ((tl_s1n_27_us_h2d.a_address & + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin - dev_sel_s1n_27 = 5'd24; + dev_sel_s1n_15 = 4'd12; end end @@ -335,19 +215,19 @@ end tlul_socket_1n #( .HReqDepth (4'h0), .HRspDepth (4'h0), - .DReqPass (25'hfc02a7), - .DRspPass (25'hfc02a7), - .DReqDepth (100'h1000000111111110101011000), - .DRspDepth (100'h1000000111111110101011000), - .N (25) - ) u_s1n_27 ( + .DReqPass (13'h1fc7), + .DRspPass (13'h1fc7), + .DReqDepth (52'h111000), + .DRspDepth (52'h111000), + .N (13) + ) u_s1n_15 ( .clk_i (clk_sys_i), .rst_ni (rst_sys_ni), - .tl_h_i (tl_s1n_27_us_h2d), - .tl_h_o (tl_s1n_27_us_d2h), - .tl_d_o (tl_s1n_27_ds_h2d), - .tl_d_i (tl_s1n_27_ds_d2h), - .dev_select_i (dev_sel_s1n_27) + .tl_h_i (tl_s1n_15_us_h2d), + .tl_h_o (tl_s1n_15_us_d2h), + .tl_d_o (tl_s1n_15_ds_h2d), + .tl_d_i (tl_s1n_15_ds_d2h), + .dev_select_i (dev_sel_s1n_15) ); tlul_socket_m1 #( .HReqPass (2'h1), @@ -356,26 +236,26 @@ end .DReqDepth (4'h0), .DRspDepth (4'h0), .M (2) - ) u_sm1_28 ( + ) u_sm1_16 ( .clk_i (clk_sys_i), .rst_ni (rst_sys_ni), - .tl_h_i (tl_sm1_28_us_h2d), - .tl_h_o (tl_sm1_28_us_d2h), - .tl_d_o (tl_sm1_28_ds_h2d), - .tl_d_i (tl_sm1_28_ds_d2h) + .tl_h_i (tl_sm1_16_us_h2d), + .tl_h_o (tl_sm1_16_us_d2h), + .tl_d_o (tl_sm1_16_ds_h2d), + .tl_d_i (tl_sm1_16_ds_d2h) ); tlul_fifo_async #( .ReqDepth (1), .RspDepth (1) - ) u_asf_29 ( + ) u_asf_17 ( .clk_h_i (clk_sys_i), .rst_h_ni (rst_sys_ni), .clk_d_i (clk_usb_i), .rst_d_ni (rst_usb_ni), - .tl_h_i (tl_asf_29_us_h2d), - .tl_h_o (tl_asf_29_us_d2h), - .tl_d_o (tl_asf_29_ds_h2d), - .tl_d_i (tl_asf_29_ds_d2h) + .tl_h_i (tl_asf_17_us_h2d), + .tl_h_o (tl_asf_17_us_d2h), + .tl_d_o (tl_asf_17_ds_h2d), + .tl_d_i (tl_asf_17_ds_d2h) ); endmodule diff --git a/rtl/bus/xbar_peri.core b/rtl/bus/xbar_peri.core new file mode 100644 index 000000000..77b44ab6c --- /dev/null +++ b/rtl/bus/xbar_peri.core @@ -0,0 +1,24 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_peri core file generated by `tlgen.py` tool +name: "lowrisc:ip:xbar_peri:0.1" +description: "Generated RTL xbar_peri" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + files: + - tl_peri_pkg.sv + - xbar_peri.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_rtl + toplevel: xbar_peri diff --git a/rtl/bus/xbar_peri.sv b/rtl/bus/xbar_peri.sv new file mode 100644 index 000000000..00dbe6e2a --- /dev/null +++ b/rtl/bus/xbar_peri.sv @@ -0,0 +1,201 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri module generated by `tlgen.py` tool +// all reset signals should be generated from one reset signal to not make any deadlock +// +// Interconnect +// main +// -> s1n_14 +// -> gpio +// -> pinmux +// -> system_info +// -> rgbled_ctrl +// -> hw_rev +// -> xadc +// -> timer +// -> pwm0 +// -> uart0 +// -> uart1 +// -> uart2 +// -> uart3 +// -> uart4 + +module xbar_peri ( + input clk_sys_i, + input rst_sys_ni, + + // Host interfaces + input tlul_pkg::tl_h2d_t tl_main_i, + output tlul_pkg::tl_d2h_t tl_main_o, + + // Device interfaces + output tlul_pkg::tl_h2d_t tl_gpio_o, + input tlul_pkg::tl_d2h_t tl_gpio_i, + output tlul_pkg::tl_h2d_t tl_pinmux_o, + input tlul_pkg::tl_d2h_t tl_pinmux_i, + output tlul_pkg::tl_h2d_t tl_rgbled_ctrl_o, + input tlul_pkg::tl_d2h_t tl_rgbled_ctrl_i, + output tlul_pkg::tl_h2d_t tl_hw_rev_o, + input tlul_pkg::tl_d2h_t tl_hw_rev_i, + output tlul_pkg::tl_h2d_t tl_xadc_o, + input tlul_pkg::tl_d2h_t tl_xadc_i, + output tlul_pkg::tl_h2d_t tl_system_info_o, + input tlul_pkg::tl_d2h_t tl_system_info_i, + output tlul_pkg::tl_h2d_t tl_timer_o, + input tlul_pkg::tl_d2h_t tl_timer_i, + output tlul_pkg::tl_h2d_t tl_pwm0_o, + input tlul_pkg::tl_d2h_t tl_pwm0_i, + output tlul_pkg::tl_h2d_t tl_uart0_o, + input tlul_pkg::tl_d2h_t tl_uart0_i, + output tlul_pkg::tl_h2d_t tl_uart1_o, + input tlul_pkg::tl_d2h_t tl_uart1_i, + output tlul_pkg::tl_h2d_t tl_uart2_o, + input tlul_pkg::tl_d2h_t tl_uart2_i, + output tlul_pkg::tl_h2d_t tl_uart3_o, + input tlul_pkg::tl_d2h_t tl_uart3_i, + output tlul_pkg::tl_h2d_t tl_uart4_o, + input tlul_pkg::tl_d2h_t tl_uart4_i, + + input prim_mubi_pkg::mubi4_t scanmode_i +); + + import tlul_pkg::*; + import tl_peri_pkg::*; + + // scanmode_i is currently not used, but provisioned for future use + // this assignment prevents lint warnings + logic unused_scanmode; + assign unused_scanmode = ^scanmode_i; + + tl_h2d_t tl_s1n_14_us_h2d ; + tl_d2h_t tl_s1n_14_us_d2h ; + + + tl_h2d_t tl_s1n_14_ds_h2d [13]; + tl_d2h_t tl_s1n_14_ds_d2h [13]; + + // Create steering signal + logic [3:0] dev_sel_s1n_14; + + + + assign tl_gpio_o = tl_s1n_14_ds_h2d[0]; + assign tl_s1n_14_ds_d2h[0] = tl_gpio_i; + + assign tl_pinmux_o = tl_s1n_14_ds_h2d[1]; + assign tl_s1n_14_ds_d2h[1] = tl_pinmux_i; + + assign tl_system_info_o = tl_s1n_14_ds_h2d[2]; + assign tl_s1n_14_ds_d2h[2] = tl_system_info_i; + + assign tl_rgbled_ctrl_o = tl_s1n_14_ds_h2d[3]; + assign tl_s1n_14_ds_d2h[3] = tl_rgbled_ctrl_i; + + assign tl_hw_rev_o = tl_s1n_14_ds_h2d[4]; + assign tl_s1n_14_ds_d2h[4] = tl_hw_rev_i; + + assign tl_xadc_o = tl_s1n_14_ds_h2d[5]; + assign tl_s1n_14_ds_d2h[5] = tl_xadc_i; + + assign tl_timer_o = tl_s1n_14_ds_h2d[6]; + assign tl_s1n_14_ds_d2h[6] = tl_timer_i; + + assign tl_pwm0_o = tl_s1n_14_ds_h2d[7]; + assign tl_s1n_14_ds_d2h[7] = tl_pwm0_i; + + assign tl_uart0_o = tl_s1n_14_ds_h2d[8]; + assign tl_s1n_14_ds_d2h[8] = tl_uart0_i; + + assign tl_uart1_o = tl_s1n_14_ds_h2d[9]; + assign tl_s1n_14_ds_d2h[9] = tl_uart1_i; + + assign tl_uart2_o = tl_s1n_14_ds_h2d[10]; + assign tl_s1n_14_ds_d2h[10] = tl_uart2_i; + + assign tl_uart3_o = tl_s1n_14_ds_h2d[11]; + assign tl_s1n_14_ds_d2h[11] = tl_uart3_i; + + assign tl_uart4_o = tl_s1n_14_ds_h2d[12]; + assign tl_s1n_14_ds_d2h[12] = tl_uart4_i; + + assign tl_s1n_14_us_h2d = tl_main_i; + assign tl_main_o = tl_s1n_14_us_d2h; + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_14 = 4'd13; + if ((tl_s1n_14_us_h2d.a_address & + ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin + dev_sel_s1n_14 = 4'd0; + + end else if ((tl_s1n_14_us_h2d.a_address & + ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin + dev_sel_s1n_14 = 4'd1; + + end else if ((tl_s1n_14_us_h2d.a_address & + ~(ADDR_MASK_SYSTEM_INFO)) == ADDR_SPACE_SYSTEM_INFO) begin + dev_sel_s1n_14 = 4'd2; + + end else if ((tl_s1n_14_us_h2d.a_address & + ~(ADDR_MASK_RGBLED_CTRL)) == ADDR_SPACE_RGBLED_CTRL) begin + dev_sel_s1n_14 = 4'd3; + + end else if ((tl_s1n_14_us_h2d.a_address & + ~(ADDR_MASK_HW_REV)) == ADDR_SPACE_HW_REV) begin + dev_sel_s1n_14 = 4'd4; + + end else if ((tl_s1n_14_us_h2d.a_address & + ~(ADDR_MASK_XADC)) == ADDR_SPACE_XADC) begin + dev_sel_s1n_14 = 4'd5; + + end else if ((tl_s1n_14_us_h2d.a_address & + ~(ADDR_MASK_TIMER)) == ADDR_SPACE_TIMER) begin + dev_sel_s1n_14 = 4'd6; + + end else if ((tl_s1n_14_us_h2d.a_address & + ~(ADDR_MASK_PWM0)) == ADDR_SPACE_PWM0) begin + dev_sel_s1n_14 = 4'd7; + + end else if ((tl_s1n_14_us_h2d.a_address & + ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin + dev_sel_s1n_14 = 4'd8; + + end else if ((tl_s1n_14_us_h2d.a_address & + ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin + dev_sel_s1n_14 = 4'd9; + + end else if ((tl_s1n_14_us_h2d.a_address & + ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin + dev_sel_s1n_14 = 4'd10; + + end else if ((tl_s1n_14_us_h2d.a_address & + ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin + dev_sel_s1n_14 = 4'd11; + + end else if ((tl_s1n_14_us_h2d.a_address & + ~(ADDR_MASK_UART4)) == ADDR_SPACE_UART4) begin + dev_sel_s1n_14 = 4'd12; +end + end + + + // Instantiation phase + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (52'h0), + .DRspDepth (52'h0), + .N (13) + ) u_s1n_14 ( + .clk_i (clk_sys_i), + .rst_ni (rst_sys_ni), + .tl_h_i (tl_s1n_14_us_h2d), + .tl_h_o (tl_s1n_14_us_d2h), + .tl_d_o (tl_s1n_14_ds_h2d), + .tl_d_i (tl_s1n_14_ds_d2h), + .dev_select_i (dev_sel_s1n_14) + ); + +endmodule diff --git a/rtl/templates/sonata_xbar_main.sv.tpl b/rtl/templates/sonata_xbar_main.sv.tpl index 4a5262f30..f548dee13 100644 --- a/rtl/templates/sonata_xbar_main.sv.tpl +++ b/rtl/templates/sonata_xbar_main.sv.tpl @@ -53,8 +53,12 @@ module sonata_xbar_main input tlul_pkg::tl_d2h_t tl_rv_plic_i ); + // Inter-xbar interfaces + tlul_pkg::tl_h2d_t tl_main_to_peri; + tlul_pkg::tl_d2h_t tl_peri_to_main; + xbar_main xbar ( - // Clock and reset. + // Clock and reset. .clk_sys_i (clk_sys_i), .rst_sys_ni (rst_sys_ni), .clk_usb_i (clk_usb_i), @@ -73,6 +77,34 @@ module sonata_xbar_main .tl_hyperram_i (tl_hyperram_i), .tl_rev_tag_o (tl_rev_tag_o), .tl_rev_tag_i (tl_rev_tag_i), + .tl_peri_o (tl_main_to_peri), + .tl_peri_i (tl_peri_to_main), + % for block in config.blocks: + % if block.name in ["i2c", "spi"]: + % for i in range(block.instances): + .tl_${block.name}${i}_o (tl_${block.name}_o[${i}]), + .tl_${block.name}${i}_i (tl_${block.name}_i[${i}]), + % endfor + % endif + % endfor + .tl_usbdev_o (tl_usbdev_o), + .tl_usbdev_i (tl_usbdev_i), + .tl_rv_plic_o (tl_rv_plic_o), + .tl_rv_plic_i (tl_rv_plic_i), + + .scanmode_i (prim_mubi_pkg::MuBi4False) + ); + + xbar_peri xbar2 ( + // Clock and reset. + .clk_sys_i (clk_sys_i), + .rst_sys_ni (rst_sys_ni), + + // Host interfaces. + .tl_main_i (tl_main_to_peri), + .tl_main_o (tl_peri_to_main), + + // Device interfaces. .tl_gpio_o (tl_gpio_o), .tl_gpio_i (tl_gpio_i), .tl_pinmux_o (tl_pinmux_o), @@ -88,17 +120,13 @@ module sonata_xbar_main .tl_timer_o (tl_timer_o), .tl_timer_i (tl_timer_i), % for block in config.blocks: - % if not block.name == "gpio": + % if block.name not in ["gpio", "i2c", "spi"]: % for i in range(block.instances): .tl_${block.name}${i}_o (tl_${block.name}_o[${i}]), .tl_${block.name}${i}_i (tl_${block.name}_i[${i}]), % endfor % endif % endfor - .tl_usbdev_o (tl_usbdev_o), - .tl_usbdev_i (tl_usbdev_i), - .tl_rv_plic_o (tl_rv_plic_o), - .tl_rv_plic_i (tl_rv_plic_i), .scanmode_i (prim_mubi_pkg::MuBi4False) ); diff --git a/sonata_system.core b/sonata_system.core index 7fffb3f9b..58692ecdb 100644 --- a/sonata_system.core +++ b/sonata_system.core @@ -14,6 +14,7 @@ filesets: - lowrisc:ip:uart - lowrisc:ip:usbdev - lowrisc:ip:xbar_main + - lowrisc:ip:xbar_peri - lowrisc:ip:xbar_ifetch - lowrisc:ip:spi - lowrisc:ip:gpio diff --git a/util/generate_xbar.sh b/util/generate_xbar.sh index f03e30d42..f231c229f 100755 --- a/util/generate_xbar.sh +++ b/util/generate_xbar.sh @@ -5,6 +5,7 @@ set -e mkdir -p rtl/bus vendor/lowrisc_ip/util/tlgen.py -t data/xbar_main_generated.hjson -o rtl/bus +vendor/lowrisc_ip/util/tlgen.py -t data/xbar_peri_generated.hjson -o rtl/bus vendor/lowrisc_ip/util/tlgen.py -t data/xbar_ifetch.hjson -o rtl/bus rm -r rtl/bus/data rm -r rtl/bus/dv diff --git a/util/top_gen/generator.py b/util/top_gen/generator.py index c4c224580..357af2db9 100644 --- a/util/top_gen/generator.py +++ b/util/top_gen/generator.py @@ -330,6 +330,7 @@ def generate_top(config: TopConfig) -> None: } for template_file, output_file in ( ("data/xbar_main.hjson", "data/xbar_main_generated.hjson"), + ("data/xbar_peri.hjson", "data/xbar_peri_generated.hjson"), ( "rtl/templates/sonata_xbar_main.sv.tpl", "rtl/bus/sonata_xbar_main.sv",