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VCML Documentation

The Virtual Components Modeling Library (vcml) is an addon library for SystemC that provides facilities to ease construction of Virtual Platforms (VPs). Roughly speaking, its contributions can be separated into two areas: Modeling Primitives and Hardware Models. Modeling Primitives refer to utilities such as improved TLM sockets, port lists and registers and are intended to serve as building blocks for new models. Hardware Models, such as UARTs, Timers, Memories etc. are also available based on actual hardware models from various vendors or common implementations. These models generally work with their corresponding Linux device drivers and can be used as off-the-shelf components to swiftly assemble an entire VP.

• Documentation files for VCML modeling primitives:

  • Logging
  • Tracing
  • Components
  • Properties
  • Backends
  • Peripherals
  • Session

• Documentation for VCML hardware models:

  • Generic Memory
  • Generic Bus
  • 8250 UART
  • DS1742 RTC
  • SDHCI
  • HWRNG
  • FBDEV
  • VIRTIO Models
  • OpenCores ETHOC
  • OpenCores OMPIC
  • OpenCores OCKBD
  • OpenCores OCFBC
  • OpenCores OCSPI
  • ARM PL011 UART
  • ARM PL190 VIC
  • ARM SP804 Dual Timer
  • ARM GIC400
  • ARM PL330 DMA
  • SiFive UART
  • RISC-V CLINT
  • RISC-V PLIC
  • Simulation Loader
  • Simulation Device
  • Simulation Throttle

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Documentation January 2024