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mux4to1_8bit.v
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mux4to1_8bit.v
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module mux4to1(sel1, sel0, i0, i1, i2, i3 , f);
input sel1, sel0, i0, i1, i2, i3;
output f;
wire w1, w2, w3, w4, nsel1, nsel0;
not(nsel1, sel1);
not(nsel0, sel0);
and(w1, nsel1, nsel0, i0);
and(w2, nsel1, sel0, i1);
and(w3, sel1, nsel0, i2);
and(w4, sel1, sel0, i3);
or(f, w1, w2, w3, w4);
endmodule
module mux4to1_8bit(sel1, sel0, i0, i1, i2, i3 , f);
input sel1, sel0;
input [7:0]i3, i2, i1, i0;
output [7:0]f;
mux4to1 mux1(.sel1(sel1), .sel0(sel0), .i0(i0[0]), .i1(i1[0]), .i2(i2[0]), .i3(i3[0]), .f(f[0]));
mux4to1 mux2(.sel1(sel1), .sel0(sel0), .i0(i0[1]), .i1(i1[1]), .i2(i2[1]), .i3(i3[1]), .f(f[1]));
mux4to1 mux3(.sel1(sel1), .sel0(sel0), .i0(i0[2]), .i1(i1[2]), .i2(i2[2]), .i3(i3[2]), .f(f[2]));
mux4to1 mux4(.sel1(sel1), .sel0(sel0), .i0(i0[3]), .i1(i1[3]), .i2(i2[3]), .i3(i3[3]), .f(f[3]));
mux4to1 mux5(.sel1(sel1), .sel0(sel0), .i0(i0[4]), .i1(i1[4]), .i2(i2[4]), .i3(i3[4]), .f(f[4]));
mux4to1 mux6(.sel1(sel1), .sel0(sel0), .i0(i0[5]), .i1(i1[5]), .i2(i2[5]), .i3(i3[5]), .f(f[5]));
mux4to1 mux7(.sel1(sel1), .sel0(sel0), .i0(i0[6]), .i1(i1[6]), .i2(i2[6]), .i3(i3[6]), .f(f[6]));
mux4to1 mux8(.sel1(sel1), .sel0(sel0), .i0(i0[7]), .i1(i1[7]), .i2(i2[7]), .i3(i3[7]), .f(f[7]));
endmodule
module test_bench_mux4to1_8bit;
reg [7:0]i0_t, i1_t, i2_t, i3_t;
reg sel1_t, sel0_t;
wire [7:0]f_t;
mux4to1_8bit mux(.sel1(sel1_t), .sel0(sel0_t), .i0(i0_t), .i1(i1_t), .i2(i2_t), .i3(i3_t), .f(f_t));
initial begin
$monitor("sel1=%b, sel0=%b, i0=%b, i1=%b, i2=%b, i3=%b f=%b", sel1_t, sel0_t, i0_t, i1_t, i2_t, i3_t, f_t);
sel1_t=1'b0; sel0_t=1'b0; i0_t=8'b10100100; i1_t=8'b00001111; i2_t=8'b00011101; i3_t=8'b10011100;
end
endmodule