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usart.h
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#ifndef _USART_H_
#define _USART_H_
/************************************************************************************
* Author: jnk0le@hotmail.com *
* https://github.com/jnk0le *
* This library is distributed under MIT license terms *
************************************************************************************/
#include <avr/io.h> // for inline func
#include "usart_config.h"
#ifndef F_CPU
#warning F_CPU is undefined, USART may not work correctly without this
#endif
#define BAUD_CALC(x) ((F_CPU+(x)*8UL) / (16UL*(x))-1UL) // macro calculating precise UBRR value
#define BAUD_CALC_FAST(x) ((F_CPU)/(BAUD*16UL)-1) // for faster real time calculations ?
#define DOUBLE_BAUD_CALC(x) ((F_CPU+(x)*4UL) / (8UL*(x))-1UL) // macro calculating UBRR value for double speed
#if !defined(__OPTIMIZE__)&&!defined(USART_NO_ABI_BREAKING_PREMATURES)
// #warning "Compiler optimizations disabled; functions from usart.h might not work as designed"
#endif
#ifdef DEBUG
#define USART_NO_ABI_BREAKING_PREMATURES
#endif
#ifndef __AVR_ARCH__ // compiler fault ?
#define USART_NO_ABI_BREAKING_PREMATURES
#endif
#ifndef RX_BUFFER_SIZE
#define RX_BUFFER_SIZE 64 // Size of the ring buffers, must be power of 2
#endif
#ifndef TX_BUFFER_SIZE
#define TX_BUFFER_SIZE 64 // Size of the ring buffers, must be power of 2
#endif
#ifndef TX0_BUFFER_SIZE
#define TX0_BUFFER_SIZE TX_BUFFER_SIZE
#endif
#ifndef RX0_BUFFER_SIZE
#define RX0_BUFFER_SIZE RX_BUFFER_SIZE
#endif
#ifndef TX1_BUFFER_SIZE
#define TX1_BUFFER_SIZE TX_BUFFER_SIZE
#endif
#ifndef RX1_BUFFER_SIZE
#define RX1_BUFFER_SIZE RX_BUFFER_SIZE
#endif
#ifndef TX2_BUFFER_SIZE
#define TX2_BUFFER_SIZE TX_BUFFER_SIZE
#endif
#ifndef RX2_BUFFER_SIZE
#define RX2_BUFFER_SIZE RX_BUFFER_SIZE
#endif
#ifndef TX3_BUFFER_SIZE
#define TX3_BUFFER_SIZE TX_BUFFER_SIZE
#endif
#ifndef RX3_BUFFER_SIZE
#define RX3_BUFFER_SIZE RX_BUFFER_SIZE
#endif
#define TX0_BUFFER_MASK (TX0_BUFFER_SIZE - 1)
#define RX0_BUFFER_MASK (RX0_BUFFER_SIZE - 1)
#define TX1_BUFFER_MASK (TX1_BUFFER_SIZE - 1)
#define RX1_BUFFER_MASK (RX1_BUFFER_SIZE - 1)
#define TX2_BUFFER_MASK (TX2_BUFFER_SIZE - 1)
#define RX2_BUFFER_MASK (RX2_BUFFER_SIZE - 1)
#define TX3_BUFFER_MASK (TX3_BUFFER_SIZE - 1)
#define RX3_BUFFER_MASK (RX3_BUFFER_SIZE - 1)
enum {COMPLETED = 1, BUFFER_EMPTY = 0, BUFFER_FULL = 0};
#if defined(URSEL)||defined(URSEL0)||defined(URSEL1)||defined(URSEL2)||defined(URSEL3)
#define USART_XCK_RISING_EDGE 0x80
#define USART_XCK_FALLING_EDGE 0x81
#define USART_5BIT_DATA 0x80
#define USART_6BIT_DATA 0x82
#define USART_7BIT_DATA 0x84
#define USART_8BIT_DATA 0x86
#define USART_1STOP_BIT 0x80
#define USART_2STOP_BITS 0x88
#define USART_NO_PARITY 0x80
#define USART_EVEN_PARITY 0xA0
#define USART_ODD_PARITY 0xB0
#define USART_ASYNC_MODE 0x80
#define USART_SYNC_MODE 0xC0
#else
#define USART_XCK_RISING_EDGE 0x00
#define USART_XCK_FALLING_EDGE 0x01
#define USART_5BIT_DATA 0x00
#define USART_6BIT_DATA 0x02
#define USART_7BIT_DATA 0x04
#define USART_8BIT_DATA 0x06
#define USART_1STOP_BIT 0x00
#define USART_2STOP_BITS 0x08
#define USART_NO_PARITY 0x00
#define USART_EVEN_PARITY 0x20
#define USART_ODD_PARITY 0x30
#define USART_ASYNC_MODE 0x00
#define USART_SYNC_MODE 0x40
#define USART_MSPI_MODE 0xC0
#endif
#define USART_8N1 (USART_8BIT_DATA|USART_NO_PARITY|USART_1STOP_BIT)
#define USART_8N2 (USART_8BIT_DATA|USART_NO_PARITY|USART_2STOP_BITS)
#define USART_8E1 (USART_8BIT_DATA|USART_EVEN_PARITY|USART_1STOP_BIT)
#define USART_8E2 (USART_8BIT_DATA|USART_EVEN_PARITY|USART_2STOP_BITS)
#define USART_8O1 (USART_8BIT_DATA|USART_ODD_PARITY|USART_1STOP_BIT)
#define USART_8O2 (USART_8BIT_DATA|USART_ODD_PARITY|USART_2STOP_BITS)
#define USART_7N1 (USART_7BIT_DATA|USART_NO_PARITY|USART_1STOP_BIT)
#define USART_7N2 (USART_7BIT_DATA|USART_NO_PARITY|USART_2STOP_BITS)
#define USART_7E1 (USART_7BIT_DATA|USART_EVEN_PARITY|USART_1STOP_BIT)
#define USART_7E2 (USART_7BIT_DATA|USART_EVEN_PARITY|USART_2STOP_BITS)
#define USART_7O1 (USART_7BIT_DATA|USART_ODD_PARITY|USART_1STOP_BIT)
#define USART_7O2 (USART_7BIT_DATA|USART_ODD_PARITY|USART_2STOP_BITS)
#ifdef NO_USART_RX // remove all RX interrupts
#define NO_RX0_INTERRUPT
#define NO_RX1_INTERRUPT
#define NO_RX2_INTERRUPT
#define NO_RX3_INTERRUPT
#endif
#ifdef NO_USART_TX // remove all TX interrupts
#define NO_TX0_INTERRUPT
#define NO_TX1_INTERRUPT
#define NO_TX2_INTERRUPT
#define NO_TX3_INTERRUPT
#endif
#ifdef USE_DOUBLE_SPEED
#define USART0_U2X_SPEED
#define USART1_U2X_SPEED
#define USART2_U2X_SPEED
#define USART3_U2X_SPEED
#endif
#ifdef RX_GETC_ECHO
#define RX0_GETC_ECHO
#define RX1_GETC_ECHO
#define RX2_GETC_ECHO
#define RX3_GETC_ECHO
#endif
#ifdef PUTC_CONVERT_LF_TO_CRLF
#define PUTC0_CONVERT_LF_TO_CRLF
#define PUTC1_CONVERT_LF_TO_CRLF
#define PUTC2_CONVERT_LF_TO_CRLF
#define PUTC3_CONVERT_LF_TO_CRLF
#endif
#ifdef USART_EXTEND_RX_BUFFER
#define USART0_EXTEND_RX_BUFFER
#define USART1_EXTEND_RX_BUFFER
#define USART2_EXTEND_RX_BUFFER
#define USART3_EXTEND_RX_BUFFER
#endif
#ifdef USART_PUTC_FAST_INSERTIONS
#define USART0_PUTC_FAST_INSERTIONS
#define USART1_PUTC_FAST_INSERTIONS
#define USART2_PUTC_FAST_INSERTIONS
#define USART3_PUTC_FAST_INSERTIONS
#endif
#ifdef USART_MPCM_MODE
#define USART0_MPCM_MODE
#define USART1_MPCM_MODE
#define USART2_MPCM_MODE
#define USART3_MPCM_MODE
#endif
#if defined(CTS0_DDR)&&defined(CTS0_PORT)&&defined(CTS0_PPIN)&&defined(CTS0_IONUM)
#define USART0_USE_SOFT_CTS
#endif
#if defined(CTS1_DDR)&&defined(CTS1_PORT)&&defined(CTS1_PPIN)&&defined(CTS1_IONUM)
#define USART1_USE_SOFT_CTS
#endif
#if defined(CTS2_DDR)&&defined(CTS2_PORT)&&defined(CTS2_PPIN)&&defined(CTS2_IONUM)
#define USART2_USE_SOFT_CTS
#endif
#if defined(CTS3_DDR)&&defined(CTS3_PORT)&&defined(CTS3_PPIN)&&defined(CTS3_IONUM)
#define USART3_USE_SOFT_CTS
#endif
#if defined(RTS0_DDR)&&defined(RTS0_PORT)&&defined(RTS0_PIN)&&defined(RTS0_IONUM)
#define USART0_USE_SOFT_RTS
#endif
#if defined(RTS1_DDR)&&defined(RTS1_PORT)&&defined(RTS1_PIN)&&defined(RTS1_IONUM)
#define USART1_USE_SOFT_RTS
#endif
#if defined(RTS2_DDR)&&defined(RTS2_PORT)&&defined(RTS2_PIN)&&defined(RTS2_IONUM)
#define USART2_USE_SOFT_RTS
#endif
#if defined(RTS3_DDR)&&defined(RTS3_PORT)&&defined(RTS3_PIN)&&defined(RTS3_IONUM)
#define USART3_USE_SOFT_RTS
#endif
#if defined(RS485_CONTROL0_DDR)&&defined(RS485_CONTROL0_PORT)&&defined(RS485_CONTROL0_PIN)&&defined(RS485_CONTROL0_IONUM)
#define USART0_RS485_MODE
#endif
#if defined(RS485_CONTROL1_DDR)&&defined(RS485_CONTROL1_PORT)&&defined(RS485_CONTROL1_PIN)&&defined(RS485_CONTROL1_IONUM)
#define USART1_RS485_MODE
#endif
#if defined(RS485_CONTROL2_DDR)&&defined(RS485_CONTROL2_PORT)&&defined(RS485_CONTROL2_PIN)&&defined(RS485_CONTROL2_IONUM)
#define USART2_RS485_MODE
#endif
#if defined(RS485_CONTROL3_DDR)&&defined(RS485_CONTROL3_PORT)&&defined(RS485_CONTROL3_PIN)&&defined(RS485_CONTROL3_IONUM)
#define USART3_RS485_MODE
#endif
#ifdef USART0_USE_SOFT_RTS
#ifndef USART0_EXTEND_RX_BUFFER
#define USART0_EXTEND_RX_BUFFER
#endif
#endif
#ifdef USART1_USE_SOFT_RTS
#ifndef USART1_EXTEND_RX_BUFFER
#define USART1_EXTEND_RX_BUFFER
#endif
#endif
#ifdef USART2_USE_SOFT_RTS
#ifndef USART2_EXTEND_RX_BUFFER
#define USART2_EXTEND_RX_BUFFER
#endif
#endif
#ifdef USART3_USE_SOFT_RTS
#ifndef USART3_EXTEND_RX_BUFFER
#define USART3_EXTEND_RX_BUFFER
#endif
#endif
#ifdef RX_NEWLINE_MODE
#if (RX_NEWLINE_MODE == 0)
#define RX_NEWLINE_MODE_R
#elif (RX_NEWLINE_MODE == 1)
#define RX_NEWLINE_MODE_N
#else // RX_NEWLINE_MODE == 2
#define RX_NEWLINE_MODE_RN
#endif
#else
#define RX_NEWLINE_MODE_RN // 2
#endif
#ifdef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
register uint8_t USART_SREG_SAVE_REG_NAME asm(USART_SREG_SAVE_REG_NUM); // have to be defined separately in every compilation unit
#endif
#ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
register uint16_t USART_Z_SAVE_REG_NAME asm(USART_Z_SAVE_REG_NUM); // have to be defined separately in every compilation unit
#endif
#if defined(USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE)&&defined(USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE)
#define USART_REG_SAVE_LIST \
[sreg_save] "+r" (USART_SREG_SAVE_REG_NAME), \
[z_save] "+r" (USART_Z_SAVE_REG_NAME)
#elif defined(USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE)
#define USART_REG_SAVE_LIST \
[z_save] "+r" (USART_Z_SAVE_REG_NAME)
#elif defined(USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE)
#define USART_REG_SAVE_LIST \
[sreg_save] "+r" (USART_SREG_SAVE_REG_NAME)
#else
#define USART_REG_SAVE_LIST
#endif
#if defined(__usbdrv_h_included__)&&!defined(USART_UNSAFE_RX_INTERRUPT)
#warning "usb may not work with uart's RX ISR"
#endif
#if defined(__usbdrv_h_included__)&&!defined(USART_UNSAFE_TX_INTERRUPT)
#warning "usb may not work with uart's TX ISR"
#endif
#if (defined(USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE)||defined(USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE))&&(defined(USART_UNSAFE_TX_INTERRUPT)||defined(USART_UNSAFE_RX_INTERRUPT))
#warning "using globally reserved save registers with interruptable interrupts might create special conditions"
#endif
#if defined(__AVR_ATtiny102__)||defined(__AVR_ATtiny104__)||defined(__AVR_ATtiny2313__)||defined(__AVR_ATtiny2313A__)
#define USART_USE_TINY_MEMORY_MODEL
#endif
#if defined(__AVR_ATtiny102__)||defined(__AVR_ATtiny104__)
#if (TX0_BUFFER_SIZE > 8)||(RX0_BUFFER_SIZE > 8)
#warning "TX or RX buffer may be too large for this mcu"
#endif
#define USART0_IN_UPPER_IO_ADDRESS_SPACE
#ifndef NO_USART0
#define USE_USART0
#define RX0_INTERRUPT USART0_RXC_vect
#define TXC0_INTERRUPT USART0_TXC_vect
#define UDRE0_INTERRUPT USART0_DRE_vect
#define UDR0_REGISTER UDR0
#define UBRR0L_REGISTER UBRR0L
#define UBRR0H_REGISTER UBRR0H
#define UCSR0A_REGISTER UCSR0A
#define UCSR0B_REGISTER UCSR0B
#define UCSR0C_REGISTER UCSR0C
#define TXCIE0_BIT TXCIE0
#define UDRIE0_BIT UDRIE0
#define RXCIE0_BIT RXCIE0
#define TXEN0_BIT TXEN0
#define RXEN0_BIT RXEN0
#define UDRE0_BIT UDRE0
#define RXC0_BIT RXC0
#define U2X0_BIT U2X0
#define MPCM0_BIT MPCM0
#define UCSZ02_BIT UCSZ02
#define TXB80_BIT TXB80
#endif //NO_USART0
#endif
#if defined(__AVR_ATtiny2313__)||defined(__AVR_ATtiny2313A__)||defined(__AVR_ATtiny4313)
#define USART0_IN_IO_ADDRESS_SPACE
#ifndef NO_USART0
#define USE_USART0
#define RX0_INTERRUPT USART_RX_vect
#define TXC0_INTERRUPT USART_TX_vect
#define UDRE0_INTERRUPT USART_UDRE_vect
#define UDR0_REGISTER UDR
#define UBRR0L_REGISTER UBRRL
#define UBRR0H_REGISTER UBRRH
#define UCSR0A_REGISTER UCSRA
#define UCSR0B_REGISTER UCSRB
#define UCSR0C_REGISTER UCSRC
#define TXCIE0_BIT TXCIE
#define UDRIE0_BIT UDRIE
#define RXCIE0_BIT RXCIE
#define TXEN0_BIT TXEN
#define RXEN0_BIT RXEN
#define UDRE0_BIT UDRE
#define RXC0_BIT RXC
#define U2X0_BIT U2X
#define MPCM0_BIT MPCM
#define UCSZ02_BIT UCSZ2
#define TXB80_BIT TXB8
#endif //NO_USART0
#endif
#if defined(__AVR_ATtiny1634__)
#define USART0_IN_UPPER_IO_ADDRESS_SPACE
#ifndef NO_USART0
#define USE_USART0
#define RX0_INTERRUPT USART0_RX_vect
#define TXC0_INTERRUPT USART0_TX_vect
#define UDRE0_INTERRUPT USART0_UDRE_vect
#define UDR0_REGISTER UDR0
#define UBRR0L_REGISTER UBRR0L
#define UBRR0H_REGISTER UBRR0H
#define UCSR0A_REGISTER UCSR0A
#define UCSR0B_REGISTER UCSR0B
#define UCSR0C_REGISTER UCSR0C
#define TXCIE0_BIT TXCIE0
#define UDRIE0_BIT UDRIE0
#define RXCIE0_BIT RXCIE0
#define TXEN0_BIT TXEN0
#define RXEN0_BIT RXEN0
#define UDRE0_BIT UDRE0
#define RXC0_BIT RXC0
#define U2X0_BIT U2X0
#define MPCM0_BIT MPCM0
#define UCSZ02_BIT UCSZ02
#define TXB80_BIT TXB80
#endif //NO_USART0
#ifndef NO_USART1
#define USE_USART1
#define RX1_INTERRUPT USART1_RX_vect
#define TXC1_INTERRUPT USART1_TX_vect
#define UDRE1_INTERRUPT USART1_UDRE_vect
#define UDR1_REGISTER UDR1
#define UBRR1L_REGISTER UBRR1L
#define UBRR1H_REGISTER UBRR1H
#define UCSR1A_REGISTER UCSR1A
#define UCSR1B_REGISTER UCSR1B
#define UCSR1C_REGISTER UCSR1C
#define TXCIE1_BIT TXCIE1
#define UDRIE1_BIT UDRIE1
#define RXCIE1_BIT RXCIE1
#define TXEN1_BIT TXEN1
#define RXEN1_BIT RXEN1
#define UDRE1_BIT UDRE1
#define RXC1_BIT RXC1
#define U2X1_BIT U2X1
#define MPCM1_BIT MPCM1
#define UCSZ12_BIT UCSZ12
#define TXB81_BIT TXB81
#endif //NO_USART1
#endif
#if defined(__AVR_ATtiny441__)||defined(__AVR_ATtiny841__)
#ifndef NO_USART0
#define USE_USART0
#define RX0_INTERRUPT USART0_RX_vect
#define TXC0_INTERRUPT USART0_TX_vect
#define UDRE0_INTERRUPT USART0_UDRE_vect
#define UDR0_REGISTER UDR0
#define UBRR0L_REGISTER UBRR0L
#define UBRR0H_REGISTER UBRR0H
#define UCSR0A_REGISTER UCSR0A
#define UCSR0B_REGISTER UCSR0B
#define UCSR0C_REGISTER UCSR0C
#define TXCIE0_BIT TXCIE0
#define UDRIE0_BIT UDRIE0
#define RXCIE0_BIT RXCIE0
#define TXEN0_BIT TXEN0
#define RXEN0_BIT RXEN0
#define UDRE0_BIT UDRE0
#define RXC0_BIT RXC0
#define U2X0_BIT U2X0
#define MPCM0_BIT MPCM0
#define UCSZ02_BIT UCSZ02
#define TXB80_BIT TXB80
#endif //NO_USART0
#ifndef NO_USART1
#define USE_USART1
#define RX1_INTERRUPT USART1_RX_vect
#define TXC1_INTERRUPT USART1_TX_vect
#define UDRE1_INTERRUPT USART1_UDRE_vect
#define UDR1_REGISTER UDR1
#define UBRR1L_REGISTER UBRR1L
#define UBRR1H_REGISTER UBRR1H
#define UCSR1A_REGISTER UCSR1A
#define UCSR1B_REGISTER UCSR1B
#define UCSR1C_REGISTER UCSR1C
#define TXCIE1_BIT TXCIE1
#define UDRIE1_BIT UDRIE1
#define RXCIE1_BIT RXCIE1
#define TXEN1_BIT TXEN1
#define RXEN1_BIT RXEN1
#define UDRE1_BIT UDRE1
#define RXC1_BIT RXC1
#define U2X1_BIT U2X1
#define MPCM1_BIT MPCM1
#define UCSZ12_BIT UCSZ12
#define TXB81_BIT TXB81
#endif //NO_USART1
#endif
#if defined(__AVR_ATmega48__)||defined(__AVR_ATmega48P__)||defined(__AVR_ATmega48PA__)||defined(__AVR_ATmega48PB__)\
||defined(__AVR_ATmega88__)||defined(__AVR_ATmega88P__)||defined(__AVR_ATmega88PA__)||defined(__AVR_ATmega88PB__)\
||defined(__AVR_ATmega168__)||defined(__AVR_ATmega168P__)||defined(__AVR_ATmega168PA__)||defined(__AVR_ATmega168PB__)\
||defined(__AVR_ATmega328__)||defined(__AVR_ATmega328P__)
#ifndef NO_USART0
#define USE_USART0
#define RX0_INTERRUPT USART_RX_vect
#define TXC0_INTERRUPT USART_TX_vect
#define UDRE0_INTERRUPT USART_UDRE_vect
#define UDR0_REGISTER UDR0
#define UBRR0L_REGISTER UBRR0L
#define UBRR0H_REGISTER UBRR0H
#define UCSR0A_REGISTER UCSR0A
#define UCSR0B_REGISTER UCSR0B
#define UCSR0C_REGISTER UCSR0C
#define TXCIE0_BIT TXCIE0
#define UDRIE0_BIT UDRIE0
#define RXCIE0_BIT RXCIE0
#define TXEN0_BIT TXEN0
#define RXEN0_BIT RXEN0
#define UDRE0_BIT UDRE0
#define RXC0_BIT RXC0
#define U2X0_BIT U2X0
#define MPCM0_BIT MPCM0
#define UCSZ02_BIT UCSZ02
#define TXB80_BIT TXB80
#endif //NO_USART0
#endif
#if defined(__AVR_ATmega328PB__)
#ifndef NO_USART0
#define USE_USART0
#define RX0_INTERRUPT USART0_RX_vect
#define TXC0_INTERRUPT USART0_TX_vect
#define UDRE0_INTERRUPT USART0_UDRE_vect
#define UDR0_REGISTER UDR0
#define UBRR0L_REGISTER UBRR0L
#define UBRR0H_REGISTER UBRR0H
#define UCSR0A_REGISTER UCSR0A
#define UCSR0B_REGISTER UCSR0B
#define UCSR0C_REGISTER UCSR0C
#define TXCIE0_BIT TXCIE0
#define UDRIE0_BIT UDRIE0
#define RXCIE0_BIT RXCIE0
#define TXEN0_BIT TXEN0
#define RXEN0_BIT RXEN0
#define UDRE0_BIT UDRE0
#define RXC0_BIT RXC0
#define U2X0_BIT U2X0
#define MPCM0_BIT MPCM0
#define UCSZ02_BIT UCSZ02
#define TXB80_BIT TXB80
#endif //NO_USART0
#ifndef NO_USART1
#define USE_USART1
#define RX1_INTERRUPT USART1_RX_vect
#define TXC1_INTERRUPT USART1_TX_vect
#define UDRE1_INTERRUPT USART1_UDRE_vect
#define UDR1_REGISTER UDR1
#define UBRR1L_REGISTER UBRR1L
#define UBRR1H_REGISTER UBRR1H
#define UCSR1A_REGISTER UCSR1A
#define UCSR1B_REGISTER UCSR1B
#define UCSR1C_REGISTER UCSR1C
#define TXCIE1_BIT TXCIE1
#define UDRIE1_BIT UDRIE1
#define RXCIE1_BIT RXCIE1
#define TXEN1_BIT TXEN1
#define RXEN1_BIT RXEN1
#define UDRE1_BIT UDRE1
#define RXC1_BIT RXC1
#define U2X1_BIT U2X1
#define MPCM1_BIT MPCM1
#define UCSZ12_BIT UCSZ12
#define TXB81_BIT TXB81
#endif //NO_USART1
#endif
#if defined(__AVR_ATmega8__)||defined(__AVR_ATmega8P__)||defined(__AVR_ATmega16__)\
||defined(__AVR_ATmega16A__)||defined(__AVR_ATmega32__)||defined(__AVR_ATmega32A__)\
||defined(__AVR_ATmega8A__)||defined(__AVR_ATmega8L__)
#define USART0_IN_IO_ADDRESS_SPACE
#ifndef NO_USART0
#define USE_USART0
#define RX0_INTERRUPT USART_RXC_vect
#define TXC0_INTERRUPT USART_TXC_vect
#define UDRE0_INTERRUPT USART_UDRE_vect
#define UDR0_REGISTER UDR
#define UBRR0L_REGISTER UBRRL
#define UBRR0H_REGISTER UBRRH
#define UCSR0A_REGISTER UCSRA
#define UCSR0B_REGISTER UCSRB
#define UCSR0C_REGISTER UCSRC
#define TXCIE0_BIT TXCIE
#define UDRIE0_BIT UDRIE
#define RXCIE0_BIT RXCIE
#define TXEN0_BIT TXEN
#define RXEN0_BIT RXEN
#define UDRE0_BIT UDRE
#define RXC0_BIT RXC
#define U2X0_BIT U2X
#define MPCM0_BIT MPCM
#define UCSZ02_BIT UCSZ2
#define TXB80_BIT TXB8
#endif //NO_USART0
#endif
#if defined(__AVR_ATmega8515__)||defined(__AVR_ATmega8515L__)
#define USART0_IN_IO_ADDRESS_SPACE
#ifndef NO_USART0
#define USE_USART0
#define RX0_INTERRUPT USART_RX_vect
#define TXC0_INTERRUPT USART_TX_vect
#define UDRE0_INTERRUPT USART_UDRE_vect
#define UDR0_REGISTER UDR
#define UBRR0L_REGISTER UBRRL
#define UBRR0H_REGISTER UBRRH
#define UCSR0A_REGISTER UCSRA
#define UCSR0B_REGISTER UCSRB
#define UCSR0C_REGISTER UCSRC
#define TXCIE0_BIT TXCIE
#define UDRIE0_BIT UDRIE
#define RXCIE0_BIT RXCIE
#define TXEN0_BIT TXEN
#define RXEN0_BIT RXEN
#define UDRE0_BIT UDRE
#define RXC0_BIT RXC
#define U2X0_BIT U2X
#define MPCM0_BIT MPCM
#define UCSZ02_BIT UCSZ2
#define TXB80_BIT TXB8
#endif //NO_USART0
#endif
#if defined(__AVR_ATmega162__)
#define USART0_IN_IO_ADDRESS_SPACE
#define USART1_IN_IO_ADDRESS_SPACE
#ifndef NO_USART0
#define USE_USART0
#define RX0_INTERRUPT USART0_RXC_vect
#define TXC0_INTERRUPT USART0_TXC_vect
#define UDRE0_INTERRUPT USART0_UDRE_vect
#define UDR0_REGISTER UDR0
#define UBRR0L_REGISTER UBRR0L
#define UBRR0H_REGISTER UBRR0H
#define UCSR0A_REGISTER UCSR0A
#define UCSR0B_REGISTER UCSR0B
#define UCSR0C_REGISTER UCSR0C
#define TXCIE0_BIT TXCIE0
#define UDRIE0_BIT UDRIE0
#define RXCIE0_BIT RXCIE0
#define TXEN0_BIT TXEN0
#define RXEN0_BIT RXEN0
#define UDRE0_BIT UDRE0
#define RXC0_BIT RXC0
#define U2X0_BIT U2X0
#define MPCM0_BIT MPCM0
#define UCSZ02_BIT UCSZ02
#define TXB80_BIT TXB80
#endif //NO_USART0
#ifndef NO_USART1
#define USE_USART1
#define RX1_INTERRUPT USART1_RXC_vect
#define TXC1_INTERRUPT USART1_TXC_vect
#define UDRE1_INTERRUPT USART1_UDRE_vect
#define UDR1_REGISTER UDR1
#define UBRR1L_REGISTER UBRR1L
#define UBRR1H_REGISTER UBRR1H
#define UCSR1A_REGISTER UCSR1A
#define UCSR1B_REGISTER UCSR1B
#define UCSR1C_REGISTER UCSR1C
#define TXCIE1_BIT TXCIE1
#define UDRIE1_BIT UDRIE1
#define RXCIE1_BIT RXCIE1
#define TXEN1_BIT TXEN1
#define RXEN1_BIT RXEN1
#define UDRE1_BIT UDRE1
#define RXC1_BIT RXC1
#define U2X1_BIT U2X1
#define MPCM1_BIT MPCM1
#define UCSZ12_BIT UCSZ12
#define TXB81_BIT TXB81
#endif //NO_USART1
#endif
#if defined(__AVR_ATmega128__)||defined(__AVR_ATmega128A__)||defined(__AVR_ATmega64__)\
||defined(__AVR_ATmega64A__)
#define USART0_IN_IO_ADDRESS_SPACE
#endif
#if defined(__AVR_ATmega644__)||defined(__AVR_ATmega644P__)||defined(__AVR_ATmega644PA__)\
||defined(__AVR_ATmega1284__)||defined(__AVR_ATmega1284P__)||defined(__AVR_ATmega128__)\
||defined(__AVR_ATmega128A__)||defined(__AVR_ATmega64__)||defined(__AVR_ATmega64A__)\
||defined(__AVR_ATmega1281__)||defined(__AVR_ATmega2561__)||defined(__AVR_ATmega640__)\
||defined(__AVR_ATmega1280__)||defined(__AVR_ATmega2560__)||defined(__AVR_ATmega164P__)\
||defined(__AVR_ATmega324P__)||defined(__AVR_ATmega324A__)||defined(__AVR_ATmega324PA__)\
||defined(__AVR_ATmega324PB__)
#ifndef NO_USART0
#define USE_USART0
#define RX0_INTERRUPT USART0_RX_vect
#define TXC0_INTERRUPT USART0_TX_vect
#define UDRE0_INTERRUPT USART0_UDRE_vect
#define UDR0_REGISTER UDR0
#define UBRR0L_REGISTER UBRR0L
#define UBRR0H_REGISTER UBRR0H
#define UCSR0A_REGISTER UCSR0A
#define UCSR0B_REGISTER UCSR0B
#define UCSR0C_REGISTER UCSR0C
#define TXCIE0_BIT TXCIE0
#define UDRIE0_BIT UDRIE0
#define RXCIE0_BIT RXCIE0
#define TXEN0_BIT TXEN0
#define RXEN0_BIT RXEN0
#define UDRE0_BIT UDRE0
#define RXC0_BIT RXC0
#define U2X0_BIT U2X0
#define MPCM0_BIT MPCM0
#define UCSZ02_BIT UCSZ02
#define TXB80_BIT TXB80
#endif
#if !defined(NO_USART1) && !defined(__AVR_ATmega644__)
#define USE_USART1
#define RX1_INTERRUPT USART1_RX_vect
#define TXC1_INTERRUPT USART1_TX_vect
#define UDRE1_INTERRUPT USART1_UDRE_vect
#define UDR1_REGISTER UDR1
#define UBRR1L_REGISTER UBRR1L
#define UBRR1H_REGISTER UBRR1H
#define UCSR1A_REGISTER UCSR1A
#define UCSR1B_REGISTER UCSR1B
#define UCSR1C_REGISTER UCSR1C
#define TXCIE1_BIT TXCIE1
#define UDRIE1_BIT UDRIE1
#define RXCIE1_BIT RXCIE1
#define TXEN1_BIT TXEN1
#define RXEN1_BIT RXEN1
#define UDRE1_BIT UDRE1
#define RXC1_BIT RXC1
#define U2X1_BIT U2X1
#define MPCM1_BIT MPCM1
#define UCSZ12_BIT UCSZ12
#define TXB81_BIT TXB81
#endif // NO_USART1 && 644
#endif
#if defined(__AVR_ATmega640__)||defined(__AVR_ATmega1280__)||defined(__AVR_ATmega2560__)||defined(__AVR_ATmega324PB__)
#ifndef NO_USART2
#define USE_USART2
#define RX2_INTERRUPT USART2_RX_vect
#define TXC2_INTERRUPT USART2_TX_vect
#define UDRE2_INTERRUPT USART2_UDRE_vect
#define UDR2_REGISTER UDR2
#define UBRR2L_REGISTER UBRR2L
#define UBRR2H_REGISTER UBRR2H
#define UCSR2A_REGISTER UCSR2A
#define UCSR2B_REGISTER UCSR2B
#define UCSR2C_REGISTER UCSR2C
#define TXCIE2_BIT TXCIE2
#define UDRIE2_BIT UDRIE2
#define RXCIE2_BIT RXCIE2
#define TXEN2_BIT TXEN2
#define RXEN2_BIT RXEN2
#define UDRE2_BIT UDRE2
#define RXC2_BIT RXC2
#define U2X2_BIT U2X2
#define MPCM2_BIT MPCM2
#define UCSZ22_BIT UCSZ22
#define TXB82_BIT TXB82
#endif // NO_USART2
#if !defined(NO_USART3)&&!defined(__AVR_ATmega324PB__)
#define USE_USART3
#define RX3_INTERRUPT USART3_RX_vect
#define TXC3_INTERRUPT USART3_TX_vect
#define UDRE3_INTERRUPT USART3_UDRE_vect
#define UDR3_REGISTER UDR3
#define UBRR3L_REGISTER UBRR3L
#define UBRR3H_REGISTER UBRR3H
#define UCSR3A_REGISTER UCSR3A
#define UCSR3B_REGISTER UCSR3B
#define UCSR3C_REGISTER UCSR3C
#define TXCIE3_BIT TXCIE3
#define UDRIE3_BIT UDRIE3
#define RXCIE3_BIT RXCIE3
#define TXEN3_BIT TXEN3
#define RXEN3_BIT RXEN3
#define UDRE3_BIT UDRE3
#define RXC3_BIT RXC3
#define U2X3_BIT U2X3
#define MPCM3_BIT MPCM3
#define UCSZ32_BIT UCSZ32
#define TXB83_BIT TXB83
#endif // NO_USART3
#endif // 640/1280/2560 usart 2 & 3
#if defined(__AVR_ATmega8U2__) || defined(__AVR_ATmega16U2__) || defined(__AVR_ATmega16U4__)\
||defined(__AVR_ATmega32U2__) || defined(__AVR_ATmega32U4__) || defined(__AVR_ATmega32U6__)\
||defined(__AVR_AT90USB82__)||defined(__AVR_AT90USB162__)
#define USART1_HARDWARE_FLOW_CONTROL_AVAILABLE
#ifndef NO_USART1 // we will call the only usart, as an usart0
#define USE_USART1
#define RX1_INTERRUPT USART1_RX_vect
#define TXC1_INTERRUPT USART1_TX_vect
#define UDRE1_INTERRUPT USART1_UDRE_vect
#define UDR1_REGISTER UDR1
#define UBRR1L_REGISTER UBRR1L
#define UBRR1H_REGISTER UBRR1H
#define UCSR1A_REGISTER UCSR1A
#define UCSR1B_REGISTER UCSR1B
#define UCSR1C_REGISTER UCSR1C
#define UCSR1D_REGISTER UCSR1D
#define TXCIE1_BIT TXCIE1
#define UDRIE1_BIT UDRIE1
#define RXCIE1_BIT RXCIE1
#define TXEN1_BIT TXEN1
#define RXEN1_BIT RXEN1
#define UDRE1_BIT UDRE1
#define RXC1_BIT RXC1
#define U2X1_BIT U2X1
#define MPCM1_BIT MPCM1
#define UCSZ12_BIT UCSZ12
#define TXB81_BIT TXB81
#define CTSEN1_BIT CTSEN
#define RTSEN1_BIT RTSEN
#endif // NO_USART1
#endif
#if defined(__AVR_ATmega169A__)||defined(__AVR_ATmega169__)||defined(__AVR_ATmega169P__)||defined(__AVR_ATmega169PA__)
#ifndef NO_USART0
#define USE_USART0
#define RX0_INTERRUPT USART0_RX_vect
#define TXC0_INTERRUPT USART0_TX_vect
#define UDRE0_INTERRUPT USART0_UDRE_vect
#define UDR0_REGISTER UDR
#define UBRR0L_REGISTER UBRRL
#define UBRR0H_REGISTER UBRRH
#define UCSR0A_REGISTER UCSRA
#define UCSR0B_REGISTER UCSRB
#define UCSR0C_REGISTER UCSRC
#define TXCIE0_BIT TXCIE
#define UDRIE0_BIT UDRIE
#define RXCIE0_BIT RXCIE
#define TXEN0_BIT TXEN
#define RXEN0_BIT RXEN
#define UDRE0_BIT UDRE
#define RXC0_BIT RXC
#define U2X0_BIT U2X
#define MPCM0_BIT MPCM
#define UCSZ02_BIT UCSZ2
#define TXB80_BIT TXB8
#endif //NO_USART0
#endif
#if defined(__AVR_ATmega329__)||defined(__AVR_ATmega329P__)||defined(__AVR_ATmega329PA__)\
||defined(__AVR_ATmega329A__)||defined(__AVR_ATmega649__)||defined(__AVR_ATmega649A__)\
||defined(__AVR_ATmega649P__)||defined(__AVR_ATmega169P__)||defined(__AVR_ATmega169PA__)\
||defined(__AVR_ATmega325__)||defined(__AVR_ATmega325A__)||defined(__AVR_ATmega325P__)\
||defined(__AVR_ATmega325PA__)||defined(__AVR_ATmega645__)||defined(__AVR_ATmega645A__)\
||defined(__AVR_ATmega645P__)
#ifndef NO_USART0
#define USE_USART0
#define RX0_INTERRUPT USART0_RX_vect
#define TXC0_INTERRUPT USART0_TX_vect
#define UDRE0_INTERRUPT USART0_UDRE_vect
#define UDR0_REGISTER UDR0
#define UBRR0L_REGISTER UBRR0L
#define UBRR0H_REGISTER UBRR0H
#define UCSR0A_REGISTER UCSR0A
#define UCSR0B_REGISTER UCSR0B
#define UCSR0C_REGISTER UCSR0C
#define TXCIE0_BIT TXCIE0
#define UDRIE0_BIT UDRIE0
#define RXCIE0_BIT RXCIE0
#define TXEN0_BIT TXEN0
#define RXEN0_BIT RXEN0
#define UDRE0_BIT UDRE0
#define RXC0_BIT RXC0
#define U2X0_BIT U2X0
#define MPCM0_BIT MPCM0
#define UCSZ02_BIT UCSZ02
#define TXB80_BIT TXB80
#endif //NO_USART0
#endif
#if defined(__AVR_ATmega3290__)||defined(__AVR_ATmega6490__)||defined(__AVR_ATmega3290P__)\
||defined(__AVR_ATmega3290PA__)||defined(__AVR_ATmega3290A__)||defined(__AVR_ATmega6490A__)\
||defined(__AVR_ATmega6490P__)||defined(__AVR_ATmega3250__)||defined(__AVR_ATmega3250A__)\
||defined(__AVR_ATmega3250P__)||defined(__AVR_ATmega3250PA__)||defined(__AVR_ATmega6450__)\
||defined(__AVR_ATmega6450A__)||defined(__AVR_ATmega6450P__)
#ifndef NO_USART0
#define USE_USART0
#define RX0_INTERRUPT USART_RX_vect // wtf
#define TXC0_INTERRUPT USART0_TX_vect
#define UDRE0_INTERRUPT USART0_UDRE_vect
#define UDR0_REGISTER UDR0
#define UBRR0L_REGISTER UBRR0L
#define UBRR0H_REGISTER UBRR0H
#define UCSR0A_REGISTER UCSR0A
#define UCSR0B_REGISTER UCSR0B
#define UCSR0C_REGISTER UCSR0C
#define TXCIE0_BIT TXCIE0
#define UDRIE0_BIT UDRIE0
#define RXCIE0_BIT RXCIE0
#define TXEN0_BIT TXEN0
#define RXEN0_BIT RXEN0
#define UDRE0_BIT UDRE0
#define RXC0_BIT RXC0
#define U2X0_BIT U2X0
#define MPCM0_BIT MPCM0
#define UCSZ02_BIT UCSZ02
#define TXB80_BIT TXB80
#endif //NO_USART0
#endif
#if defined(__AVR_AT90CAN32__)||defined(__AVR_AT90CAN64__)||defined(__AVR_AT90CAN128__)\
||defined(__AVR_ATmega64RFR2__)||defined(__AVR_ATmega128RFR2__)||defined(__AVR_ATmega256RFR2__)\
||defined(__AVR_ATmega644RFR2__)||defined(__AVR_ATmega1284RFR2__)||defined(__AVR_ATmega2564RFR2__)\
||defined(__AVR_ATmega128RFA1__)
#ifndef NO_USART0
#define USE_USART0
#define RX0_INTERRUPT USART0_RX_vect
#define TXC0_INTERRUPT USART0_TX_vect
#define UDRE0_INTERRUPT USART0_UDRE_vect
#define UDR0_REGISTER UDR0
#define UBRR0L_REGISTER UBRR0L
#define UBRR0H_REGISTER UBRR0H
#define UCSR0A_REGISTER UCSR0A
#define UCSR0B_REGISTER UCSR0B
#define UCSR0C_REGISTER UCSR0C
#define TXCIE0_BIT TXCIE0
#define UDRIE0_BIT UDRIE0
#define RXCIE0_BIT RXCIE0
#define TXEN0_BIT TXEN0
#define RXEN0_BIT RXEN0
#define UDRE0_BIT UDRE0
#define RXC0_BIT RXC0
#define U2X0_BIT U2X0
#define MPCM0_BIT MPCM0
#define UCSZ02_BIT UCSZ02
#define TXB80_BIT TXB80
#endif // NO_USART0
#ifndef NO_USART1
#define USE_USART1
#define RX1_INTERRUPT USART1_RX_vect
#define TXC1_INTERRUPT USART1_TX_vect
#define UDRE1_INTERRUPT USART1_UDRE_vect
#define UDR1_REGISTER UDR1
#define UBRR1L_REGISTER UBRR1L
#define UBRR1H_REGISTER UBRR1H
#define UCSR1A_REGISTER UCSR1A
#define UCSR1B_REGISTER UCSR1B
#define UCSR1C_REGISTER UCSR1C
#define TXCIE1_BIT TXCIE1
#define UDRIE1_BIT UDRIE1
#define RXCIE1_BIT RXCIE1
#define TXEN1_BIT TXEN1
#define RXEN1_BIT RXEN1
#define UDRE1_BIT UDRE1
#define RXC1_BIT RXC1
#define U2X1_BIT U2X1
#define MPCM1_BIT MPCM1
#define UCSZ12_BIT UCSZ12
#define TXB81_BIT TXB81