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arm-gen.c
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arm-gen.c
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/*
* ARMv4 code generator for TCC
*
* Copyright (c) 2003 Daniel Glöckner
* Copyright (c) 2012 Thomas Preud'homme
*
* Based on i386-gen.c by Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifdef TARGET_DEFS_ONLY
#if defined(TCC_ARM_EABI) && !defined(TCC_ARM_VFP)
#error "Currently TinyCC only supports float computation with VFP instructions"
#endif
/* number of available registers */
#ifdef TCC_ARM_VFP
#define NB_REGS 13
#else
#define NB_REGS 9
#endif
#ifndef TCC_CPU_VERSION
# define TCC_CPU_VERSION 5
#endif
/* a register can belong to several classes. The classes must be
sorted from more general to more precise (see gv2() code which does
assumptions on it). */
#define RC_INT 0x0001 /* generic integer register */
#define RC_FLOAT 0x0002 /* generic float register */
#define RC_R0 0x0004
#define RC_R1 0x0008
#define RC_R2 0x0010
#define RC_R3 0x0020
#define RC_R12 0x0040
#define RC_F0 0x0080
#define RC_F1 0x0100
#define RC_F2 0x0200
#define RC_F3 0x0400
#ifdef TCC_ARM_VFP
#define RC_F4 0x0800
#define RC_F5 0x1000
#define RC_F6 0x2000
#define RC_F7 0x4000
#endif
#define RC_IRET RC_R0 /* function return: integer register */
#define RC_IRE2 RC_R1 /* function return: second integer register */
#define RC_FRET RC_F0 /* function return: float register */
/* pretty names for the registers */
enum {
TREG_R0 = 0,
TREG_R1,
TREG_R2,
TREG_R3,
TREG_R12,
TREG_F0,
TREG_F1,
TREG_F2,
TREG_F3,
#ifdef TCC_ARM_VFP
TREG_F4,
TREG_F5,
TREG_F6,
TREG_F7,
#endif
TREG_SP = 13,
TREG_LR,
};
#ifdef TCC_ARM_VFP
#define T2CPR(t) (((t) & VT_BTYPE) != VT_FLOAT ? 0x100 : 0)
#endif
/* return registers for function */
#define REG_IRET TREG_R0 /* single word int return register */
#define REG_IRE2 TREG_R1 /* second word return register (for long long) */
#define REG_FRET TREG_F0 /* float return register */
#ifdef TCC_ARM_EABI
#define TOK___divdi3 TOK___aeabi_ldivmod
#define TOK___moddi3 TOK___aeabi_ldivmod
#define TOK___udivdi3 TOK___aeabi_uldivmod
#define TOK___umoddi3 TOK___aeabi_uldivmod
#endif
/* defined if function parameters must be evaluated in reverse order */
#define INVERT_FUNC_PARAMS
/* defined if structures are passed as pointers. Otherwise structures
are directly pushed on stack. */
/* #define FUNC_STRUCT_PARAM_AS_PTR */
/* pointer size, in bytes */
#define PTR_SIZE 4
/* long double size and alignment, in bytes */
#ifdef TCC_ARM_VFP
#define LDOUBLE_SIZE 8
#endif
#ifndef LDOUBLE_SIZE
#define LDOUBLE_SIZE 8
#endif
#ifdef TCC_ARM_EABI
#define LDOUBLE_ALIGN 8
#else
#define LDOUBLE_ALIGN 4
#endif
/* maximum alignment (for aligned attribute support) */
#define MAX_ALIGN 8
#define CHAR_IS_UNSIGNED
#ifdef TCC_ARM_HARDFLOAT
# define ARM_FLOAT_ABI ARM_HARD_FLOAT
#else
# define ARM_FLOAT_ABI ARM_SOFTFP_FLOAT
#endif
/******************************************************/
#else /* ! TARGET_DEFS_ONLY */
/******************************************************/
#define USING_GLOBALS
#include "tcc.h"
ST_DATA const char * const target_machine_defs =
"__arm__\0"
"__arm\0"
"arm\0"
"__arm_elf__\0"
"__arm_elf\0"
"arm_elf\0"
"__ARM_ARCH_4__\0"
"__ARMEL__\0"
"__APCS_32__\0"
#if defined TCC_ARM_EABI
"__ARM_EABI__\0"
#endif
;
ST_DATA const int reg_classes[NB_REGS] = {
/* r0 */ RC_INT | RC_R0,
/* r1 */ RC_INT | RC_R1,
/* r2 */ RC_INT | RC_R2,
/* r3 */ RC_INT | RC_R3,
/* r12 */ RC_INT | RC_R12,
/* f0 */ RC_FLOAT | RC_F0,
/* f1 */ RC_FLOAT | RC_F1,
/* f2 */ RC_FLOAT | RC_F2,
/* f3 */ RC_FLOAT | RC_F3,
#ifdef TCC_ARM_VFP
/* d4/s8 */ RC_FLOAT | RC_F4,
/* d5/s10 */ RC_FLOAT | RC_F5,
/* d6/s12 */ RC_FLOAT | RC_F6,
/* d7/s14 */ RC_FLOAT | RC_F7,
#endif
};
#if defined(TCC_ARM_EABI) && defined(TCC_ARM_VFP)
ST_FUNC void arm_init(TCCState *S)
{
S->armgen_float_type.t = VT_FLOAT;
S->armgen_double_type.t = VT_DOUBLE;
S->armgen_func_float_type.t = VT_FUNC;
S->armgen_func_float_type.ref = sym_push(S, SYM_FIELD, &S->armgen_float_type, FUNC_CDECL, FUNC_OLD);
S->armgen_func_double_type.t = VT_FUNC;
S->armgen_func_double_type.ref = sym_push(S, SYM_FIELD, &S->armgen_double_type, FUNC_CDECL, FUNC_OLD);
S->float_abi = S->float_abi;
#ifndef TCC_ARM_HARDFLOAT
// XXX: Works on OpenBSD
// # warning "soft float ABI currently not supported: default to softfp"
#endif
}
#else
#define func_float_type func_old_type
#define func_double_type func_old_type
#define func_ldouble_type func_old_type
ST_FUNC void arm_init(struct TCCState *s)
{
#if 0
#if !defined (TCC_ARM_VFP)
tcc_warning("Support for FPA is deprecated and will be removed in next"
" release");
#endif
#if !defined (TCC_ARM_EABI)
tcc_warning("Support for OABI is deprecated and will be removed in next"
" release");
#endif
#endif
}
#endif
#define CHECK_R(r) ((r) >= TREG_R0 && (r) <= TREG_LR)
static int two2mask(TCCState *S, int a,int b) {
if (!CHECK_R(a) || !CHECK_R(b))
tcc_error(S, "compiler error! registers %i,%i is not valid",a,b);
return (reg_classes[a]|reg_classes[b])&~(RC_INT|RC_FLOAT);
}
static int regmask(TCCState *S, int r) {
if (!CHECK_R(r))
tcc_error(S, "compiler error! register %i is not valid",r);
return reg_classes[r]&~(RC_INT|RC_FLOAT);
}
/******************************************************/
#if defined(TCC_ARM_EABI) && !defined(CONFIG_TCC_ELFINTERP)
const char *default_elfinterp(struct TCCState *s)
{
if (s->float_abi == ARM_HARD_FLOAT)
return "/lib/ld-linux-armhf.so.3";
else
return "/lib/ld-linux.so.3";
}
#endif
void o(TCCState *S, uint32_t i)
{
/* this is a good place to start adding big-endian support*/
int ind1;
if (S->nocode_wanted)
return;
ind1 = S->ind + 4;
if (!cur_text_section)
tcc_error(S, "compiler error! This happens f.ex. if the compiler\n"
"can't evaluate constant expressions outside of a function.");
if (ind1 > cur_text_section->data_allocated)
section_realloc(S, cur_text_section, ind1);
cur_text_section->data[S->ind++] = i&255;
i>>=8;
cur_text_section->data[S->ind++] = i&255;
i>>=8;
cur_text_section->data[S->ind++] = i&255;
i>>=8;
cur_text_section->data[S->ind++] = i;
}
static uint32_t stuff_const(uint32_t op, uint32_t c)
{
int try_neg=0;
uint32_t nc = 0, negop = 0;
switch(op&0x1F00000)
{
case 0x800000: //add
case 0x400000: //sub
try_neg=1;
negop=op^0xC00000;
nc=-c;
break;
case 0x1A00000: //mov
case 0x1E00000: //mvn
try_neg=1;
negop=op^0x400000;
nc=~c;
break;
case 0x200000: //xor
if(c==~0)
return (op&0xF010F000)|((op>>16)&0xF)|0x1E00000;
break;
case 0x0: //and
if(c==~0)
return (op&0xF010F000)|((op>>16)&0xF)|0x1A00000;
case 0x1C00000: //bic
try_neg=1;
negop=op^0x1C00000;
nc=~c;
break;
case 0x1800000: //orr
if(c==~0)
return (op&0xFFF0FFFF)|0x1E00000;
break;
}
do {
uint32_t m;
int i;
if(c<256) /* catch undefined <<32 */
return op|c;
for(i=2;i<32;i+=2) {
m=(0xff>>i)|(0xff<<(32-i));
if(!(c&~m))
return op|(i<<7)|(c<<i)|(c>>(32-i));
}
op=negop;
c=nc;
} while(try_neg--);
return 0;
}
//only add,sub
void stuff_const_harder(TCCState *S, uint32_t op, uint32_t v) {
uint32_t x;
x=stuff_const(op,v);
if(x)
o(S, x);
else {
uint32_t a[16], nv, no, o2, n2;
int i,j,k;
a[0]=0xff;
o2=(op&0xfff0ffff)|((op&0xf000)<<4);;
for(i=1;i<16;i++)
a[i]=(a[i-1]>>2)|(a[i-1]<<30);
for(i=0;i<12;i++)
for(j=i<4?i+12:15;j>=i+4;j--)
if((v&(a[i]|a[j]))==v) {
o(S, stuff_const(op,v&a[i]));
o(S, stuff_const(o2,v&a[j]));
return;
}
no=op^0xC00000;
n2=o2^0xC00000;
nv=-v;
for(i=0;i<12;i++)
for(j=i<4?i+12:15;j>=i+4;j--)
if((nv&(a[i]|a[j]))==nv) {
o(S, stuff_const(no,nv&a[i]));
o(S, stuff_const(n2,nv&a[j]));
return;
}
for(i=0;i<8;i++)
for(j=i+4;j<12;j++)
for(k=i<4?i+12:15;k>=j+4;k--)
if((v&(a[i]|a[j]|a[k]))==v) {
o(S, stuff_const(op,v&a[i]));
o(S, stuff_const(o2,v&a[j]));
o(S, stuff_const(o2,v&a[k]));
return;
}
no=op^0xC00000;
nv=-v;
for(i=0;i<8;i++)
for(j=i+4;j<12;j++)
for(k=i<4?i+12:15;k>=j+4;k--)
if((nv&(a[i]|a[j]|a[k]))==nv) {
o(S, stuff_const(no,nv&a[i]));
o(S, stuff_const(n2,nv&a[j]));
o(S, stuff_const(n2,nv&a[k]));
return;
}
o(S, stuff_const(op,v&a[0]));
o(S, stuff_const(o2,v&a[4]));
o(S, stuff_const(o2,v&a[8]));
o(S, stuff_const(o2,v&a[12]));
}
}
uint32_t encbranch(TCCState *S, int pos, int addr, int fail)
{
addr-=pos+8;
addr/=4;
if(addr>=0x1000000 || addr<-0x1000000) {
if(fail)
tcc_error(S, "FIXME: function bigger than 32MB");
return 0;
}
return 0x0A000000|(addr&0xffffff);
}
int decbranch(TCCState *S, int pos)
{
int x;
x=*(uint32_t *)(cur_text_section->data + pos);
x&=0x00ffffff;
if(x&0x800000)
x-=0x1000000;
return x*4+pos+8;
}
/* output a symbol and patch all calls to it */
void gsym_addr(TCCState *S, int t, int a)
{
uint32_t *x;
int lt;
while(t) {
x=(uint32_t *)(cur_text_section->data + t);
t=decbranch(S, lt=t);
if(a==lt+4)
*x=0xE1A00000; // nop
else {
*x &= 0xff000000;
*x |= encbranch(S, lt,a,1);
}
}
}
#ifdef TCC_ARM_VFP
static uint32_t vfpr(TCCState *S, int r)
{
if(r<TREG_F0 || r>TREG_F7)
tcc_error(S, "compiler error! register %i is no vfp register",r);
return r - TREG_F0;
}
#else
static uint32_t fpr(TCCState *S, int r)
{
if(r<TREG_F0 || r>TREG_F3)
tcc_error(S, "compiler error! register %i is no fpa register",r);
return r - TREG_F0;
}
#endif
static uint32_t intr(TCCState *S, int r)
{
if(r == TREG_R12)
return 12;
if(r >= TREG_R0 && r <= TREG_R3)
return r - TREG_R0;
if (!(r >= TREG_SP && r <= TREG_LR))
tcc_error(S, "compiler error! register %i is no int register",r);
return r + (13 - TREG_SP);
}
static void calcaddr(TCCState *S, uint32_t *base, int *off, int *sgn, int maxoff, unsigned shift)
{
if(*off>maxoff || *off&((1<<shift)-1)) {
uint32_t x, y;
x=0xE280E000;
if(*sgn)
x=0xE240E000;
x|=(*base)<<16;
*base=14; // lr
y=stuff_const(x,*off&~maxoff);
if(y) {
o(S, y);
*off&=maxoff;
return;
}
y=stuff_const(x,(*off+maxoff)&~maxoff);
if(y) {
o(S, y);
*sgn=!*sgn;
*off=((*off+maxoff)&~maxoff)-*off;
return;
}
stuff_const_harder(S, x,*off&~maxoff);
*off&=maxoff;
}
}
static uint32_t mapcc(TCCState *S, int cc)
{
switch(cc)
{
case TOK_ULT:
return 0x30000000; /* CC/LO */
case TOK_UGE:
return 0x20000000; /* CS/HS */
case TOK_EQ:
return 0x00000000; /* EQ */
case TOK_NE:
return 0x10000000; /* NE */
case TOK_ULE:
return 0x90000000; /* LS */
case TOK_UGT:
return 0x80000000; /* HI */
case TOK_Nset:
return 0x40000000; /* MI */
case TOK_Nclear:
return 0x50000000; /* PL */
case TOK_LT:
return 0xB0000000; /* LT */
case TOK_GE:
return 0xA0000000; /* GE */
case TOK_LE:
return 0xD0000000; /* LE */
case TOK_GT:
return 0xC0000000; /* GT */
}
tcc_error(S, "unexpected condition code");
return 0xE0000000; /* AL */
}
static int negcc(TCCState *S, int cc)
{
switch(cc)
{
case TOK_ULT:
return TOK_UGE;
case TOK_UGE:
return TOK_ULT;
case TOK_EQ:
return TOK_NE;
case TOK_NE:
return TOK_EQ;
case TOK_ULE:
return TOK_UGT;
case TOK_UGT:
return TOK_ULE;
case TOK_Nset:
return TOK_Nclear;
case TOK_Nclear:
return TOK_Nset;
case TOK_LT:
return TOK_GE;
case TOK_GE:
return TOK_LT;
case TOK_LE:
return TOK_GT;
case TOK_GT:
return TOK_LE;
}
tcc_error(S, "unexpected condition code");
return TOK_NE;
}
/* Load value into register r.
Use relative/got addressing to avoid setting DT_TEXTREL */
static void load_value(TCCState *S, SValue *sv, int r)
{
o(S, 0xE59F0000|(intr(S, r)<<12)); /* ldr r, [pc] */
o(S, 0xEA000000); /* b $+4 */
#ifndef CONFIG_TCC_PIE
if(sv->r & VT_SYM)
greloc(S, cur_text_section, sv->sym, S->ind, R_ARM_ABS32);
o(S, sv->c.i);
#else
if(sv->r & VT_SYM) {
if (sv->sym->type.t & VT_STATIC) {
greloc(cur_text_section, sv->sym, ind, R_ARM_REL32);
o(S, sv->c.i - 12);
o(S, 0xe080000f | (intr(S, r)<<12) | (intr(S, r)<<16)); // add rx,rx,pc
}
else {
greloc(cur_text_section, sv->sym, ind, R_ARM_GOT_PREL);
o(S, -12);
o(S, 0xe080000f | (intr(S, r)<<12) | (intr(S, r)<<16)); // add rx,rx,pc
o(S, 0xe5900000 | (intr(S, r)<<12) | (intr(S, r)<<16)); // ldr rx,[rx]
if (sv->c.i)
stuff_const_harder(S, 0xe2800000 | (intr(S, r)<<12) | (intr(S, r)<<16),
sv->c.i);
}
}
else
o(S, sv->c.i);
#endif
}
/* load 'r' from value 'sv' */
void load(TCCState *S, int r, SValue *sv)
{
int v, ft, fc, fr, sign;
uint32_t op;
SValue v1;
fr = sv->r;
ft = sv->type.t;
fc = sv->c.i;
if(fc>=0)
sign=0;
else {
sign=1;
fc=-fc;
}
v = fr & VT_VALMASK;
if (fr & VT_LVAL) {
uint32_t base = 0xB; // fp
if(v == VT_LLOCAL) {
v1.type.t = VT_PTR;
v1.r = VT_LOCAL | VT_LVAL;
v1.c.i = sv->c.i;
load(S, TREG_LR, &v1);
base = 14; /* lr */
fc=sign=0;
v=VT_LOCAL;
} else if(v == VT_CONST) {
v1.type.t = VT_PTR;
v1.r = fr&~VT_LVAL;
v1.c.i = sv->c.i;
v1.sym=sv->sym;
load(S, TREG_LR, &v1);
base = 14; /* lr */
fc=sign=0;
v=VT_LOCAL;
} else if(v < VT_CONST) {
base=intr(S, v);
fc=sign=0;
v=VT_LOCAL;
}
if(v == VT_LOCAL) {
if(is_float(ft)) {
calcaddr(S, &base,&fc,&sign,1020,2);
#ifdef TCC_ARM_VFP
op=0xED100A00; /* flds */
if(!sign)
op|=0x800000;
if ((ft & VT_BTYPE) != VT_FLOAT)
op|=0x100; /* flds -> fldd */
o(S, op|(vfpr(S, r)<<12)|(fc>>2)|(base<<16));
#else
op=0xED100100;
if(!sign)
op|=0x800000;
#if LDOUBLE_SIZE == 8
if ((ft & VT_BTYPE) != VT_FLOAT)
op|=0x8000;
#else
if ((ft & VT_BTYPE) == VT_DOUBLE)
op|=0x8000;
else if ((ft & VT_BTYPE) == VT_LDOUBLE)
op|=0x400000;
#endif
o(S, op|(fpr(S, r)<<12)|(fc>>2)|(base<<16));
#endif
} else if((ft & (VT_BTYPE|VT_UNSIGNED)) == VT_BYTE
|| (ft & VT_BTYPE) == VT_SHORT) {
calcaddr(S, &base,&fc,&sign,255,0);
op=0xE1500090;
if ((ft & VT_BTYPE) == VT_SHORT)
op|=0x20;
if ((ft & VT_UNSIGNED) == 0)
op|=0x40;
if(!sign)
op|=0x800000;
o(S, op|(intr(S, r)<<12)|(base<<16)|((fc&0xf0)<<4)|(fc&0xf));
} else {
calcaddr(S, &base,&fc,&sign,4095,0);
op=0xE5100000;
if(!sign)
op|=0x800000;
if ((ft & VT_BTYPE) == VT_BYTE || (ft & VT_BTYPE) == VT_BOOL)
op|=0x400000;
o(S, op|(intr(S, r)<<12)|fc|(base<<16));
}
return;
}
} else {
if (v == VT_CONST) {
op=stuff_const(0xE3A00000|(intr(S, r)<<12),sv->c.i);
if (fr & VT_SYM || !op)
load_value(S, sv, r);
else
o(S, op);
return;
} else if (v == VT_LOCAL) {
op=stuff_const(0xE28B0000|(intr(S, r)<<12),sv->c.i);
if (fr & VT_SYM || !op) {
load_value(S, sv, r);
o(S, 0xE08B0000|(intr(S, r)<<12)|intr(S, r));
} else
o(S, op);
return;
} else if(v == VT_CMP) {
o(S, mapcc(S, sv->c.i)|0x3A00001|(intr(S, r)<<12));
o(S, mapcc(S, negcc(S, sv->c.i))|0x3A00000|(intr(S, r)<<12));
return;
} else if (v == VT_JMP || v == VT_JMPI) {
int t;
t = v & 1;
o(S, 0xE3A00000|(intr(S, r)<<12)|t);
o(S, 0xEA000000);
gsym(S, sv->c.i);
o(S, 0xE3A00000|(intr(S, r)<<12)|(t^1));
return;
} else if (v < VT_CONST) {
if(is_float(ft))
#ifdef TCC_ARM_VFP
o(S, 0xEEB00A40|(vfpr(S, r)<<12)|vfpr(S, v)|T2CPR(ft)); /* fcpyX */
#else
o(S, 0xEE008180|(fpr(S, r)<<12)|fpr(S, v));
#endif
else
o(S, 0xE1A00000|(intr(S, r)<<12)|intr(S, v));
return;
}
}
tcc_error(S, "load unimplemented!");
}
/* store register 'r' in lvalue 'v' */
void store(TCCState *S, int r, SValue *sv)
{
SValue v1;
int v, ft, fc, fr, sign;
uint32_t op;
fr = sv->r;
ft = sv->type.t;
fc = sv->c.i;
if(fc>=0)
sign=0;
else {
sign=1;
fc=-fc;
}
v = fr & VT_VALMASK;
if (fr & VT_LVAL || fr == VT_LOCAL) {
uint32_t base = 0xb; /* fp */
if(v < VT_CONST) {
base=intr(S, v);
v=VT_LOCAL;
fc=sign=0;
} else if(v == VT_CONST) {
v1.type.t = ft;
v1.r = fr&~VT_LVAL;
v1.c.i = sv->c.i;
v1.sym=sv->sym;
load(S, TREG_LR, &v1);
base = 14; /* lr */
fc=sign=0;
v=VT_LOCAL;
}
if(v == VT_LOCAL) {
if(is_float(ft)) {
calcaddr(S, &base,&fc,&sign,1020,2);
#ifdef TCC_ARM_VFP
op=0xED000A00; /* fsts */
if(!sign)
op|=0x800000;
if ((ft & VT_BTYPE) != VT_FLOAT)
op|=0x100; /* fsts -> fstd */
o(S, op|(vfpr(S, r)<<12)|(fc>>2)|(base<<16));
#else
op=0xED000100;
if(!sign)
op|=0x800000;
#if LDOUBLE_SIZE == 8
if ((ft & VT_BTYPE) != VT_FLOAT)
op|=0x8000;
#else
if ((ft & VT_BTYPE) == VT_DOUBLE)
op|=0x8000;
if ((ft & VT_BTYPE) == VT_LDOUBLE)
op|=0x400000;
#endif
o(S, op|(fpr(S, r)<<12)|(fc>>2)|(base<<16));
#endif
return;
} else if((ft & VT_BTYPE) == VT_SHORT) {
calcaddr(S, &base,&fc,&sign,255,0);
op=0xE14000B0;
if(!sign)
op|=0x800000;
o(S, op|(intr(S, r)<<12)|(base<<16)|((fc&0xf0)<<4)|(fc&0xf));
} else {
calcaddr(S, &base,&fc,&sign,4095,0);
op=0xE5000000;
if(!sign)
op|=0x800000;
if ((ft & VT_BTYPE) == VT_BYTE || (ft & VT_BTYPE) == VT_BOOL)
op|=0x400000;
o(S, op|(intr(S, r)<<12)|fc|(base<<16));
}
return;
}
}
tcc_error(S, "store unimplemented");
}
static void gadd_sp(TCCState *S, int val)
{
stuff_const_harder(S, 0xE28DD000,val);
}
/* 'is_jmp' is '1' if it is a jump */
static void gcall_or_jmp(TCCState *S, int is_jmp)
{
int r;
uint32_t x;
if ((S->vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
/* constant case */
if(S->vtop->r & VT_SYM){
x=encbranch(S, S->ind, S->ind+S->vtop->c.i,0);
if(x) {
/* relocation case */
greloc(S, cur_text_section, S->vtop->sym, S->ind, R_ARM_PC24);
o(S, x|(is_jmp?0xE0000000:0xE1000000));
} else {
r = TREG_LR;
load_value(S, S->vtop, r);
if(is_jmp)
o(S, 0xE1A0F000 | intr(S, r)); // mov pc, r
else
o(S, 0xe12fff30 | intr(S, r)); // blx r
}
}else{
if(!is_jmp)
o(S, 0xE28FE004); // add lr,pc,#4
o(S, 0xE51FF004); // ldr pc,[pc,#-4]
o(S, S->vtop->c.i);
}
} else {
/* otherwise, indirect call */
#ifdef CONFIG_TCC_BCHECK
S->vtop->r &= ~VT_MUSTBOUND;
#endif
r = gv(S, RC_INT);
if(!is_jmp)
o(S, 0xE1A0E00F); // mov lr,pc
o(S, 0xE1A0F000|intr(S, r)); // mov pc,r
}
}
#if defined(CONFIG_TCC_BCHECK)
static void gen_bounds_call(TCCState *S, int v)
{
Sym *sym = external_helper_sym(S, v);
greloc(S, cur_text_section, sym, S->ind, R_ARM_PC24);
o(S, 0xebfffffe);
}
static void gen_bounds_prolog(TCCState *S)
{
/* leave some room for bound checking code */
S->func_bound_offset = lbounds_section->data_offset;
S->func_bound_ind = S->ind;
S->func_bound_add_epilog = 0;
o(S, 0xe1a00000); /* ld r0,lbounds_section->data_offset */
o(S, 0xe1a00000);
o(S, 0xe1a00000);
o(S, 0xe1a00000);
o(S, 0xe1a00000); /* call __bound_local_new */
}
static void gen_bounds_epilog(TCCState *S)
{
addr_t saved_ind;
addr_t *bounds_ptr;
Sym *sym_data;
int offset_modified = S->func_bound_offset != lbounds_section->data_offset;
if (!offset_modified && !S->func_bound_add_epilog)
return;
/* add end of table info */
bounds_ptr = section_ptr_add(S, lbounds_section, sizeof(addr_t));
*bounds_ptr = 0;
sym_data = get_sym_ref(S, &S->char_pointer_type, lbounds_section,
S->func_bound_offset, lbounds_section->data_offset);
/* generate bound local allocation */
if (offset_modified) {
saved_ind = S->ind;
S->ind = S->func_bound_ind;
o(S, 0xe59f0000); /* ldr r0, [pc] */
o(S, 0xea000000); /* b $+4 */
greloc(S, cur_text_section, sym_data, S->ind, R_ARM_REL32);
o(S, -12); /* lbounds_section->data_offset */
o(S, 0xe080000f); /* add r0,r0,pc */
gen_bounds_call(S, TOK___bound_local_new);
S->ind = saved_ind;
}
/* generate bound check local freeing */
o(S, 0xe92d0003); /* push {r0,r1} */
o(S, 0xed2d0b02); /* vpush {d0} */
o(S, 0xe59f0000); /* ldr r0, [pc] */
o(S, 0xea000000); /* b $+4 */
greloc(S, cur_text_section, sym_data, S->ind, R_ARM_REL32);
o(S, -12); /* lbounds_section->data_offset */
o(S, 0xe080000f); /* add r0,r0,pc */
gen_bounds_call(S, TOK___bound_local_delete);
o(S, 0xecbd0b02); /* vpop {d0} */
o(S, 0xe8bd0003); /* pop {r0,r1} */
}
#endif
static int unalias_ldbl(int btype)
{
#if LDOUBLE_SIZE == 8
if (btype == VT_LDOUBLE)
btype = VT_DOUBLE;
#endif
return btype;
}
/* Return whether a structure is an homogeneous float aggregate or not.
The answer is true if all the elements of the structure are of the same
primitive float type and there is less than 4 elements.
type: the type corresponding to the structure to be tested */
static int is_hgen_float_aggr(CType *type)
{
if ((type->t & VT_BTYPE) == VT_STRUCT) {
struct Sym *ref;
int btype, nb_fields = 0;
ref = type->ref->next;
if (ref) {
btype = unalias_ldbl(ref->type.t & VT_BTYPE);
if (btype == VT_FLOAT || btype == VT_DOUBLE) {
for(; ref && btype == unalias_ldbl(ref->type.t & VT_BTYPE); ref = ref->next, nb_fields++);
return !ref && nb_fields <= 4;
}
}
}
return 0;
}
struct avail_regs {
signed char avail[3]; /* 3 holes max with only float and double alignments */
int first_hole; /* first available hole */
int last_hole; /* last available hole (none if equal to first_hole) */
int first_free_reg; /* next free register in the sequence, hole excluded */
};
/* Find suitable registers for a VFP Co-Processor Register Candidate (VFP CPRC
param) according to the rules described in the procedure call standard for
the ARM architecture (AAPCS). If found, the registers are assigned to this
VFP CPRC parameter. Registers are allocated in sequence unless a hole exists
and the parameter is a single float.
avregs: opaque structure to keep track of available VFP co-processor regs
align: alignment constraints for the param, as returned by type_size()
size: size of the parameter, as returned by type_size() */
int assign_vfpreg(struct avail_regs *avregs, int align, int size)
{
int first_reg = 0;
if (avregs->first_free_reg == -1)
return -1;
if (align >> 3) { /* double alignment */
first_reg = avregs->first_free_reg;
/* alignment constraint not respected so use next reg and record hole */
if (first_reg & 1)
avregs->avail[avregs->last_hole++] = first_reg++;
} else { /* no special alignment (float or array of float) */
/* if single float and a hole is available, assign the param to it */
if (size == 4 && avregs->first_hole != avregs->last_hole)
return avregs->avail[avregs->first_hole++];
else
first_reg = avregs->first_free_reg;
}
if (first_reg + size / 4 <= 16) {
avregs->first_free_reg = first_reg + size / 4;
return first_reg;
}
avregs->first_free_reg = -1;
return -1;
}
/* Returns whether all params need to be passed in core registers or not.
This is the case for function part of the runtime ABI. */
int floats_in_core_regs(SValue *sval)
{
if (!sval->sym)
return 0;
switch (sval->sym->v) {
case TOK___floatundisf:
case TOK___floatundidf:
case TOK___fixunssfdi:
case TOK___fixunsdfdi:
#ifndef TCC_ARM_VFP
case TOK___fixunsxfdi:
#endif
case TOK___floatdisf:
case TOK___floatdidf:
case TOK___fixsfdi:
case TOK___fixdfdi:
return 1;
default:
return 0;
}
}
/* Return the number of registers needed to return the struct, or 0 if
returning via struct pointer. */
ST_FUNC int gfunc_sret(TCCState *S, CType *vt, int variadic, CType *ret, int *ret_align, int *regsize) {
#ifdef TCC_ARM_EABI
int size, align;
size = type_size(vt, &align);
if (S->float_abi == ARM_HARD_FLOAT && !variadic &&
(is_float(vt->t) || is_hgen_float_aggr(vt))) {
*ret_align = 8;
*regsize = 8;
ret->ref = NULL;
ret->t = VT_DOUBLE;
return (size + 7) >> 3;
} else if (size > 0 && size <= 4) {
*ret_align = 4;