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vivado_14880.backup.log
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vivado_14880.backup.log
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#-----------------------------------------------------------
# Vivado v2022.2.2 (64-bit)
# SW Build 3788238 on Tue Feb 21 20:00:34 MST 2023
# IP Build 3783773 on Tue Feb 21 23:41:56 MST 2023
# Start of session at: Fri Jun 2 17:41:26 2023
# Process ID: 14880
# Current directory: D:/Workspaces/Verilog/Pipelined
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent3476 D:\Workspaces\Verilog\Pipelined\Pipelined.xpr
# Log file: D:/Workspaces/Verilog/Pipelined/vivado.log
# Journal file: D:/Workspaces/Verilog/Pipelined\vivado.jou
# Running On: DESKTOP-LCCEBF0, OS: Windows, CPU Frequency: 2208 MHz, CPU Physical cores: 6, Host memory: 34142 MB
#-----------------------------------------------------------
start_gui
open_project D:/Workspaces/Verilog/Pipelined/Pipelined.xpr
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-a7-100:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/arty-a7-100/E.0/1.0/board.xml as part xc7a100tcsg324-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-a7-100:part0:1.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/arty-a7-100/E.0/1.1/board.xml as part xc7a100tcsg324-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-a7-35:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/arty-a7-35/E.0/1.0/board.xml as part xc7a35ticsg324-1l specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-a7-35:part0:1.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/arty-a7-35/E.0/1.1/board.xml as part xc7a35ticsg324-1l specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-25:part0:1.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/arty-s7-25/E.0/board.xml as part xc7s25csga324-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-50:part0:1.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/arty-s7-50/B.0/board.xml as part xc7s50csga324-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty:part0:1.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/arty/C.0/board.xml as part xc7a35ticsg324-1l specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:basys3:part0:1.2 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/basys3/C.0/board.xml as part xc7a35tcpg236-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:cmod-s7-25:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/cmod-s7-25/B.0/board.xml as part xc7s25csga225-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:cmod_a7-15t:part0:1.2 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/cmod_a7-15t/B.0/board.xml as part xc7a15tcpg236-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:cmod_a7-35t:part0:1.2 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/cmod_a7-35t/B.0/board.xml as part xc7a35tcpg236-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:gzu_3eg:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/genesys-zu-3eg/B.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:gzu_3eg:part0:1.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/genesys-zu-3eg/D.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:gzu_5ev:part0:1.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/genesys-zu-5ev/C.0/board.xml as part xczu5ev-sfvc784-1-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:nexys-a7-100t:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/nexys-a7-100t/D.0/1.0/board.xml as part xc7a100tcsg324-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:nexys-a7-100t:part0:1.3 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/nexys-a7-100t/D.0/1.3/board.xml as part xc7a100tcsg324-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:nexys-a7-50t:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/nexys-a7-50t/D.0/1.0/board.xml as part xc7a50ticsg324-1l specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:nexys-a7-50t:part0:1.3 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/nexys-a7-50t/D.0/1.3/board.xml as part xc7a50ticsg324-1l specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:nexys4:part0:1.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/nexys4/B.1/board.xml as part xc7a100tcsg324-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:nexys4_ddr:part0:1.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/nexys4_ddr/C.1/board.xml as part xc7a100tcsg324-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:nexys_video:part0:1.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/nexys_video/A.0/1.1/board.xml as part xc7a200tsbg484-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:nexys_video:part0:1.2 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/nexys_video/A.0/1.2/board.xml as part xc7a200tsbg484-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:usb104-a7:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/usb104-a7/B/1.0/board.xml as part xc7a100tcsg324-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:usb104-a7:part0:1.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/usb104-a7/B/1.1/board.xml as part xc7a100tcsg324-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:usb104-a7:part0:1.2 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/usb104-a7/B/1.2/board.xml as part xc7a100tcsg324-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:usb104-a7:part0:1.3 available at D:/Programs/Xilinx/Vivado/2022.2/data/boards/board_files/usb104-a7/B/1.3/board.xml as part xc7a100tcsg324-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:ac701:part0:1.4 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/ac701/1.4/board.xml as part xc7a200tfbg676-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26c:part0:1.2 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/k26c/1.2/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26c:part0:1.3 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/k26c/1.3/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26c:part0:1.4 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/k26c/1.4/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26i:part0:1.2 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/k26i/1.2/board.xml as part xck26-sfvc784-2lvi-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26i:part0:1.3 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/k26i/1.3/board.xml as part xck26-sfvc784-2lvi-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26i:part0:1.4 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/k26i/1.4/board.xml as part xck26-sfvc784-2lvi-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.4 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.4/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.5 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.5/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kr260_som:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kr260_som/1.0/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kr260_som:part0:1.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kr260_som/1.1/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kv260_som:part0:1.2 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kv260_som/1.2/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kv260_som:part0:1.3 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kv260_som/1.3/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kv260_som:part0:1.4 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kv260_som/1.4/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:sp701:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/sp701/1.0/board.xml as part xc7s100fgga676-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:sp701:part0:1.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/sp701/1.1/board.xml as part xc7s100fgga676-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.1/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu104:part0:1.1 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu104/1.1/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.4 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.4/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.5 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.5/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.6 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.6/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at D:/Programs/Xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'D:/Workspaces/Verilog/Pipelined/Pipelined.gen/sources_1'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Programs/Xilinx/Vivado/2022.2/data/ip'.
open_project: Time (s): cpu = 00:00:27 ; elapsed = 00:00:12 . Memory (MB): peak = 1180.121 ; gain = 407.441
update_compile_order -fileset sources_1
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'CPU'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'D:/Programs/Xilinx/Vivado/2022.2/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'CPU' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj CPU_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Adder.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Adder
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Constant.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Constant15
INFO: [VRFC 10-311] analyzing module Constant4
INFO: [VRFC 10-311] analyzing module Constant0
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Decoder_4to16.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Decoder_4to16
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Extender.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Extender
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Instruction_memory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module IMem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Memory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module DMem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Mux_16to1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Mux_16to1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Mux_2to1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Mux_2to1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Pipeline.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module DP_IF
INFO: [VRFC 10-311] analyzing module DP_ID
INFO: [VRFC 10-311] analyzing module DP_EX
INFO: [VRFC 10-311] analyzing module DP_MEM
INFO: [VRFC 10-311] analyzing module DP_WB
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Register_file.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register_file
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Register_sync_rw.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register_sync_rw
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/CPU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CPU
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot CPU_behav xil_defaultlib.CPU xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.2.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: D:/Programs/Xilinx/Vivado/2022.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot CPU_behav xil_defaultlib.CPU xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'Op' [D:/Workspaces/ODTU/EE446/EXP4/CPU.v:22]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'Cond' [D:/Workspaces/ODTU/EE446/EXP4/CPU.v:48]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 6 for port 'Funct' [D:/Workspaces/ODTU/EE446/EXP4/CPU.v:49]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'Op' [D:/Workspaces/ODTU/EE446/EXP4/CPU.v:50]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'Rd' [D:/Workspaces/ODTU/EE446/EXP4/CPU.v:52]
WARNING: [VRFC 10-3091] actual bit length 15 differs from formal bit length 16 for port 'OUT' [D:/Workspaces/ODTU/EE446/EXP4/Register_file.v:19]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4100] "D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.Controller
Compiling module xil_defaultlib.Constant0
Compiling module xil_defaultlib.IMem(BYTE_SIZE=4,ADDR_WIDTH=32)
Compiling module xil_defaultlib.Adder(WIDTH=32)
Compiling module xil_defaultlib.Constant4
Compiling module xil_defaultlib.DP_WB
Compiling module xil_defaultlib.Extender
Compiling module xil_defaultlib.Mux_2to1(WIDTH=32)
Compiling module xil_defaultlib.ALU(WIDTH=32)
Compiling module xil_defaultlib.DMem(BYTE_SIZE=4,ADDR_WIDTH=32)
Compiling module xil_defaultlib.DP_IF
Compiling module xil_defaultlib.Constant15
Compiling module xil_defaultlib.DP_ID
Compiling module xil_defaultlib.DP_EX
Compiling module xil_defaultlib.DP_MEM
Compiling module xil_defaultlib.Mux_2to1(WIDTH=4)
Compiling module xil_defaultlib.Register_sync_rw(WIDTH=32)
Compiling module xil_defaultlib.Decoder_4to16
Compiling module xil_defaultlib.Mux_16to1
Compiling module xil_defaultlib.Register_file(WIDTH=32)
Compiling module xil_defaultlib.Datapath
Compiling module xil_defaultlib.CPU
Compiling module xil_defaultlib.glbl
Built simulation snapshot CPU_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "CPU_behav -key {Behavioral:sim_1:Functional:CPU} -tclbatch {CPU.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
source CPU.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
WARNING: File mem_data.txt referenced on D:/Workspaces/ODTU/EE446/EXP4/Constant.v at line 21 cannot be opened for reading. Please ensure that this file is available in the current working directory.
WARNING: File mem_data.txt referenced on D:/Workspaces/ODTU/EE446/EXP4/Constant.v at line 21 cannot be opened for reading. Please ensure that this file is available in the current working directory.
INFO: [USF-XSim-96] XSim completed. Design snapshot 'CPU_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1232.023 ; gain = 25.824
add_force {/CPU/clk} -radix hex {1 0ns} {0 50000ps} -repeat_every 100000ps
add_force {/CPU/reset} -radix hex {0 0ns}
run 800 ps
add_force {/CPU/clk} -radix hex {1 0ns} {0 50000ps} -repeat_every 100000ps
run 800 ps
run 800 ps
run 2 ns
remove_forces { {/CPU/clk} }
add_force {/CPU/clk} -radix bin {1 0ns} {0 50000ps} -repeat_every 100000ps
run 2 ns
remove_forces { {/CPU/clk} }
add_force {/CPU/clk} -radix bin {1 0ns} {0 50ps} -repeat_every 100ps
run 2 ns
add_force {/CPU/reset} -radix hex {1 1ns}
run 2 ns
add_force {/CPU/reset} -radix hex {0 0ns}
run 2 ns
run 2 ns
run 2 ns
add_force {/CPU/reset} -radix hex {1 0ns} -cancel_after 1ns
run 2 ns
save_wave_config {D:/Workspaces/Verilog/Pipelined/CPU_behav.wcfg}
add_files -fileset sim_1 -norecurse D:/Workspaces/Verilog/Pipelined/CPU_behav.wcfg
set_property xsim.view D:/Workspaces/Verilog/Pipelined/CPU_behav.wcfg [get_filesets sim_1]
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'CPU'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'D:/Programs/Xilinx/Vivado/2022.2/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'CPU' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj CPU_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Adder.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Adder
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Constant.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Constant15
INFO: [VRFC 10-311] analyzing module Constant4
INFO: [VRFC 10-311] analyzing module Constant0
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Decoder_4to16.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Decoder_4to16
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Extender.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Extender
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Instruction_memory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module IMem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Memory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module DMem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Mux_16to1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Mux_16to1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Mux_2to1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Mux_2to1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Pipeline.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module DP_IF
INFO: [VRFC 10-311] analyzing module DP_ID
INFO: [VRFC 10-311] analyzing module DP_EX
INFO: [VRFC 10-311] analyzing module DP_MEM
INFO: [VRFC 10-311] analyzing module DP_WB
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Register_file.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register_file
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Register_sync_rw.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register_sync_rw
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/CPU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CPU
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot CPU_behav xil_defaultlib.CPU xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.2.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: D:/Programs/Xilinx/Vivado/2022.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot CPU_behav xil_defaultlib.CPU xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 15 differs from formal bit length 16 for port 'OUT' [D:/Workspaces/ODTU/EE446/EXP4/Register_file.v:19]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4100] "D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.Controller
Compiling module xil_defaultlib.Constant0
Compiling module xil_defaultlib.IMem(BYTE_SIZE=4,ADDR_WIDTH=32)
Compiling module xil_defaultlib.Adder(WIDTH=32)
Compiling module xil_defaultlib.Constant4
Compiling module xil_defaultlib.DP_WB
Compiling module xil_defaultlib.Extender
Compiling module xil_defaultlib.Mux_2to1(WIDTH=32)
Compiling module xil_defaultlib.ALU(WIDTH=32)
Compiling module xil_defaultlib.DMem(BYTE_SIZE=4,ADDR_WIDTH=32)
Compiling module xil_defaultlib.DP_IF
Compiling module xil_defaultlib.Constant15
Compiling module xil_defaultlib.DP_ID
Compiling module xil_defaultlib.DP_EX
Compiling module xil_defaultlib.DP_MEM
Compiling module xil_defaultlib.Mux_2to1(WIDTH=4)
Compiling module xil_defaultlib.Register_sync_rw(WIDTH=32)
Compiling module xil_defaultlib.Decoder_4to16
Compiling module xil_defaultlib.Mux_16to1
Compiling module xil_defaultlib.Register_file(WIDTH=32)
Compiling module xil_defaultlib.Datapath
Compiling module xil_defaultlib.CPU
Compiling module xil_defaultlib.glbl
Built simulation snapshot CPU_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "CPU_behav -key {Behavioral:sim_1:Functional:CPU} -tclbatch {CPU.tcl} -view {D:/Workspaces/Verilog/Pipelined/CPU_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
open_wave_config D:/Workspaces/Verilog/Pipelined/CPU_behav.wcfg
source CPU.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
WARNING: File mem_data.txt referenced on D:/Workspaces/ODTU/EE446/EXP4/Constant.v at line 21 cannot be opened for reading. Please ensure that this file is available in the current working directory.
WARNING: File mem_data.txt referenced on D:/Workspaces/ODTU/EE446/EXP4/Constant.v at line 21 cannot be opened for reading. Please ensure that this file is available in the current working directory.
INFO: [USF-XSim-96] XSim completed. Design snapshot 'CPU_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.039 ; gain = 6.867
run 2 ns
run 2 ns
run 2 ns
run 2 ns
run 2 ns
run 2 ns
run 2 ns
run 2 ns
reset_run synth_1
INFO: [Project 1-1160] Copying file D:/Workspaces/Verilog/Pipelined/Pipelined.runs/synth_1/CPU.dcp to D:/Workspaces/Verilog/Pipelined/Pipelined.srcs/utils_1/imports/synth_1 and adding it to utils fileset
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory D:/Workspaces/Verilog/Pipelined/Pipelined.runs/synth_1
launch_runs synth_1 -jobs 6
[Fri Jun 2 17:51:59 2023] Launched synth_1...
Run output will be captured here: D:/Workspaces/Verilog/Pipelined/Pipelined.runs/synth_1/runme.log
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'CPU'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
boost::filesystem::remove: The process cannot access the file because it is being used by another process: "D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim/simulate.log"
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'CPU'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'D:/Programs/Xilinx/Vivado/2022.2/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'CPU' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj CPU_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Adder.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Adder
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Constant.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Constant15
INFO: [VRFC 10-311] analyzing module Constant4
INFO: [VRFC 10-311] analyzing module Constant0
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Decoder_4to16.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Decoder_4to16
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Extender.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Extender
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Instruction_memory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module IMem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Memory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module DMem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Mux_16to1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Mux_16to1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Mux_2to1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Mux_2to1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Pipeline.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module DP_IF
INFO: [VRFC 10-311] analyzing module DP_ID
INFO: [VRFC 10-311] analyzing module DP_EX
INFO: [VRFC 10-311] analyzing module DP_MEM
INFO: [VRFC 10-311] analyzing module DP_WB
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Register_file.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register_file
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Register_sync_rw.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register_sync_rw
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/CPU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CPU
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot CPU_behav xil_defaultlib.CPU xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.2.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: D:/Programs/Xilinx/Vivado/2022.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot CPU_behav xil_defaultlib.CPU xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 15 differs from formal bit length 16 for port 'OUT' [D:/Workspaces/ODTU/EE446/EXP4/Register_file.v:19]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4100] "D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.Controller
Compiling module xil_defaultlib.Constant0
Compiling module xil_defaultlib.IMem(BYTE_SIZE=4,ADDR_WIDTH=32)
Compiling module xil_defaultlib.Adder(WIDTH=32)
Compiling module xil_defaultlib.Constant4
Compiling module xil_defaultlib.DP_WB
Compiling module xil_defaultlib.Extender
Compiling module xil_defaultlib.Mux_2to1(WIDTH=32)
Compiling module xil_defaultlib.ALU(WIDTH=32)
Compiling module xil_defaultlib.DMem(BYTE_SIZE=4,ADDR_WIDTH=32)
Compiling module xil_defaultlib.DP_IF
Compiling module xil_defaultlib.Constant15
Compiling module xil_defaultlib.DP_ID
Compiling module xil_defaultlib.DP_EX
Compiling module xil_defaultlib.DP_MEM
Compiling module xil_defaultlib.Mux_2to1(WIDTH=4)
Compiling module xil_defaultlib.Register_sync_rw(WIDTH=32)
Compiling module xil_defaultlib.Decoder_4to16
Compiling module xil_defaultlib.Mux_16to1
Compiling module xil_defaultlib.Register_file(WIDTH=32)
Compiling module xil_defaultlib.Datapath
Compiling module xil_defaultlib.CPU
Compiling module xil_defaultlib.glbl
Built simulation snapshot CPU_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "CPU_behav -key {Behavioral:sim_1:Functional:CPU} -tclbatch {CPU.tcl} -view {D:/Workspaces/Verilog/Pipelined/CPU_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
open_wave_config D:/Workspaces/Verilog/Pipelined/CPU_behav.wcfg
source CPU.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
WARNING: File mem_data.txt referenced on D:/Workspaces/ODTU/EE446/EXP4/Constant.v at line 21 cannot be opened for reading. Please ensure that this file is available in the current working directory.
WARNING: File mem_data.txt referenced on D:/Workspaces/ODTU/EE446/EXP4/Constant.v at line 21 cannot be opened for reading. Please ensure that this file is available in the current working directory.
INFO: [USF-XSim-96] XSim completed. Design snapshot 'CPU_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1267.242 ; gain = 7.102
run 2 ns
add_force {/CPU/reset} -radix hex {0 0ns}
add_force {/CPU/reset} -radix bin {1 0ns} -cancel_after 1ns
add_force {/CPU/clk} -radix bin {1 0ns} {0 50ps} -repeat_every 100ps
run 2 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'CPU'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'D:/Programs/Xilinx/Vivado/2022.2/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'CPU' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj CPU_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Adder.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Adder
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Constant.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Constant15
INFO: [VRFC 10-311] analyzing module Constant4
INFO: [VRFC 10-311] analyzing module Constant0
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Decoder_4to16.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Decoder_4to16
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Extender.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Extender
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Instruction_memory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module IMem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Memory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module DMem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Mux_16to1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Mux_16to1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Mux_2to1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Mux_2to1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Pipeline.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module DP_IF
INFO: [VRFC 10-311] analyzing module DP_ID
INFO: [VRFC 10-311] analyzing module DP_EX
INFO: [VRFC 10-311] analyzing module DP_MEM
INFO: [VRFC 10-311] analyzing module DP_WB
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Register_file.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register_file
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Register_sync_rw.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register_sync_rw
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/CPU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CPU
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot CPU_behav xil_defaultlib.CPU xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.2.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: D:/Programs/Xilinx/Vivado/2022.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot CPU_behav xil_defaultlib.CPU xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 15 differs from formal bit length 16 for port 'OUT' [D:/Workspaces/ODTU/EE446/EXP4/Register_file.v:19]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4100] "D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.Controller
Compiling module xil_defaultlib.Constant0
Compiling module xil_defaultlib.IMem(BYTE_SIZE=4,ADDR_WIDTH=32)
Compiling module xil_defaultlib.Adder(WIDTH=32)
Compiling module xil_defaultlib.Constant4
Compiling module xil_defaultlib.DP_WB
Compiling module xil_defaultlib.Extender
Compiling module xil_defaultlib.Mux_2to1(WIDTH=32)
Compiling module xil_defaultlib.ALU(WIDTH=32)
Compiling module xil_defaultlib.DMem(BYTE_SIZE=4,ADDR_WIDTH=32)
Compiling module xil_defaultlib.DP_IF
Compiling module xil_defaultlib.Constant15
Compiling module xil_defaultlib.DP_ID
Compiling module xil_defaultlib.DP_EX
Compiling module xil_defaultlib.DP_MEM
Compiling module xil_defaultlib.Mux_2to1(WIDTH=4)
Compiling module xil_defaultlib.Register_sync_rw(WIDTH=32)
Compiling module xil_defaultlib.Decoder_4to16
Compiling module xil_defaultlib.Mux_16to1
Compiling module xil_defaultlib.Register_file(WIDTH=32)
Compiling module xil_defaultlib.Datapath
Compiling module xil_defaultlib.CPU
Compiling module xil_defaultlib.glbl
Built simulation snapshot CPU_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "CPU_behav -key {Behavioral:sim_1:Functional:CPU} -tclbatch {CPU.tcl} -view {D:/Workspaces/Verilog/Pipelined/CPU_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
open_wave_config D:/Workspaces/Verilog/Pipelined/CPU_behav.wcfg
source CPU.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
WARNING: File mem_data.txt referenced on D:/Workspaces/ODTU/EE446/EXP4/Constant.v at line 21 cannot be opened for reading. Please ensure that this file is available in the current working directory.
WARNING: File mem_data.txt referenced on D:/Workspaces/ODTU/EE446/EXP4/Constant.v at line 21 cannot be opened for reading. Please ensure that this file is available in the current working directory.
INFO: [USF-XSim-96] XSim completed. Design snapshot 'CPU_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1269.648 ; gain = 0.906
add_force {/CPU/reset} -radix bin {1 0ns} {0 50ps} -repeat_every 100ps
remove_forces { {/CPU/reset} }
add_force {/CPU/clk} -radix bin {1 0ns} {0 50ps} -repeat_every 100ps
add_force {/CPU/reset} -radix bin {0 0ns}
add_force {/CPU/reset} -radix bin {1 0ns} -cancel_after 1ns
run 2 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'CPU'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'D:/Programs/Xilinx/Vivado/2022.2/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'CPU' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj CPU_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Adder.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Adder
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Constant.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Constant15
INFO: [VRFC 10-311] analyzing module Constant4
INFO: [VRFC 10-311] analyzing module Constant0
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Decoder_4to16.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Decoder_4to16
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Extender.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Extender
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Instruction_memory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module IMem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Memory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module DMem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Mux_16to1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Mux_16to1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Mux_2to1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Mux_2to1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Pipeline.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module DP_IF
INFO: [VRFC 10-311] analyzing module DP_ID
INFO: [VRFC 10-311] analyzing module DP_EX
INFO: [VRFC 10-311] analyzing module DP_MEM
INFO: [VRFC 10-311] analyzing module DP_WB
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Register_file.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register_file
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Register_sync_rw.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register_sync_rw
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/CPU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CPU
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot CPU_behav xil_defaultlib.CPU xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.2.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: D:/Programs/Xilinx/Vivado/2022.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot CPU_behav xil_defaultlib.CPU xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 15 differs from formal bit length 16 for port 'OUT' [D:/Workspaces/ODTU/EE446/EXP4/Register_file.v:19]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4100] "D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.Controller
Compiling module xil_defaultlib.Constant0
Compiling module xil_defaultlib.IMem(BYTE_SIZE=4,ADDR_WIDTH=32)
Compiling module xil_defaultlib.Adder(WIDTH=32)
Compiling module xil_defaultlib.Constant4
Compiling module xil_defaultlib.DP_WB
Compiling module xil_defaultlib.Extender
Compiling module xil_defaultlib.Mux_2to1(WIDTH=32)
Compiling module xil_defaultlib.ALU(WIDTH=32)
Compiling module xil_defaultlib.DMem(BYTE_SIZE=4,ADDR_WIDTH=32)
Compiling module xil_defaultlib.DP_IF
Compiling module xil_defaultlib.Constant15
Compiling module xil_defaultlib.DP_ID
Compiling module xil_defaultlib.DP_EX
Compiling module xil_defaultlib.DP_MEM
Compiling module xil_defaultlib.Mux_2to1(WIDTH=4)
Compiling module xil_defaultlib.Register_sync_rw(WIDTH=32)
Compiling module xil_defaultlib.Decoder_4to16
Compiling module xil_defaultlib.Mux_16to1
Compiling module xil_defaultlib.Register_file(WIDTH=32)
Compiling module xil_defaultlib.Datapath
Compiling module xil_defaultlib.CPU
Compiling module xil_defaultlib.glbl
Built simulation snapshot CPU_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "CPU_behav -key {Behavioral:sim_1:Functional:CPU} -tclbatch {CPU.tcl} -view {D:/Workspaces/Verilog/Pipelined/CPU_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
open_wave_config D:/Workspaces/Verilog/Pipelined/CPU_behav.wcfg
source CPU.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
WARNING: File mem_data.txt referenced on D:/Workspaces/ODTU/EE446/EXP4/Constant.v at line 21 cannot be opened for reading. Please ensure that this file is available in the current working directory.
WARNING: File mem_data.txt referenced on D:/Workspaces/ODTU/EE446/EXP4/Constant.v at line 21 cannot be opened for reading. Please ensure that this file is available in the current working directory.
INFO: [USF-XSim-96] XSim completed. Design snapshot 'CPU_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1272.371 ; gain = 1.949
add_force {/CPU/reset} -radix bin {0 0ns}
add_force {/CPU/reset} -radix hex {1 0ns} -cancel_after 1ns
add_force {/CPU/clk} -radix hex {1 0ns} {0 50ps} -repeat_every 100ps
run 2 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'CPU'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'D:/Programs/Xilinx/Vivado/2022.2/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'CPU' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj CPU_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Adder.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Adder
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Constant.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Constant15
INFO: [VRFC 10-311] analyzing module Constant4
INFO: [VRFC 10-311] analyzing module Constant0
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Decoder_4to16.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Decoder_4to16
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Extender.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Extender
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Instruction_memory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module IMem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Memory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module DMem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Mux_16to1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Mux_16to1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Mux_2to1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Mux_2to1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Pipeline.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module DP_IF
INFO: [VRFC 10-311] analyzing module DP_ID
INFO: [VRFC 10-311] analyzing module DP_EX
INFO: [VRFC 10-311] analyzing module DP_MEM
INFO: [VRFC 10-311] analyzing module DP_WB
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Register_file.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register_file
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Register_sync_rw.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register_sync_rw
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/CPU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CPU
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot CPU_behav xil_defaultlib.CPU xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.2.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: D:/Programs/Xilinx/Vivado/2022.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot CPU_behav xil_defaultlib.CPU xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 15 differs from formal bit length 16 for port 'OUT' [D:/Workspaces/ODTU/EE446/EXP4/Register_file.v:19]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4100] "D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.Controller
Compiling module xil_defaultlib.Constant0
Compiling module xil_defaultlib.IMem(BYTE_SIZE=4,ADDR_WIDTH=32)
Compiling module xil_defaultlib.Adder(WIDTH=32)
Compiling module xil_defaultlib.Constant4
Compiling module xil_defaultlib.DP_WB
Compiling module xil_defaultlib.Extender
Compiling module xil_defaultlib.Mux_2to1(WIDTH=32)
Compiling module xil_defaultlib.ALU(WIDTH=32)
Compiling module xil_defaultlib.DMem(BYTE_SIZE=4,ADDR_WIDTH=32)
Compiling module xil_defaultlib.DP_IF
Compiling module xil_defaultlib.Constant15
Compiling module xil_defaultlib.DP_ID
Compiling module xil_defaultlib.DP_EX
Compiling module xil_defaultlib.DP_MEM
Compiling module xil_defaultlib.Mux_2to1(WIDTH=4)
Compiling module xil_defaultlib.Register_sync_rw(WIDTH=32)
Compiling module xil_defaultlib.Decoder_4to16
Compiling module xil_defaultlib.Mux_16to1
Compiling module xil_defaultlib.Register_file(WIDTH=32)
Compiling module xil_defaultlib.Datapath
Compiling module xil_defaultlib.CPU
Compiling module xil_defaultlib.glbl
Built simulation snapshot CPU_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "CPU_behav -key {Behavioral:sim_1:Functional:CPU} -tclbatch {CPU.tcl} -view {D:/Workspaces/Verilog/Pipelined/CPU_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
open_wave_config D:/Workspaces/Verilog/Pipelined/CPU_behav.wcfg
source CPU.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
WARNING: File mem_data.txt referenced on D:/Workspaces/ODTU/EE446/EXP4/Constant.v at line 21 cannot be opened for reading. Please ensure that this file is available in the current working directory.
WARNING: File mem_data.txt referenced on D:/Workspaces/ODTU/EE446/EXP4/Constant.v at line 21 cannot be opened for reading. Please ensure that this file is available in the current working directory.
INFO: [USF-XSim-96] XSim completed. Design snapshot 'CPU_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1272.371 ; gain = 0.000
add_force {/CPU/reset} -radix hex {0 0ns}
add_force {/CPU/reset} -radix hex {1 0ns} -cancel_after 1ns
add_force {/CPU/clk} -radix hex {1 0ns} {0 50ps} -repeat_every 100ps
run 2 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'CPU'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'D:/Programs/Xilinx/Vivado/2022.2/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'CPU' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj CPU_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/ALU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Adder.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Adder
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Constant.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Constant15
INFO: [VRFC 10-311] analyzing module Constant4
INFO: [VRFC 10-311] analyzing module Constant0
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Controller
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Decoder_4to16.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Decoder_4to16
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Extender.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Extender
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Instruction_memory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module IMem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Memory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module DMem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Mux_16to1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Mux_16to1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Mux_2to1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Mux_2to1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Pipeline.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module DP_IF
INFO: [VRFC 10-311] analyzing module DP_ID
INFO: [VRFC 10-311] analyzing module DP_EX
INFO: [VRFC 10-311] analyzing module DP_MEM
INFO: [VRFC 10-311] analyzing module DP_WB
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Register_file.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register_file
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/Register_sync_rw.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Register_sync_rw
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Workspaces/ODTU/EE446/EXP4/CPU.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CPU
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot CPU_behav xil_defaultlib.CPU xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.2.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: D:/Programs/Xilinx/Vivado/2022.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot CPU_behav xil_defaultlib.CPU xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 15 differs from formal bit length 16 for port 'OUT' [D:/Workspaces/ODTU/EE446/EXP4/Register_file.v:19]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4100] "D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.Controller
Compiling module xil_defaultlib.Constant0
Compiling module xil_defaultlib.IMem(BYTE_SIZE=4,ADDR_WIDTH=32)
Compiling module xil_defaultlib.Adder(WIDTH=32)
Compiling module xil_defaultlib.Constant4
Compiling module xil_defaultlib.DP_WB
Compiling module xil_defaultlib.Extender
Compiling module xil_defaultlib.Mux_2to1(WIDTH=32)
Compiling module xil_defaultlib.ALU(WIDTH=32)
Compiling module xil_defaultlib.DMem(BYTE_SIZE=4,ADDR_WIDTH=32)
Compiling module xil_defaultlib.DP_IF
Compiling module xil_defaultlib.Constant15
Compiling module xil_defaultlib.DP_ID
Compiling module xil_defaultlib.DP_EX
Compiling module xil_defaultlib.DP_MEM
Compiling module xil_defaultlib.Mux_2to1(WIDTH=4)
Compiling module xil_defaultlib.Register_sync_rw(WIDTH=32)
Compiling module xil_defaultlib.Decoder_4to16
Compiling module xil_defaultlib.Mux_16to1
Compiling module xil_defaultlib.Register_file(WIDTH=32)
Compiling module xil_defaultlib.Datapath
Compiling module xil_defaultlib.CPU
Compiling module xil_defaultlib.glbl
Built simulation snapshot CPU_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Workspaces/Verilog/Pipelined/Pipelined.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "CPU_behav -key {Behavioral:sim_1:Functional:CPU} -tclbatch {CPU.tcl} -view {D:/Workspaces/Verilog/Pipelined/CPU_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
open_wave_config D:/Workspaces/Verilog/Pipelined/CPU_behav.wcfg
source CPU.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
WARNING: File mem_data.txt referenced on D:/Workspaces/ODTU/EE446/EXP4/Constant.v at line 21 cannot be opened for reading. Please ensure that this file is available in the current working directory.
WARNING: File mem_data.txt referenced on D:/Workspaces/ODTU/EE446/EXP4/Constant.v at line 21 cannot be opened for reading. Please ensure that this file is available in the current working directory.
INFO: [USF-XSim-96] XSim completed. Design snapshot 'CPU_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1276.496 ; gain = 3.613