Pinned Loading

1. RTL-to-GDSII RTL-to-GDSII Public

   Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout generation

   C++ 6

2. sev_seg_FPGA sev_seg_FPGA Public

   its a seven segment display controller in FPGA which counts in ascending order

   JavaScript

3. Enc_Dec_Xor Enc_Dec_Xor Public

   8:3 Encoder is used as input and 3:8 decoder is used as output, to verify that the input and output data are same a Xor gate is implemented, it will return 1 if any mismatch in the input and output…

   Verilog

4. WIFI_CAR WIFI_CAR Public

   A code to operate a battery operated car over wifi control

   C++