diff --git a/doc/nrf/app_dev/device_guides/nrf54l/building_nrf54l.rst b/doc/nrf/app_dev/device_guides/nrf54l/building_nrf54l.rst new file mode 100644 index 000000000000..6fce0113d254 --- /dev/null +++ b/doc/nrf/app_dev/device_guides/nrf54l/building_nrf54l.rst @@ -0,0 +1,129 @@ +.. _building_nrf54l: + +Building and programming with nRF54L15 DK +######################################### + +.. contents:: + :local: + :depth: 2 + +This guide provides instructions on how to build and program the nRF54L15 development kit. +Whether you are working with single or multi-image builds, the following sections will guide you through the necessary steps. + +Depending on the sample, you must program only the application core or both the Fast Lightweight Peripheral Processor (FLPR) and the application core. +Additionally, the process will differ based on whether you are working with a single-image or multi-image build. + +Building for the application core +********************************* + +For instructions on building for the application core only, see how to :ref:`program an application `. + +Building for the application and FLPR core +****************************************** + +This section outlines how to build and program for both the application and FLPR core, covering separate builds and sysbuild configurations. +FLPR core supports two variants: + +* ``nrf54l15dk/nrf54l15/cpuflpr`` where FLPR runs from SRAM (recommended). + To build FLPR image with this variant, the application core image must include the ``nordic-flpr`` snippet. + +* ``nrf54l15dk/nrf54l15/cpuflpr/xip`` where FLPR runs from RRAM. + To build FLPR image with this variant, the application core image must include the ``nordic-flpr-xip`` snippet. + +Separate images +--------------- + +To build and program the application sample and the FLPR sample as separate images, follow these steps: + +.. tabs:: + + .. group-tab:: west + + 1. |open_terminal_window_with_environment| + #. Build the application core image, and based on your build target include the appropriate snippet: + + .. code-block:: console + + west build -p -b nrf54l15dk/nrf54l15/cpuapp -S nordic-flpr --no-sysbuild + + #. Flash the application core image by running the following command: + + .. code-block:: console + + west flash + + #. Build the FLPR core image: + + .. code-block:: console + + west build -p -b nrf54l15dk/nrf54l15/cpuflpr --no-sysbuild + + #. Once you have sucessfully built the FLPR core image, flash it onto your device: + + .. code-block:: console + + west flash + + .. group-tab:: nRF Util + + 1. |open_terminal_window_with_environment| + #. For the FLPR core, run the following command to erase the flash memory of the FLPR core and program the sample: + + .. Commands TBD + + .. code-block:: console + + nrfutil device program --firmware zephyr.hex --options chip_erase_mode=ERASE_ALL --core Network + + #. For the application core, navigate to its build folder and run: + + .. code-block:: console + + nrfutil device program --firmware zephyr.hex --options chip_erase_mode=ERASE_ALL + + .. note:: + The application build folder will be in a sub-directory which is the name of the folder of the application + + #. Reset the development kit: + + .. Commands TBD + + .. code-block:: console + + nrfutil device reset --reset-kind=RESET_PIN + + See :ref:`readback_protection_error` if you encounter an error. + +With sysbuild +------------- + +To build and program with sysbuild, complete the following steps: + +.. tabs:: + + .. group-tab:: Using VPR Launcher + + When using the VPR Launcher, the default configuration is employed for building with sysbuild targeting FLPR devices. + This process involves creating a minimal image that will be flashed onto the application core. + The primary function of this image is to transfer the FLPR code to the designated region (if necessary) and initiate the FLPR core. + + To build and flash both images, run the following command: + + .. code-block:: console + + west build -p -b nrf54l15dk/nrf54l15/cpuflpr + west flash + + .. group-tab:: Using application that aupports multi-image builds + + If your application involves creating custom images for both the application core and the FLPR core, make sure to disable the VPR Launcher. + You can do this by disabling the ``SB_CONFIG_VPR_LAUNCHER=n`` option when building for the FLPR target. + + In case your application creates custom images for both application core and FLPR core, make sure to disable VPR lanucher with `SB_CONFIG_VPR_LAUNCHER` when building for FLPR target. + + To build and flash both images, run the following command: + + .. code-block:: console + + west build -p -b nrf54l15dk/nrf54l15/cpuflpr + west flash diff --git a/doc/nrf/app_dev/device_guides/nrf54l/index.rst b/doc/nrf/app_dev/device_guides/nrf54l/index.rst index 4d419876b208..2dc02276d0ad 100644 --- a/doc/nrf/app_dev/device_guides/nrf54l/index.rst +++ b/doc/nrf/app_dev/device_guides/nrf54l/index.rst @@ -36,4 +36,6 @@ Zephyr and the |NCS| provide support and contain board definitions for developin features testing_dfu + vpr_flpr + building_nrf54l peripheral_sensor_node_shield diff --git a/doc/nrf/app_dev/device_guides/nrf54l/vpr_flpr.rst b/doc/nrf/app_dev/device_guides/nrf54l/vpr_flpr.rst new file mode 100644 index 000000000000..fd13a4beaa60 --- /dev/null +++ b/doc/nrf/app_dev/device_guides/nrf54l/vpr_flpr.rst @@ -0,0 +1,39 @@ +.. _vpr_flpr_nrf54l: + +Working with the FLPR core +########################## + +.. contents:: + :local: + :depth: 2 + +The nRF54L15 SoC has a dedicated VPR CPU (RISC-V architecture), named *fast lightweight peripheral processor* (FLPR). +The following peripherals are available for use with the FLPR core, and can be accessed through the appropriate Zephyr Device Driver API: + +* GPIO +* GPIOTE +* GRTC +* TWIM +* UARTE +* VPR + +Using FLPR with Zephyr multithreaded mode +***************************************** + +FLPR can function as a generic core, operating under the full Zephyr kernel. +In this configuration, building the FLPR target is similar the application core. +However, the application core build must incorporate an overlay that enables the FLPR coprocessor. +This ensures that the necessary code to initiate FLPR is integrated. + +Using FLPR with Zephyr threadless mode +************************************** + +FLPR is optimized for implementing software-defined peripherals (SDP). +For more information, see documentation page. + +Memory allocation +***************** + +If a FLPR CPU is running, it can lead to increased latency when accessing ``RAM_01``. +Because of this, when FLPR is used in a project, you should utilize ``RAM_01`` to store only the FLPR code, FLPR data, and the application CPU's non-time-sensitive information. +Conversely, you should use ``RAM_00`` to store data with strict access time requirements such as DMA buffers, and the application CPU data used in low-latency ISRs.