From b524b0e61990b415fe3b011611d031b28c29d279 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Stasiak?= Date: Wed, 13 Nov 2024 10:51:09 +0100 Subject: [PATCH] [nrf fromlist] drivers: pwm: nrfx: add pin retention MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add pin retenion if GPD is enabled for nRF54H20. Upstream PR #: 80672 Signed-off-by: MichaƂ Stasiak --- drivers/pwm/pwm_nrfx.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pwm/pwm_nrfx.c b/drivers/pwm/pwm_nrfx.c index 5161b299c3a..230a90d6cdf 100644 --- a/drivers/pwm/pwm_nrfx.c +++ b/drivers/pwm/pwm_nrfx.c @@ -13,6 +13,9 @@ #include #include #include +#ifdef CONFIG_SOC_NRF54H20_GPD +#include +#endif #include @@ -274,6 +277,10 @@ static void pwm_resume(const struct device *dev) (void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); +#ifdef CONFIG_SOC_NRF54H20_GPD + nrf_gpd_retain_pins_set(config->pcfg, false); +#endif + for (size_t i = 0; i < NRF_PWM_CHANNEL_COUNT; i++) { uint32_t psel; @@ -302,6 +309,10 @@ static void pwm_suspend(const struct device *dev) while (!nrfx_pwm_stopped_check(&config->pwm)) { } +#ifdef CONFIG_SOC_NRF54H20_GPD + nrf_gpd_retain_pins_set(config->pcfg, true); +#endif + memset(dev->data, 0, sizeof(struct pwm_nrfx_data)); (void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP); }