From 42fc53cb8562efe15ca44e70f1c3c02d40b72745 Mon Sep 17 00:00:00 2001 From: Jakub Zymelka Date: Wed, 13 Nov 2024 10:04:29 +0100 Subject: [PATCH 1/2] [nrf noup] drivers: pinctrl: Add SDP MSPI pin configuration Configure SDP MSPI pins to switch their control to VPR core Signed-off-by: Jakub Zymelka --- drivers/pinctrl/pinctrl_nrf.c | 32 +++++++++++++++++-- .../zephyr/dt-bindings/pinctrl/nrf-pinctrl.h | 22 +++++++++++++ modules/hal_nordic/nrfx/nrfe_config.h | 2 ++ 3 files changed, 54 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl_nrf.c b/drivers/pinctrl/pinctrl_nrf.c index 1e80de8fe67..15fcebc5f1d 100644 --- a/drivers/pinctrl/pinctrl_nrf.c +++ b/drivers/pinctrl/pinctrl_nrf.c @@ -94,6 +94,15 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = { #define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line #endif +#if defined(CONFIG_SOC_NRF54L15_CPUAPP) +#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) || defined(CONFIG_MSPI_NRFE) +#define NRF_PSEL_SDP_MSPI(reg, pin) \ + ((NRF_GPIO_Type *)reg)->PIN_CNF[pin] = \ + ((((NRF_GPIO_Type *)reg)->PIN_CNF[pin] & ~GPIO_PIN_CNF_CTRLSEL_Msk) | \ + (NRF_GPIO_PIN_SEL_VPR << GPIO_PIN_CNF_CTRLSEL_Pos)); +#endif +#endif + int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) { @@ -347,6 +356,25 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, input = NRF_GPIO_PIN_INPUT_CONNECT; break; #endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_can) */ +#if defined(CONFIG_SOC_NRF54L15_CPUAPP) +#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) + case NRF_FUN_SDP_MSPI_CS0: + case NRF_FUN_SDP_MSPI_CS1: + case NRF_FUN_SDP_MSPI_SCK: + case NRF_FUN_SDP_MSPI_DQ0: + case NRF_FUN_SDP_MSPI_DQ1: + case NRF_FUN_SDP_MSPI_DQ2: + case NRF_FUN_SDP_MSPI_DQ3: + case NRF_FUN_SDP_MSPI_DQ4: + case NRF_FUN_SDP_MSPI_DQ5: + case NRF_FUN_SDP_MSPI_DQ6: + case NRF_FUN_SDP_MSPI_DQ7: + NRF_PSEL_SDP_MSPI(reg, psel); + dir = NRF_GPIO_PIN_DIR_OUTPUT; + input = NRF_GPIO_PIN_INPUT_CONNECT; + break; +#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) */ +#endif /* CONFIG_SOC_NRF54L15_CPUAPP */ default: return -ENOTSUP; } @@ -380,8 +408,8 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, input = NRF_GPIO_PIN_INPUT_DISCONNECT; } - nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]), - drive, NRF_GPIO_PIN_NOSENSE); + nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]), drive, + NRF_GPIO_PIN_NOSENSE); #if NRF_GPIO_HAS_CLOCKPIN nrf_gpio_pin_clock_set(pin, NRF_GET_CLOCKPIN_ENABLE(pins[i])); #endif diff --git a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h index 4611baef95c..aab00563bbe 100644 --- a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h @@ -162,6 +162,28 @@ #define NRF_FUN_CAN_TX 46U /** CAN RX */ #define NRF_FUN_CAN_RX 47U +/** SDP_MSPI CK */ +#define NRF_FUN_SDP_MSPI_SCK 48U +/** SDP_MSPI DQ0 */ +#define NRF_FUN_SDP_MSPI_DQ0 49U +/** SDP_MSPI DQ1 */ +#define NRF_FUN_SDP_MSPI_DQ1 50U +/** SDP_MSPI DQ2 */ +#define NRF_FUN_SDP_MSPI_DQ2 51U +/** SDP_MSPI DQ3 */ +#define NRF_FUN_SDP_MSPI_DQ3 52U +/** SDP_MSPI DQ4 */ +#define NRF_FUN_SDP_MSPI_DQ4 53U +/** SDP_MSPI DQ5 */ +#define NRF_FUN_SDP_MSPI_DQ5 54U +/** SDP_MSPI DQ6 */ +#define NRF_FUN_SDP_MSPI_DQ6 55U +/** SDP_MSPI DQ7 */ +#define NRF_FUN_SDP_MSPI_DQ7 56U +/** SDP_MSPI CS0 */ +#define NRF_FUN_SDP_MSPI_CS0 57U +/** SDP_MSPI CS1 */ +#define NRF_FUN_SDP_MSPI_CS1 58U /** @} */ diff --git a/modules/hal_nordic/nrfx/nrfe_config.h b/modules/hal_nordic/nrfx/nrfe_config.h index c85d22a14a3..6373b3212d8 100644 --- a/modules/hal_nordic/nrfx/nrfe_config.h +++ b/modules/hal_nordic/nrfx/nrfe_config.h @@ -9,6 +9,8 @@ #ifdef CONFIG_GPIO_NRFE #include +#elif CONFIG_MSPI_NRFE +#include #else #error "NRFE config header included, even though no SW-define IO device is enabled." #endif From 6303428ce2216129b21f4e23926d4dd8a2d19875 Mon Sep 17 00:00:00 2001 From: Jakub Zymelka Date: Wed, 13 Nov 2024 10:05:17 +0100 Subject: [PATCH 2/2] [nrf noup] tests: drivers: mspi: add SDP MSPI testcase Add SDP MPSI testcase to basic API test. Signed-off-by: Jakub Zymelka --- .../boards/nrf54l15dk_nrf54l15_cpuapp.overlay | 24 +++++++++++++++++++ tests/drivers/mspi/api/src/main.c | 10 ++++++++ tests/drivers/mspi/api/testcase.yaml | 16 +++++++++++++ 3 files changed, 50 insertions(+) create mode 100644 tests/drivers/mspi/api/boards/nrf54l15dk_nrf54l15_cpuapp.overlay diff --git a/tests/drivers/mspi/api/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/tests/drivers/mspi/api/boards/nrf54l15dk_nrf54l15_cpuapp.overlay new file mode 100644 index 00000000000..0bc92a235bc --- /dev/null +++ b/tests/drivers/mspi/api/boards/nrf54l15dk_nrf54l15_cpuapp.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + + / { + aliases { + mspi0 = &sdp_mspi; + }; +}; + +&cpuflpr_vpr { + status = "okay"; + + sdp_mspi: sdp_mspi@5004c000 { + mspi_device: mspi_device@0 { + status = "okay"; + compatible = "zephyr,mspi-emul-device"; + reg = <0x0>; + mspi-max-frequency = <48000000>; + }; + }; +}; \ No newline at end of file diff --git a/tests/drivers/mspi/api/src/main.c b/tests/drivers/mspi/api/src/main.c index d6b632f29c1..7d5daa7bbbe 100644 --- a/tests/drivers/mspi/api/src/main.c +++ b/tests/drivers/mspi/api/src/main.c @@ -20,7 +20,11 @@ typedef struct mspi_ambiq_timing_cfg mspi_timing_cfg; typedef enum mspi_ambiq_timing_param mspi_timing_param; #endif +// #if defined(CONFIG_SOC_NRF54L15_CPUAPP) +// #define MSPI_BUS_NODE DT_NODELABEL(sdp_mspi) +// #else #define MSPI_BUS_NODE DT_ALIAS(mspi0) +// #endif static const struct device *mspi_devices[] = { DT_FOREACH_CHILD_STATUS_OKAY_SEP(MSPI_BUS_NODE, DEVICE_DT_GET, (,)) @@ -51,13 +55,17 @@ static struct mspi_dev_cfg device_cfg[] = { DT_FOREACH_CHILD_STATUS_OKAY_SEP(MSPI_BUS_NODE, MSPI_DEVICE_CONFIG_DT, (,)) }; +#if CONFIG_MSPI_XIP static struct mspi_xip_cfg xip_cfg[] = { DT_FOREACH_CHILD_STATUS_OKAY_SEP(MSPI_BUS_NODE, MSPI_XIP_CONFIG_DT, (,)) }; +#endif +#if CONFIG_MSPI_SCRAMBLE static struct mspi_scramble_cfg scramble_cfg[] = { DT_FOREACH_CHILD_STATUS_OKAY_SEP(MSPI_BUS_NODE, MSPI_SCRAMBLE_CONFIG_DT, (,)) }; +#endif ZTEST(mspi_api, test_mspi_api) { @@ -102,9 +110,11 @@ ZTEST(mspi_api, test_mspi_api) zassert_equal(ret, 0, "mspi_timing_config failed."); #endif +#if CONFIG_MSPI_ASYNC ret = mspi_register_callback(mspi_bus, &dev_id[dev_idx], MSPI_BUS_XFER_COMPLETE, NULL, NULL); zassert_equal(ret, 0, "mspi_register_callback failed."); +#endif ret = mspi_get_channel_status(mspi_bus, 0); zassert_equal(ret, 0, "mspi_get_channel_status failed."); diff --git a/tests/drivers/mspi/api/testcase.yaml b/tests/drivers/mspi/api/testcase.yaml index 3675cc485f3..730f6f61438 100644 --- a/tests/drivers/mspi/api/testcase.yaml +++ b/tests/drivers/mspi/api/testcase.yaml @@ -15,3 +15,19 @@ tests: - apollo3p_evb integration_platforms: - native_sim + + drivers.mspi.api.emspi: + tags: + - drivers + - mspi + - api + harness: ztest + platform_allow: + - nrf54l15dk_nrf54l15_cpuapp + integration_platforms: + - nrf54l15dk_nrf54l15_cpuapp + extra_args: + - SB_CONFIG_VPR_LAUNCHER=n + - SB_CONFIG_PARTITION_MANAGER=n + - SB_CONFIG_SDP=y + - SB_CONFIG_SDP_MSPI=y