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Merge pull request #2769 from o1-labs/dw/implement-add-riscv32 o1vm CI #143: Commit 1992ca9 pushed by dannywillems
November 20, 2024 14:52 33m 5s master
master
November 20, 2024 14:52 33m 5s
Merge pull request #2768 from o1-labs/dw/interpret-rtype-import o1vm CI #142: Commit c58cd7f pushed by dannywillems
November 20, 2024 13:56 32m 57s master
master
November 20, 2024 13:56 32m 57s
o1vm/riscv32: introduce tests checking the number of instructions o1vm CI #141: Pull request #2789 opened by dannywillems
November 20, 2024 13:53 33m 35s dw/o1vm/riscv32-nb-of-instr
dw/o1vm/riscv32-nb-of-instr
November 20, 2024 13:53 33m 35s
o1vm/mips: move regtest reg. number of selectors into MIPS directory o1vm CI #140: Pull request #2788 opened by dannywillems
November 20, 2024 13:44 32m 52s dw/pickles-mips-selectors-move-tests
dw/pickles-mips-selectors-move-tests
November 20, 2024 13:44 32m 52s
Merge pull request #2767 from o1-labs/dw/o1vm/remove-debugging-commen… o1vm CI #139: Commit 203e376 pushed by dannywillems
November 20, 2024 13:43 33m 14s master
master
November 20, 2024 13:43 33m 14s
o1vm/riscv32: sketch interpretation of mtype instruction o1vm CI #138: Pull request #2787 synchronize by dannywillems
November 20, 2024 13:43 33m 24s dw/expand-m-type-instruction-interpret
dw/expand-m-type-instruction-interpret
November 20, 2024 13:43 33m 24s
o1vm/riscv32: add fibonacci-7 test, and ignore it for now o1vm CI #137: Pull request #2786 synchronize by dannywillems
November 20, 2024 13:42 33m 6s dw/add-fibonacci-7-and-ignore-for-now
dw/add-fibonacci-7-and-ignore-for-now
November 20, 2024 13:42 33m 6s
o1vm/riscv32: sketch interpretation of mtype instruction o1vm CI #136: Pull request #2787 opened by dannywillems
November 20, 2024 13:34 32m 57s dw/expand-m-type-instruction-interpret
dw/expand-m-type-instruction-interpret
November 20, 2024 13:34 32m 57s
o1vm/riscv32: add fibonacci-7 test, and ignore it for now o1vm CI #135: Pull request #2786 opened by dannywillems
November 20, 2024 13:19 33m 3s dw/add-fibonacci-7-and-ignore-for-now
dw/add-fibonacci-7-and-ignore-for-now
November 20, 2024 13:19 33m 3s
o1vm/riscv32: expand missing instructions for itype o1vm CI #134: Pull request #2785 opened by dannywillems
November 20, 2024 13:07 33m 9s dw/itype-expand-missing-instruction
dw/itype-expand-missing-instruction
November 20, 2024 13:07 33m 9s
o1vm/riscv32: sketch implementation of UJ-type instr interpretation o1vm CI #133: Pull request #2784 synchronize by dannywillems
November 20, 2024 13:01 33m 9s dw/sketch-uj-type-interpret
dw/sketch-uj-type-interpret
November 20, 2024 13:01 33m 9s
o1vm/riscv32: sketch implementation of UJ-type instr interpretation o1vm CI #132: Pull request #2784 opened by dannywillems
November 20, 2024 13:00 33m 4s dw/sketch-uj-type-interpret
dw/sketch-uj-type-interpret
November 20, 2024 13:00 33m 4s
o1vm/riscv32: sketch implementation of U-type instr interpretation o1vm CI #131: Pull request #2783 synchronize by dannywillems
November 20, 2024 12:55 33m 30s dw/sketch-u-type-interpret
dw/sketch-u-type-interpret
November 20, 2024 12:55 33m 30s
o1vm/riscv32: sketch implementation of U-type instr interpretation o1vm CI #130: Pull request #2783 opened by dannywillems
November 20, 2024 12:55 33m 15s dw/sketch-u-type-interpret
dw/sketch-u-type-interpret
November 20, 2024 12:55 33m 15s
Merge pull request #2766 from o1-labs/dw/o1vm/add-is-prime-naive-bina… o1vm CI #129: Commit 5057235 pushed by dannywillems
November 20, 2024 12:50 32m 49s master
master
November 20, 2024 12:50 32m 49s
o1vm/riscv32: sketch implementation of SB-type instr interpretation o1vm CI #128: Pull request #2782 synchronize by dannywillems
November 20, 2024 12:50 33m 36s dw/sketch-sb-type-interpret
dw/sketch-sb-type-interpret
November 20, 2024 12:50 33m 36s
o1vm/riscv32: sketch implementation of SB-type instr interpretation o1vm CI #127: Pull request #2782 opened by dannywillems
November 20, 2024 12:49 33m 42s dw/sketch-sb-type-interpret
dw/sketch-sb-type-interpret
November 20, 2024 12:49 33m 42s
Merge pull request #2765 from o1-labs/dw/o1vm/rename-resources-directory o1vm CI #126: Commit 25c2e8d pushed by dannywillems
November 20, 2024 12:33 33m 4s master
master
November 20, 2024 12:33 33m 4s
o1vm/riscv32: continue instruction doc + add credits o1vm CI #125: Pull request #2781 opened by dannywillems
November 20, 2024 12:31 32m 47s dw/o1vm-riscv32-doc-and-credit
dw/o1vm-riscv32-doc-and-credit
November 20, 2024 12:31 32m 47s
o1vm/riscv32: sketch implementation of S-type instr interpretation o1vm CI #124: Pull request #2780 opened by dannywillems
November 20, 2024 12:02 32m 56s dw/sketch-implement-stype
dw/sketch-implement-stype
November 20, 2024 12:02 32m 56s
o1vm/riscv32: add link for documentation + add missing constraint reg instruction decomposition o1vm CI #123: Pull request #2779 opened by dannywillems
November 20, 2024 11:53 33m 11s dw/implement-itype-iterpret-doc
dw/implement-itype-iterpret-doc
November 20, 2024 11:53 33m 11s
o1vm/riscv32: implement R type instruction and o1vm CI #122: Pull request #2778 opened by dannywillems
November 20, 2024 11:48 33m 5s dw/implement-and-riscv32
dw/implement-and-riscv32
November 20, 2024 11:48 33m 5s
o1vm/riscv32: implement R type instruction or o1vm CI #121: Pull request #2777 opened by dannywillems
November 20, 2024 11:46 33m 30s dw/implement-or-riscv32
dw/implement-or-riscv32
November 20, 2024 11:46 33m 30s
o1vm/riscv32: implement R type instruction sra o1vm CI #120: Pull request #2776 opened by dannywillems
November 20, 2024 11:44 33m 6s dw/implement-sra-riscv32
dw/implement-sra-riscv32
November 20, 2024 11:44 33m 6s
o1vm/riscv32: implement R type instruction srl o1vm CI #119: Pull request #2775 opened by dannywillems
November 20, 2024 11:42 33m 6s dw/implement-srl-riscv32
dw/implement-srl-riscv32
November 20, 2024 11:42 33m 6s
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