From 07e58b6c67a1ce97fcbb84f7d74041b8db2f8897 Mon Sep 17 00:00:00 2001 From: Sai Vegasena Date: Wed, 20 Nov 2024 12:43:42 +0100 Subject: [PATCH] o1vm/riscv32: implement R type instruction sra Co-authored-by: Danny Willems --- o1vm/src/interpreters/riscv32im/interpreter.rs | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 9f1f479be2..cc26fab9f3 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -1377,7 +1377,17 @@ pub fn interpret_rtype(env: &mut Env, instr: RInstruction) env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32)); } RInstruction::ShiftRightArithmetic => { - unimplemented!("ShiftRightArithmetic"); + /* sra: x[rd] = x[rs1] >> x[rs2] */ + let local_rs1 = env.read_register(&rs1); + let local_rs2 = env.read_register(&rs2); + let local_rd = unsafe { + let pos = env.alloc_scratch(); + env.shift_right_arithmetic(&local_rs1, &local_rs2, pos) + }; + env.write_register(&rd, local_rd); + + env.set_instruction_pointer(next_instruction_pointer.clone()); + env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32)); } RInstruction::Or => { unimplemented!("Or")