From f518c8d6aa280f7f30ad7755e32f2fa7be02a23e Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 25 Nov 2024 16:01:32 +0100 Subject: [PATCH] o1vm/riscv32im: test decoding remu --- o1vm/src/interpreters/riscv32im/tests.rs | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/o1vm/src/interpreters/riscv32im/tests.rs b/o1vm/src/interpreters/riscv32im/tests.rs index 548f96ca56..4c2305f825 100644 --- a/o1vm/src/interpreters/riscv32im/tests.rs +++ b/o1vm/src/interpreters/riscv32im/tests.rs @@ -411,6 +411,29 @@ pub fn generate_random_rem_instruction(rng: &mut RNG) ] } +pub fn generate_random_remu_instruction(rng: &mut RNG) -> [u8; 4] { + let opcode = 0b0110011; + let rd = rng.gen_range(0..32); + let funct3 = 0b111; + let rs1 = rng.gen_range(0..32); + let rs2 = rng.gen_range(0..32); + let funct2 = 0b01; + let funct5 = 0b00000; + let instruction = opcode + | (rd << 7) + | (funct3 << 12) + | (rs1 << 15) + | (rs2 << 20) + | (funct2 << 25) + | (funct5 << 27); + [ + instruction as u8, + (instruction >> 8) as u8, + (instruction >> 16) as u8, + (instruction >> 24) as u8, + ] +} + #[test] pub fn test_instruction_decoding_add() { let mut env: Env = dummy_env(); @@ -637,3 +660,16 @@ pub fn test_instruction_decoding_rem() { let (opcode, _instruction) = env.decode_instruction(); assert_eq!(opcode, Instruction::MType(MInstruction::Rem)); } + +#[test] +pub fn test_instruction_decoding_remu() { + let mut env: Env = dummy_env(); + let mut rng = o1_utils::tests::make_test_rng(None); + let instruction = generate_random_remu_instruction(&mut rng); + env.memory[0].1[0] = instruction[0]; + env.memory[0].1[1] = instruction[1]; + env.memory[0].1[2] = instruction[2]; + env.memory[0].1[3] = instruction[3]; + let (opcode, _instruction) = env.decode_instruction(); + assert_eq!(opcode, Instruction::MType(MInstruction::Remu)); +}