From aab22df80355abeef058bda6b76276b49cf2ab50 Mon Sep 17 00:00:00 2001
From: Danny Willems <be.danny.willems@gmail.com>
Date: Mon, 23 Dec 2024 15:45:54 +0100
Subject: [PATCH 1/2] o1vm/riscv32im: add one test for addi with negative
 values only

---
 .../programs/riscv32im/bin/addi_negative        | Bin 456 -> 464 bytes
 .../programs/riscv32im/src/addi_negative.S      |   3 +++
 o1vm/tests/test_riscv_elf.rs                    |   1 +
 3 files changed, 4 insertions(+)

diff --git a/o1vm/resources/programs/riscv32im/bin/addi_negative b/o1vm/resources/programs/riscv32im/bin/addi_negative
index f610f7df86b0c65ba290b0ec29a2b2bf9aab3055..5d3eca47c23f70baa3e0637bc42f8f15ed60a395 100755
GIT binary patch
delta 74
zcmX@Xe1Um_0;9o1MRCS86D_q>)-W(IfG{f%GYBv+OlERm6K;O=XEO8QpTc|%2PgBL
cdoZ!#38Tg2R7PdSHIq9T)fu@bZ)6k)01f~aaR2}S

delta 85
zcmcb>e1ds`0;9%6MRCR@6D_r6mM}0dfG{f%GYBv+OlERm6K;O=XEO8QpA$QtFd9tG
aWmINdGI=7Sx&$*L1A{V19TWh$U;qG<SP^&t

diff --git a/o1vm/resources/programs/riscv32im/src/addi_negative.S b/o1vm/resources/programs/riscv32im/src/addi_negative.S
index 5ef1bfda36..1b94dfb420 100644
--- a/o1vm/resources/programs/riscv32im/src/addi_negative.S
+++ b/o1vm/resources/programs/riscv32im/src/addi_negative.S
@@ -10,6 +10,9 @@ _start:
     # Subtract 100 using addi (addi with negative immediate)
     addi t2, t1, -100     # t2 = t1 + (-100) (Expected: t2 = -50)
 
+    li t3, -1000          # t3 = -1000
+    addi t4, t3, -500     # t4 = t0 + (-500) (Expected: t4 = -1500)
+
     # Custom exit syscall
     li a0, 0
     li a1, 0
diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs
index 077b634270..09a0b068dd 100644
--- a/o1vm/tests/test_riscv_elf.rs
+++ b/o1vm/tests/test_riscv_elf.rs
@@ -195,6 +195,7 @@ fn test_addi_negative() {
     assert_eq!(witness.registers[T0], 100);
     assert_eq!(witness.registers[T1], 50);
     assert_eq!(witness.registers[T2], (-50_i32) as u32);
+    assert_eq!(witness.registers[T4], (-1500_i32) as u32);
 }
 
 #[test]

From 2c55e6ba2a31c62e6e6f4c2edabd2134550be340 Mon Sep 17 00:00:00 2001
From: Danny Willems <be.danny.willems@gmail.com>
Date: Mon, 23 Dec 2024 19:29:29 +0100
Subject: [PATCH 2/2] o1vm/riscv32im: check T3 register state for addi

---
 o1vm/tests/test_riscv_elf.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs
index 09a0b068dd..8c65ba25fb 100644
--- a/o1vm/tests/test_riscv_elf.rs
+++ b/o1vm/tests/test_riscv_elf.rs
@@ -195,6 +195,7 @@ fn test_addi_negative() {
     assert_eq!(witness.registers[T0], 100);
     assert_eq!(witness.registers[T1], 50);
     assert_eq!(witness.registers[T2], (-50_i32) as u32);
+    assert_eq!(witness.registers[T3], (-1000_i32) as u32);
     assert_eq!(witness.registers[T4], (-1500_i32) as u32);
 }