From 49235d338ff233dc29a2809b0d179f603b657301 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 18:46:20 +0100 Subject: [PATCH] Run make build-mips-programs --- o1vm/resources/programs/mips/bin/add | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/addi | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/addiu | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/addu | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/and | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/andi | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/beq | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/bgez | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/bgtz | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/blez | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/bltz | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/bne | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/brk | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/clo | Bin 0 -> 668 bytes o1vm/resources/programs/mips/bin/clone | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/clz | Bin 0 -> 668 bytes o1vm/resources/programs/mips/bin/div | Bin 0 -> 668 bytes o1vm/resources/programs/mips/bin/divu | Bin 0 -> 636 bytes o1vm/resources/programs/mips/bin/exit_group | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/fcntl | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/j | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/jal | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/jalr | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/jr | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/lb | Bin 0 -> 780 bytes o1vm/resources/programs/mips/bin/lbu | Bin 0 -> 652 bytes o1vm/resources/programs/mips/bin/lh | Bin 0 -> 684 bytes o1vm/resources/programs/mips/bin/lhu | Bin 0 -> 668 bytes o1vm/resources/programs/mips/bin/lui | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/lw | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/lwl | Bin 0 -> 700 bytes o1vm/resources/programs/mips/bin/lwr | Bin 0 -> 700 bytes o1vm/resources/programs/mips/bin/mfthi | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/mftlo | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/mmap | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/movn | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/movz | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/mul | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/mult | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/multu | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/nor | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/oracle | Bin 0 -> 860 bytes o1vm/resources/programs/mips/bin/oracle_kzg | Bin 0 -> 828 bytes .../programs/mips/bin/oracle_unaligned_read | Bin 0 -> 956 bytes .../programs/mips/bin/oracle_unaligned_write | Bin 0 -> 924 bytes o1vm/resources/programs/mips/bin/ori | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/sb | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/sh | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/sll | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/sllv | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/slt | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/slti | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/sltiu | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/sltu | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/sra | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/srav | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/srl | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/srlv | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/sub | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/subu | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/swl | Bin 0 -> 716 bytes o1vm/resources/programs/mips/bin/swr | Bin 0 -> 716 bytes o1vm/resources/programs/mips/bin/xor | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/xori | Bin 0 -> 588 bytes o1vm/resources/programs/mips/src/add.asm | 38 +++++ o1vm/resources/programs/mips/src/addi.asm | 38 +++++ o1vm/resources/programs/mips/src/addiu.asm | 38 +++++ o1vm/resources/programs/mips/src/addu.asm | 38 +++++ o1vm/resources/programs/mips/src/and.asm | 42 ++++++ o1vm/resources/programs/mips/src/andi.asm | 37 +++++ o1vm/resources/programs/mips/src/beq.asm | 50 +++++++ o1vm/resources/programs/mips/src/bgez.asm | 48 +++++++ o1vm/resources/programs/mips/src/bgtz.asm | 49 +++++++ o1vm/resources/programs/mips/src/blez.asm | 48 +++++++ o1vm/resources/programs/mips/src/bltz.asm | 50 +++++++ o1vm/resources/programs/mips/src/bne.asm | 50 +++++++ o1vm/resources/programs/mips/src/brk.asm | 22 +++ o1vm/resources/programs/mips/src/clo.asm | 59 ++++++++ o1vm/resources/programs/mips/src/clone.asm | 22 +++ o1vm/resources/programs/mips/src/clz.asm | 58 ++++++++ o1vm/resources/programs/mips/src/div.asm | 49 +++++++ o1vm/resources/programs/mips/src/divu.asm | 49 +++++++ .../programs/mips/src/exit_group.asm | 25 ++++ o1vm/resources/programs/mips/src/fcntl.asm | 23 +++ o1vm/resources/programs/mips/src/j.asm | 41 ++++++ o1vm/resources/programs/mips/src/jal.asm | 43 ++++++ o1vm/resources/programs/mips/src/jalr.asm | 44 ++++++ o1vm/resources/programs/mips/src/jr.asm | 42 ++++++ o1vm/resources/programs/mips/src/lb.asm | 112 +++++++++++++++ o1vm/resources/programs/mips/src/lbu.asm | 64 +++++++++ o1vm/resources/programs/mips/src/lh.asm | 80 +++++++++++ o1vm/resources/programs/mips/src/lhu.asm | 72 ++++++++++ o1vm/resources/programs/mips/src/lui.asm | 34 +++++ o1vm/resources/programs/mips/src/lw.asm | 39 +++++ o1vm/resources/programs/mips/src/lwl.asm | 78 ++++++++++ o1vm/resources/programs/mips/src/lwr.asm | 78 ++++++++++ o1vm/resources/programs/mips/src/mfthi.asm | 39 +++++ o1vm/resources/programs/mips/src/mftlo.asm | 39 +++++ o1vm/resources/programs/mips/src/mmap.asm | 24 ++++ o1vm/resources/programs/mips/src/movn.asm | 42 ++++++ o1vm/resources/programs/mips/src/movz.asm | 42 ++++++ o1vm/resources/programs/mips/src/mul.asm | 42 ++++++ o1vm/resources/programs/mips/src/mult.asm | 49 +++++++ o1vm/resources/programs/mips/src/multu.asm | 49 +++++++ o1vm/resources/programs/mips/src/nor.asm | 41 ++++++ o1vm/resources/programs/mips/src/oracle.asm | 102 ++++++++++++++ .../programs/mips/src/oracle_kzg.asm | 98 +++++++++++++ .../mips/src/oracle_unaligned_read.asm | 133 ++++++++++++++++++ .../mips/src/oracle_unaligned_write.asm | 123 ++++++++++++++++ o1vm/resources/programs/mips/src/ori.asm | 34 +++++ o1vm/resources/programs/mips/src/sb.asm | 54 +++++++ o1vm/resources/programs/mips/src/sh.asm | 50 +++++++ o1vm/resources/programs/mips/src/sll.asm | 40 ++++++ o1vm/resources/programs/mips/src/sllv.asm | 41 ++++++ o1vm/resources/programs/mips/src/slt.asm | 36 +++++ o1vm/resources/programs/mips/src/slti.asm | 37 +++++ o1vm/resources/programs/mips/src/sltiu.asm | 37 +++++ o1vm/resources/programs/mips/src/sltu.asm | 36 +++++ o1vm/resources/programs/mips/src/sra.asm | 40 ++++++ o1vm/resources/programs/mips/src/srav.asm | 41 ++++++ o1vm/resources/programs/mips/src/srl.asm | 40 ++++++ o1vm/resources/programs/mips/src/srlv.asm | 41 ++++++ o1vm/resources/programs/mips/src/sub.asm | 40 ++++++ o1vm/resources/programs/mips/src/subu.asm | 42 ++++++ o1vm/resources/programs/mips/src/swl.asm | 81 +++++++++++ o1vm/resources/programs/mips/src/swr.asm | 81 +++++++++++ o1vm/resources/programs/mips/src/xor.asm | 43 ++++++ o1vm/resources/programs/mips/src/xori.asm | 38 +++++ 128 files changed, 3235 insertions(+) create mode 100755 o1vm/resources/programs/mips/bin/add create mode 100755 o1vm/resources/programs/mips/bin/addi create mode 100755 o1vm/resources/programs/mips/bin/addiu create mode 100755 o1vm/resources/programs/mips/bin/addu create mode 100755 o1vm/resources/programs/mips/bin/and create mode 100755 o1vm/resources/programs/mips/bin/andi create mode 100755 o1vm/resources/programs/mips/bin/beq create mode 100755 o1vm/resources/programs/mips/bin/bgez create mode 100755 o1vm/resources/programs/mips/bin/bgtz create mode 100755 o1vm/resources/programs/mips/bin/blez create mode 100755 o1vm/resources/programs/mips/bin/bltz create mode 100755 o1vm/resources/programs/mips/bin/bne create mode 100755 o1vm/resources/programs/mips/bin/brk create mode 100755 o1vm/resources/programs/mips/bin/clo create mode 100755 o1vm/resources/programs/mips/bin/clone create mode 100755 o1vm/resources/programs/mips/bin/clz create mode 100755 o1vm/resources/programs/mips/bin/div create mode 100755 o1vm/resources/programs/mips/bin/divu create mode 100755 o1vm/resources/programs/mips/bin/exit_group create mode 100755 o1vm/resources/programs/mips/bin/fcntl create mode 100755 o1vm/resources/programs/mips/bin/j create mode 100755 o1vm/resources/programs/mips/bin/jal create mode 100755 o1vm/resources/programs/mips/bin/jalr create mode 100755 o1vm/resources/programs/mips/bin/jr create mode 100755 o1vm/resources/programs/mips/bin/lb create mode 100755 o1vm/resources/programs/mips/bin/lbu create mode 100755 o1vm/resources/programs/mips/bin/lh create mode 100755 o1vm/resources/programs/mips/bin/lhu create mode 100755 o1vm/resources/programs/mips/bin/lui create mode 100755 o1vm/resources/programs/mips/bin/lw create mode 100755 o1vm/resources/programs/mips/bin/lwl create mode 100755 o1vm/resources/programs/mips/bin/lwr create mode 100755 o1vm/resources/programs/mips/bin/mfthi create mode 100755 o1vm/resources/programs/mips/bin/mftlo create mode 100755 o1vm/resources/programs/mips/bin/mmap create mode 100755 o1vm/resources/programs/mips/bin/movn create mode 100755 o1vm/resources/programs/mips/bin/movz create mode 100755 o1vm/resources/programs/mips/bin/mul create mode 100755 o1vm/resources/programs/mips/bin/mult create mode 100755 o1vm/resources/programs/mips/bin/multu create mode 100755 o1vm/resources/programs/mips/bin/nor create mode 100755 o1vm/resources/programs/mips/bin/oracle create mode 100755 o1vm/resources/programs/mips/bin/oracle_kzg create mode 100755 o1vm/resources/programs/mips/bin/oracle_unaligned_read create mode 100755 o1vm/resources/programs/mips/bin/oracle_unaligned_write create mode 100755 o1vm/resources/programs/mips/bin/ori create mode 100755 o1vm/resources/programs/mips/bin/sb create mode 100755 o1vm/resources/programs/mips/bin/sh create mode 100755 o1vm/resources/programs/mips/bin/sll create mode 100755 o1vm/resources/programs/mips/bin/sllv create mode 100755 o1vm/resources/programs/mips/bin/slt create mode 100755 o1vm/resources/programs/mips/bin/slti create mode 100755 o1vm/resources/programs/mips/bin/sltiu create mode 100755 o1vm/resources/programs/mips/bin/sltu create mode 100755 o1vm/resources/programs/mips/bin/sra create mode 100755 o1vm/resources/programs/mips/bin/srav create mode 100755 o1vm/resources/programs/mips/bin/srl create mode 100755 o1vm/resources/programs/mips/bin/srlv create mode 100755 o1vm/resources/programs/mips/bin/sub create mode 100755 o1vm/resources/programs/mips/bin/subu create mode 100755 o1vm/resources/programs/mips/bin/swl create mode 100755 o1vm/resources/programs/mips/bin/swr create mode 100755 o1vm/resources/programs/mips/bin/xor create mode 100755 o1vm/resources/programs/mips/bin/xori create mode 100644 o1vm/resources/programs/mips/src/add.asm create mode 100644 o1vm/resources/programs/mips/src/addi.asm create mode 100644 o1vm/resources/programs/mips/src/addiu.asm create mode 100644 o1vm/resources/programs/mips/src/addu.asm create mode 100644 o1vm/resources/programs/mips/src/and.asm create mode 100644 o1vm/resources/programs/mips/src/andi.asm create mode 100644 o1vm/resources/programs/mips/src/beq.asm create mode 100644 o1vm/resources/programs/mips/src/bgez.asm create mode 100644 o1vm/resources/programs/mips/src/bgtz.asm create mode 100644 o1vm/resources/programs/mips/src/blez.asm create mode 100644 o1vm/resources/programs/mips/src/bltz.asm create mode 100644 o1vm/resources/programs/mips/src/bne.asm create mode 100644 o1vm/resources/programs/mips/src/brk.asm create mode 100644 o1vm/resources/programs/mips/src/clo.asm create mode 100644 o1vm/resources/programs/mips/src/clone.asm create mode 100644 o1vm/resources/programs/mips/src/clz.asm create mode 100644 o1vm/resources/programs/mips/src/div.asm create mode 100644 o1vm/resources/programs/mips/src/divu.asm create mode 100644 o1vm/resources/programs/mips/src/exit_group.asm create mode 100644 o1vm/resources/programs/mips/src/fcntl.asm create mode 100644 o1vm/resources/programs/mips/src/j.asm create mode 100644 o1vm/resources/programs/mips/src/jal.asm create mode 100644 o1vm/resources/programs/mips/src/jalr.asm create mode 100644 o1vm/resources/programs/mips/src/jr.asm create mode 100644 o1vm/resources/programs/mips/src/lb.asm create mode 100644 o1vm/resources/programs/mips/src/lbu.asm create mode 100644 o1vm/resources/programs/mips/src/lh.asm create mode 100644 o1vm/resources/programs/mips/src/lhu.asm create mode 100644 o1vm/resources/programs/mips/src/lui.asm create mode 100644 o1vm/resources/programs/mips/src/lw.asm create mode 100644 o1vm/resources/programs/mips/src/lwl.asm create mode 100644 o1vm/resources/programs/mips/src/lwr.asm create mode 100644 o1vm/resources/programs/mips/src/mfthi.asm create mode 100644 o1vm/resources/programs/mips/src/mftlo.asm create mode 100644 o1vm/resources/programs/mips/src/mmap.asm create mode 100644 o1vm/resources/programs/mips/src/movn.asm create mode 100644 o1vm/resources/programs/mips/src/movz.asm create mode 100644 o1vm/resources/programs/mips/src/mul.asm create mode 100644 o1vm/resources/programs/mips/src/mult.asm create mode 100644 o1vm/resources/programs/mips/src/multu.asm create mode 100644 o1vm/resources/programs/mips/src/nor.asm create mode 100644 o1vm/resources/programs/mips/src/oracle.asm create mode 100644 o1vm/resources/programs/mips/src/oracle_kzg.asm create mode 100644 o1vm/resources/programs/mips/src/oracle_unaligned_read.asm create mode 100644 o1vm/resources/programs/mips/src/oracle_unaligned_write.asm create mode 100644 o1vm/resources/programs/mips/src/ori.asm create mode 100644 o1vm/resources/programs/mips/src/sb.asm create mode 100644 o1vm/resources/programs/mips/src/sh.asm create mode 100644 o1vm/resources/programs/mips/src/sll.asm create mode 100644 o1vm/resources/programs/mips/src/sllv.asm create mode 100644 o1vm/resources/programs/mips/src/slt.asm create mode 100644 o1vm/resources/programs/mips/src/slti.asm create mode 100644 o1vm/resources/programs/mips/src/sltiu.asm create mode 100644 o1vm/resources/programs/mips/src/sltu.asm create mode 100644 o1vm/resources/programs/mips/src/sra.asm create mode 100644 o1vm/resources/programs/mips/src/srav.asm create mode 100644 o1vm/resources/programs/mips/src/srl.asm create mode 100644 o1vm/resources/programs/mips/src/srlv.asm create mode 100644 o1vm/resources/programs/mips/src/sub.asm create mode 100644 o1vm/resources/programs/mips/src/subu.asm create mode 100644 o1vm/resources/programs/mips/src/swl.asm create mode 100644 o1vm/resources/programs/mips/src/swr.asm create mode 100644 o1vm/resources/programs/mips/src/xor.asm create mode 100644 o1vm/resources/programs/mips/src/xori.asm diff --git a/o1vm/resources/programs/mips/bin/add b/o1vm/resources/programs/mips/bin/add new file mode 100755 index 0000000000000000000000000000000000000000..05d80d6d90901e98d188397fea468ce225bbd61a GIT binary patch literal 588 zcma)3%}T>S7@SS|lj6bjCY}ObRB%sK5PE0@1woTW`r1WNsNVj}PsHf4Xe`tMcWjX&*0Y`;2f zsBUEKd1QY&ErhByNY1XHR{XzJ8?|s-{Aac2MW14SGFuk6HERkwf67f}(joNy?chPD z!|C`ro#fEjXfmCR=g?;KVxYOCQ)9B}aA`)l|K2}&kC~m)8x)yJwq<61UEW0UJ*2Ne z7T=mIkaJ&>jr2!^b8El-p?d>Alj9P<7%FPAr0Dp1%|fQVY5ixs&|`7lK+DnW=N)KHy*3V5fd z1hCIuP$44DrIwtR*q)20ys%3pfZ_!LRNaI!36%Ql#6;jVtjqp(_1-ppC;qT!vHff} zpgNJYr;+_`?x5Oi*`JdOs0IIT(Lg0!7yr50^P)$wHyqE4+v*hsoj>MgX3`A$_WJH# zr`c%mln!&~S${Yh4<^v2|7@VSq*G&Nqik;ax&Pijd6${B=naZYCEGGHzbW0>yhW5L)1HaX_KPMMZ3;y4tiF$2a{O4xRi5|t?XfiKuYt$8V{+OH0q$`iM z_Q%7gbd*D9gVA_0oI;zyvw`N4PL0XN{ka+B?tA~_U1rv%*DErWY|G5ty1a?xdq7`6 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+############################################################################### +# File : add.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'add' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff # A = 0xfffffffd (-3) + ori $t0, 0xfffd + ori $t1, $0, 0x3 # B = 0x3 + add $t2, $t0, $t1 # C = A + B = 0 + sltiu $v0, $t2, 1 # D = 1 if C == 0 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/addi.asm b/o1vm/resources/programs/mips/src/addi.asm new file mode 100644 index 0000000000..6981d134fd --- /dev/null +++ b/o1vm/resources/programs/mips/src/addi.asm @@ -0,0 +1,38 @@ +############################################################################### +# File : addi.asm +# Project : MIPS32 MUX +# Author : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'addi' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff # A = 0xfffffffd (-3) + ori $t0, 0xfffd + addi $t1, $t0, 5 # B = A + 5 = 2 + addi $t2, $t1, 0xfffe # C = B + -2 = 0 + sltiu $v0, $t2, 1 # D = 1 if C == 0 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/addiu.asm b/o1vm/resources/programs/mips/src/addiu.asm new file mode 100644 index 0000000000..116ce36145 --- /dev/null +++ b/o1vm/resources/programs/mips/src/addiu.asm @@ -0,0 +1,38 @@ +############################################################################### +# File : addiu.asm +# Project : MIPS32 MUX +# Author : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'addiu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff # A = 0xfffffffd (-3) + ori $t0, 0xfffd + addiu $t1, $t0, 5 # B = A + 5 = 2 + addiu $t2, $t1, 0xfffe # C = B + -2 = 0 + sltiu $v0, $t2, 1 # D = 1 if C == 0 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/addu.asm b/o1vm/resources/programs/mips/src/addu.asm new file mode 100644 index 0000000000..328143dbc6 --- /dev/null +++ b/o1vm/resources/programs/mips/src/addu.asm @@ -0,0 +1,38 @@ +############################################################################### +# File : addu.asm +# Project : MIPS32 MUX +# Author : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'addu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff # A = 0xfffffffd (-3) + ori $t0, 0xfffd + ori $t1, $0, 0x3 # B = 0x3 + addu $t2, $t0, $t1 # C = A + B = 0 + sltiu $v0, $t2, 1 # D = 1 if C == 0 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/and.asm b/o1vm/resources/programs/mips/src/and.asm new file mode 100644 index 0000000000..19d40b99cc --- /dev/null +++ b/o1vm/resources/programs/mips/src/and.asm @@ -0,0 +1,42 @@ +############################################################################### +# File : and.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'and' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + lui $t1, 0xaaaa # B = 0xaaaaaaaa + lui $t2, 0x5555 # C = 0x55555555 + ori $t0, 0xbeef + ori $t1, 0xaaaa + ori $t2, 0x5555 + and $t3, $t0, $t1 # D = A & B = 0x8aaaaaaa + and $t4, $t2, $t3 # E = B & D = 0 + sltiu $v0, $t4, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/andi.asm b/o1vm/resources/programs/mips/src/andi.asm new file mode 100644 index 0000000000..78939b5d45 --- /dev/null +++ b/o1vm/resources/programs/mips/src/andi.asm @@ -0,0 +1,37 @@ +############################################################################### +# File : andi.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'andi' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $t0, $0, 0xcafe # A = 0xcafe + andi $t1, $t0, 0xaaaa # B = A & 0xaaaa = 0x8aaa + andi $t2, $t1, 0x5555 # C = B & 0x5555 = 0 + sltiu $v0, $t2, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/beq.asm b/o1vm/resources/programs/mips/src/beq.asm new file mode 100644 index 0000000000..a0733b62c8 --- /dev/null +++ b/o1vm/resources/programs/mips/src/beq.asm @@ -0,0 +1,50 @@ +############################################################################### +# File : beq.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'beq' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $t0, $0, 0xcafe + ori $t1, $0, 0xcafe + ori $v0, $0, 0 # The test result starts as a failure + beq $t0, $v0, $finish # No branch + nop + beq $t0, $t1, $target + nop + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + +$done: + jr $ra + nop + j $finish # Early-by-1 branch detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + beq $0, $0, $finish # Late-by-1 branch detection (result not stored) + nop + j $finish + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/bgez.asm b/o1vm/resources/programs/mips/src/bgez.asm new file mode 100644 index 0000000000..be7d41eb1a --- /dev/null +++ b/o1vm/resources/programs/mips/src/bgez.asm @@ -0,0 +1,48 @@ +############################################################################### +# File : bgez.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'bgez' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff + bgez $t0, $finish # No branch + nop + bgez $s1, $target + nop + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + +$done: + jr $ra + nop + j $finish # Early-by-1 branch detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + bgez $0, $finish # Late-by-1 branch detection (result not stored) + nop + j $finish # Broken branch recovery + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/bgtz.asm b/o1vm/resources/programs/mips/src/bgtz.asm new file mode 100644 index 0000000000..27b0199b88 --- /dev/null +++ b/o1vm/resources/programs/mips/src/bgtz.asm @@ -0,0 +1,49 @@ +############################################################################### +# File : bgtz.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'bgtz' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $v0, $0, 0 # The test result starts as a failure + lui $t0, 0xffff + bgtz $t0, $finish # No branch + nop + bgtz $s1, $target + nop + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + +$done: + jr $ra + nop + j $finish # Early-by-1 branch detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + bgtz $s1, $finish # Late-by-1 branch detection (result not stored) + nop + j $finish # Broken branch recovery + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/blez.asm b/o1vm/resources/programs/mips/src/blez.asm new file mode 100644 index 0000000000..56c11338f7 --- /dev/null +++ b/o1vm/resources/programs/mips/src/blez.asm @@ -0,0 +1,48 @@ +############################################################################### +# File : blez.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'blez' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $v0, $0, 0 # The test result starts as a failure + blez $s1, $finish # No branch + lui $t0, 0xffff + blez $t0, $target + nop + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + +$done: + jr $ra + nop + j $finish # Early-by-1 branch detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + blez $0, $finish # Late-by-1 branch detection (result not stored) + nop + j $finish + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/bltz.asm b/o1vm/resources/programs/mips/src/bltz.asm new file mode 100644 index 0000000000..27264f7251 --- /dev/null +++ b/o1vm/resources/programs/mips/src/bltz.asm @@ -0,0 +1,50 @@ +############################################################################### +# File : bltz.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'bltz' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $v0, $0, 0 # The test result starts as a failure + bltz $0, $finish # No branch + nop + bltz $s1, $finish # No branch + lui $t0, 0xffff + bltz $t0, $target + nop + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + +$done: + jr $ra + nop + j $finish # Early-by-1 branch detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + bltz $t0, $finish # Late-by-1 branch detection (result not stored) + nop + j $finish # Broken branch recovery + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/bne.asm b/o1vm/resources/programs/mips/src/bne.asm new file mode 100644 index 0000000000..427ba8b941 --- /dev/null +++ b/o1vm/resources/programs/mips/src/bne.asm @@ -0,0 +1,50 @@ +############################################################################### +# File : bne.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'bne' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $t0, $0, 0xcafe + ori $t1, $0, 0xcafe + ori $v0, $0, 0 # The test result starts as a failure + bne $t0, $t1, $finish # No branch + nop + bne $t0, $v0, $target + nop + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + +$done: + jr $ra + nop + j $finish # Early-by-1 branch detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + bne $t0, $0, $finish # Late-by-1 branch detection (result not stored) + nop + j $finish + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/brk.asm b/o1vm/resources/programs/mips/src/brk.asm new file mode 100644 index 0000000000..cf4ace06f3 --- /dev/null +++ b/o1vm/resources/programs/mips/src/brk.asm @@ -0,0 +1,22 @@ +.section .text +.global __start + +__start: + li $v0, 4045 + syscall + lui $t0, 0x4000 + subu $v0, $v0, $t0 + sltiu $v0, $v0, 1 + +# save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/clo.asm b/o1vm/resources/programs/mips/src/clo.asm new file mode 100644 index 0000000000..374d3fa15e --- /dev/null +++ b/o1vm/resources/programs/mips/src/clo.asm @@ -0,0 +1,59 @@ +############################################################################### +# File : clo.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'clo' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t2, 0xffff # 32 + ori $t2, 0xffff + lui $t3, 0xffff # 18 + ori $t3, 0xc000 + lui $t4, 0xf800 # 5 + lui $t5, 0xf000 # 4 + lui $t6, 0x7fff # 0 + ori $t7, $0, 0 # 0 + clo $s2, $t2 + clo $s3, $t3 + clo $s4, $t4 + clo $s5, $t5 + clo $s6, $t6 + clo $s7, $t7 + addiu $s2, -32 + addiu $s3, -18 + addiu $s4, -5 + addiu $s5, -4 + addiu $s6, 0 + addiu $s7, 0 + or $v1, $s2, $s3 + or $v1, $v1, $s4 + or $v1, $v1, $s5 + or $v1, $v1, $s6 + or $v1, $v1, $s7 + sltiu $v0, $v1, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/clone.asm b/o1vm/resources/programs/mips/src/clone.asm new file mode 100644 index 0000000000..5bf53581d2 --- /dev/null +++ b/o1vm/resources/programs/mips/src/clone.asm @@ -0,0 +1,22 @@ +.section .text +.global __start + +__start: + li $v0, 4120 + syscall + li $t0, 0x1 + subu $v0, $v0, $t0 + sltiu $v0, $v0, 1 + +# save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/clz.asm b/o1vm/resources/programs/mips/src/clz.asm new file mode 100644 index 0000000000..dd33c0daa2 --- /dev/null +++ b/o1vm/resources/programs/mips/src/clz.asm @@ -0,0 +1,58 @@ +############################################################################### +# File : clz.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'clz' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t2, 0xffff # 0 + ori $t2, 0xffff + ori $t3, $0, 0x0100 # 23 + lui $t4, 0x0700 # 5 + lui $t5, 0x0f00 # 4 + lui $t6, 0x7fff # 1 + ori $t7, $0, 0 # 32 + clz $s2, $t2 + clz $s3, $t3 + clz $s4, $t4 + clz $s5, $t5 + clz $s6, $t6 + clz $s7, $t7 + addiu $s2, 0 + addiu $s3, -23 + addiu $s4, -5 + addiu $s5, -4 + addiu $s6, -1 + addiu $s7, -32 + or $v1, $s2, $s3 + or $v1, $v1, $s4 + or $v1, $v1, $s5 + or $v1, $v1, $s6 + or $v1, $v1, $s7 + sltiu $v0, $v1, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/div.asm b/o1vm/resources/programs/mips/src/div.asm new file mode 100644 index 0000000000..ae4f26ffeb --- /dev/null +++ b/o1vm/resources/programs/mips/src/div.asm @@ -0,0 +1,49 @@ +############################################################################### +# File : div.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'div' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0x1234 + ori $t0, 0x5678 + lui $t1, 0xc001 + ori $t1, 0xcafe + div $t1, $t0 # 0xfffffffd (q), 0xf69ece66 (r) + mfhi $t2 + mflo $t3 + lui $t4, 0xf69e + ori $t4, 0xce66 + lui $t5, 0xffff + ori $t5, 0xfffd + subu $t6, $t2, $t4 + subu $t7, $t3, $t5 + sltiu $v0, $t6, 1 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/divu.asm b/o1vm/resources/programs/mips/src/divu.asm new file mode 100644 index 0000000000..825fac128c --- /dev/null +++ b/o1vm/resources/programs/mips/src/divu.asm @@ -0,0 +1,49 @@ +############################################################################### +# File : divu.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'divu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0x1234 + ori $t0, 0x5678 + lui $t1, 0xc001 + ori $t1, 0xcafe + divu $t1, $t0 # 0xa (q), 0x09f66a4e (r) + mfhi $t2 + mflo $t3 + lui $t4, 0x09f6 + ori $t4, 0x6a4e + lui $t5, 0x0000 + ori $t5, 0x000a + subu $t6, $t2, $t4 + subu $t7, $t3, $t5 + sltiu $v0, $t6, 1 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/exit_group.asm b/o1vm/resources/programs/mips/src/exit_group.asm new file mode 100644 index 0000000000..058f08f494 --- /dev/null +++ b/o1vm/resources/programs/mips/src/exit_group.asm @@ -0,0 +1,25 @@ +.section .text +.global __start + +__start: + li $a0, 1 + li $v0, 4246 + syscall + + # Unreachable .... + # set test result to fail. + # Test runner should short-circuit before reaching this point. + li $v0, 0 + + # save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/fcntl.asm b/o1vm/resources/programs/mips/src/fcntl.asm new file mode 100644 index 0000000000..b199dae3ed --- /dev/null +++ b/o1vm/resources/programs/mips/src/fcntl.asm @@ -0,0 +1,23 @@ +.section .text +.global __start + +__start: + # fnctl(0, 3) + li $v0, 4055 + li $a0, 0x0 + li $a1, 0x3 + syscall + sltiu $v0, $v0, 1 + +# save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/j.asm b/o1vm/resources/programs/mips/src/j.asm new file mode 100644 index 0000000000..3932995c82 --- /dev/null +++ b/o1vm/resources/programs/mips/src/j.asm @@ -0,0 +1,41 @@ +############################################################################### +# File : j.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'j' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + j $target + ori $v0, $0, 0 # The test result starts as a failure + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + jr $ra + nop + j $finish # Early-by-1 detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + j $finish # Late-by 1 detection (result not written) + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/jal.asm b/o1vm/resources/programs/mips/src/jal.asm new file mode 100644 index 0000000000..cf8abb5c66 --- /dev/null +++ b/o1vm/resources/programs/mips/src/jal.asm @@ -0,0 +1,43 @@ +############################################################################### +# File : jal.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'jal' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $v1, $ra, 0 # Save $ra + jal $target + ori $v0, $0, 0 # The test result starts as a failure + +$finish: + sw $v0, 8($s0) + ori $ra, $v1, 0 # Restore $ra + sw $s1, 4($s0) + jr $ra + nop + j $finish # Early-by-1 detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + jr $ra + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/jalr.asm b/o1vm/resources/programs/mips/src/jalr.asm new file mode 100644 index 0000000000..1a8805435a --- /dev/null +++ b/o1vm/resources/programs/mips/src/jalr.asm @@ -0,0 +1,44 @@ +############################################################################### +# File : jalr.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'jalr' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $v1, $ra, 0 # Save $ra + la $t0, $target + jalr $t0 + ori $v0, $0, 0 # The test result starts as a failure + +$finish: + sw $v0, 8($s0) + ori $ra, $v1, 0 # Restore $ra + sw $s1, 4($s0) + jr $ra + nop + j $finish # Early-by-1 detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + jr $ra + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/jr.asm b/o1vm/resources/programs/mips/src/jr.asm new file mode 100644 index 0000000000..7fd6b34e9e --- /dev/null +++ b/o1vm/resources/programs/mips/src/jr.asm @@ -0,0 +1,42 @@ +############################################################################### +# File : jr.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'jr' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + la $t0, $target + jr $t0 + ori $v0, $0, 0 # The test result starts as a failure + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + jr $ra + nop + j $finish # Early-by-1 detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + j $finish + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/lb.asm b/o1vm/resources/programs/mips/src/lb.asm new file mode 100644 index 0000000000..8ae2bdb177 --- /dev/null +++ b/o1vm/resources/programs/mips/src/lb.asm @@ -0,0 +1,112 @@ +############################################################################### +# File : lb.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lb' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + lui $t1, 0xc001 + ori $t1, 0x7afe + sw $t1, 0($t0) + lb $t2, 0($t0) + lb $t3, 1($t0) + lb $t4, 2($t0) + lb $t5, 3($t0) + .ifdef big_endian + lui $t6, 0xffff + ori $t6, 0xffc0 + lui $t7, 0x0000 + ori $t7, 0x0001 + lui $t8, 0x0000 + ori $t8, 0x007a + lui $t9, 0xffff + ori $t9, 0xfffe + .else + lui $t6, 0xffff + ori $t6, 0xfffe + lui $t7, 0x0000 + ori $t7, 0x007a + lui $t8, 0x0000 + ori $t8, 0x0001 + lui $t9, 0xffff + ori $t9, 0xffc0 + .endif + subu $v1, $t2, $t6 + sltiu $v0, $v1, 1 + subu $v1, $t3, $t7 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t4, $t8 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t5, $t9 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + + # Repeat with halves swapped (sign extension corner cases) + lui $t1, 0x7afe + ori $t1, 0xc001 + sw $t1, 0($t0) + lb $t2, 0($t0) + lb $t3, 1($t0) + lb $t4, 2($t0) + lb $t5, 3($t0) + .ifdef big_endian + lui $t6, 0x0000 + ori $t6, 0x007a + lui $t7, 0xffff + ori $t7, 0xfffe + lui $t8, 0xffff + ori $t8, 0xffc0 + lui $t9, 0x0000 + ori $t9, 0x0001 + .else + lui $t6, 0x0000 + ori $t6, 0x0001 + lui $t7, 0xffff + ori $t7, 0xffc0 + lui $t8, 0xffff + ori $t8, 0xfffe + lui $t9, 0x0000 + ori $t9, 0x007a + .endif + subu $v1, $t2, $t6 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t3, $t7 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t4, $t8 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t5, $t9 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/lbu.asm b/o1vm/resources/programs/mips/src/lbu.asm new file mode 100644 index 0000000000..9473a3b2fb --- /dev/null +++ b/o1vm/resources/programs/mips/src/lbu.asm @@ -0,0 +1,64 @@ +############################################################################### +# File : lbu.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lbu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + lui $t1, 0xc001 + ori $t1, 0x7afe + sw $t1, 0($t0) + lbu $t2, 0($t0) + lbu $t3, 1($t0) + lbu $t4, 2($t0) + lbu $t5, 3($t0) + .ifdef big_endian + ori $t6, $0, 0x00c0 + ori $t7, $0, 0x0001 + ori $t8, $0, 0x007a + ori $t9, $0, 0x00fe + .else + ori $t6, $0, 0x00fe + ori $t7, $0, 0x007a + ori $t8, $0, 0x0001 + ori $t9, $0, 0x00c0 + .endif + subu $v1, $t2, $t6 + sltiu $v0, $v1, 1 + subu $v1, $t3, $t7 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t4, $t8 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t5, $t9 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/lh.asm b/o1vm/resources/programs/mips/src/lh.asm new file mode 100644 index 0000000000..bbf3d072c3 --- /dev/null +++ b/o1vm/resources/programs/mips/src/lh.asm @@ -0,0 +1,80 @@ +############################################################################### +# File : lh.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lh' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + lui $t1, 0x7001 + ori $t1, 0xcafe + sw $t1, 0($t0) + lh $t2, 0($t0) + lh $t3, 2($t0) + .ifdef big_endian + lui $t4, 0x0000 + ori $t4, 0x7001 + lui $t5, 0xffff + ori $t5, 0xcafe + .else + lui $t4, 0xffff + ori $t4, 0xcafe + lui $t5, 0x0000 + ori $t5, 0x7001 + .endif + subu $v1, $t2, $t4 + sltiu $v0, $v1, 1 + subu $v1, $t3, $t5 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + + # Repeat with halves swapped (sign extension corner cases) + lui $t1, 0xcafe + ori $t1, 0x7001 + sw $t1, 0($t0) + lh $t2, 0($t0) + lh $t3, 2($t0) + .ifdef big_endian + lui $t4, 0xffff + ori $t4, 0xcafe + lui $t5, 0x0000 + ori $t5, 0x7001 + .else + lui $t4, 0x0000 + ori $t4, 0x7001 + lui $t5, 0xffff + ori $t5, 0xcafe + .endif + subu $v1, $t2, $t4 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t3, $t5 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/lhu.asm b/o1vm/resources/programs/mips/src/lhu.asm new file mode 100644 index 0000000000..17399ce929 --- /dev/null +++ b/o1vm/resources/programs/mips/src/lhu.asm @@ -0,0 +1,72 @@ +############################################################################### +# File : lhu.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lhu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + lui $t1, 0x7001 + ori $t1, 0xcafe + sw $t1, 0($t0) + lhu $t2, 0($t0) + lhu $t3, 2($t0) + .ifdef big_endian + ori $t4, $0, 0x7001 + ori $t5, $0, 0xcafe + .else + ori $t4, $0, 0xcafe + ori $t5, $0, 0x7001 + .endif + subu $v1, $t2, $t4 + sltiu $v0, $v1, 1 + subu $v1, $t3, $t5 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + + # Repeat with halves swapped (sign extension corner cases) + lui $t1, 0xcafe + ori $t1, 0x7001 + sw $t1, 0($t0) + lhu $t2, 0($t0) + lhu $t3, 2($t0) + .ifdef big_endian + ori $t4, $0, 0xcafe + ori $t5, $0, 0x7001 + .else + ori $t4, $0, 0x7001 + ori $t5, $0, 0xcafe + .endif + subu $v1, $t2, $t4 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t3, $t5 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/lui.asm b/o1vm/resources/programs/mips/src/lui.asm new file mode 100644 index 0000000000..1b08d1b1c4 --- /dev/null +++ b/o1vm/resources/programs/mips/src/lui.asm @@ -0,0 +1,34 @@ +############################################################################### +# File : lui.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lui' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $v0, $0, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/lw.asm b/o1vm/resources/programs/mips/src/lw.asm new file mode 100644 index 0000000000..57eaa15dba --- /dev/null +++ b/o1vm/resources/programs/mips/src/lw.asm @@ -0,0 +1,39 @@ +############################################################################### +# File : lw.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lw' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load a valid address (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + sw $0, 0($t0) + ori $t1, $0, 1 + sw $t1, 0($t0) + lw $v0, 0($t0) + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/lwl.asm b/o1vm/resources/programs/mips/src/lwl.asm new file mode 100644 index 0000000000..8b0aa87f17 --- /dev/null +++ b/o1vm/resources/programs/mips/src/lwl.asm @@ -0,0 +1,78 @@ +############################################################################### +# File : lwl.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lwl' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + lui $t1, 0xc001 # Memory word is 0xc001cafe + ori $t1, 0xcafe + sw $t1, 0($t0) + lui $t2, 0xdeaf # Register word is 0xdeafbeef + ori $t2, 0xbeef + or $t3, $0, $t2 + or $t4, $0, $t2 + or $t5, $0, $t2 + or $t6, $0, $t2 + lwl $t3, 0($t0) + lwl $t4, 1($t0) + lwl $t5, 2($t0) + lwl $t6, 3($t0) + .ifdef big_endian + lui $s3, 0xc001 # 0xc001cafe + ori $s3, 0xcafe + lui $s4, 0x01ca # 0x01cafeef + ori $s4, 0xfeef + lui $s5, 0xcafe # 0xcafebeef + ori $s5, 0xbeef + lui $s6, 0xfeaf # 0xfeafbeef + ori $s6, 0xbeef + .else + lui $s3, 0xfeaf # 0xfeafbeef + ori $s3, 0xbeef + lui $s4, 0xcafe # 0xcafebeef + ori $s4, 0xbeef + lui $s5, 0x01ca # 0x01cafeef + ori $s5, 0xfeef + lui $s6, 0xc001 # 0xc001cafe + ori $s6, 0xcafe + .endif + subu $s2, $t3, $s3 + sltiu $v0, $s2, 1 + subu $s2, $t4, $s4 + sltiu $v1, $s2, 1 + and $v0, $v0, $v1 + subu $s2, $t5, $s5 + sltiu $v1, $s2, 1 + and $v0, $v0, $v1 + subu $s2, $t6, $s6 + sltiu $v1, $s2, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/lwr.asm b/o1vm/resources/programs/mips/src/lwr.asm new file mode 100644 index 0000000000..5561a18d5e --- /dev/null +++ b/o1vm/resources/programs/mips/src/lwr.asm @@ -0,0 +1,78 @@ +############################################################################### +# File : lwr.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lwr' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + lui $t1, 0xc001 # Memory word is 0xc001cafe + ori $t1, 0xcafe + sw $t1, 0($t0) + lui $t2, 0xdeaf # Register word is 0xdeafbeef + ori $t2, 0xbeef + or $t3, $0, $t2 + or $t4, $0, $t2 + or $t5, $0, $t2 + or $t6, $0, $t2 + lwr $t3, 0($t0) + lwr $t4, 1($t0) + lwr $t5, 2($t0) + lwr $t6, 3($t0) + .ifdef big_endian + lui $s3, 0xdeaf # 0xdeafbec0 + ori $s3, 0xbec0 + lui $s4, 0xdeaf # 0xdeafc001 + ori $s4, 0xc001 + lui $s5, 0xdec0 # 0xdec001ca + ori $s5, 0x01ca + lui $s6, 0xc001 # 0xc001cafe + ori $s6, 0xcafe + .else + lui $s3, 0xc001 # 0xc001cafe + ori $s3, 0xcafe + lui $s4, 0xdec0 # 0xdec001ca + ori $s4, 0x01ca + lui $s5, 0xdeaf # 0xdeafc001 + ori $s5, 0xc001 + lui $s6, 0xdeaf # 0xdeafbec0 + ori $s6, 0xbec0 + .endif + subu $s2, $t3, $s3 + sltiu $v0, $s2, 1 + subu $s2, $t4, $s4 + sltiu $v1, $s2, 1 + and $v0, $v0, $v1 + subu $s2, $t5, $s5 + sltiu $v1, $s2, 1 + and $v0, $v0, $v1 + subu $s2, $t6, $s6 + sltiu $v1, $s2, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/mfthi.asm b/o1vm/resources/programs/mips/src/mfthi.asm new file mode 100644 index 0000000000..ad7654b6ab --- /dev/null +++ b/o1vm/resources/programs/mips/src/mfthi.asm @@ -0,0 +1,39 @@ +############################################################################### +# File : mfthi.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'mthi' and 'mfhi' instructions. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf + ori $t0, 0xbeef + mthi $t0 + mfhi $t1 + subu $v1, $t0, $t1 + sltiu $v0, $v1, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/mftlo.asm b/o1vm/resources/programs/mips/src/mftlo.asm new file mode 100644 index 0000000000..e43da205ed --- /dev/null +++ b/o1vm/resources/programs/mips/src/mftlo.asm @@ -0,0 +1,39 @@ +############################################################################### +# File : mftlo.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'mtlo' and 'mflo' instructions. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf + ori $t0, 0xbeef + mtlo $t0 + mflo $t1 + subu $v1, $t0, $t1 + sltiu $v0, $v1, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/mmap.asm b/o1vm/resources/programs/mips/src/mmap.asm new file mode 100644 index 0000000000..8de6fad851 --- /dev/null +++ b/o1vm/resources/programs/mips/src/mmap.asm @@ -0,0 +1,24 @@ +.section .text +.global __start + +__start: + li $v0, 4090 + lui $a0, 0x3000 + li $a1, 4096 + syscall + lui $t0, 0x3000 + subu $v0, $v0, $t0 + sltiu $v0, $v0, 1 + + # save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/movn.asm b/o1vm/resources/programs/mips/src/movn.asm new file mode 100644 index 0000000000..53b9580817 --- /dev/null +++ b/o1vm/resources/programs/mips/src/movn.asm @@ -0,0 +1,42 @@ +############################################################################### +# File : movn.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'movn' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf + ori $t0, $t0, 0xbeef + ori $t1, $0, 0 + movn $t2, $t0, $s1 # $t2 gets 0xdeafbeef + movn $t1, $t0, $0 # $t1 remains 0 + subu $t3, $t2, $t0 + sltiu $v0, $t3, 1 + sltiu $v1, $t1, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/movz.asm b/o1vm/resources/programs/mips/src/movz.asm new file mode 100644 index 0000000000..74e78eacb5 --- /dev/null +++ b/o1vm/resources/programs/mips/src/movz.asm @@ -0,0 +1,42 @@ +############################################################################### +# File : movz.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'movz' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf + ori $t0, $t0, 0xbeef + ori $t2, $0, 0 + movz $t2, $t0, $s0 # $t2 remains 0 + movz $t1, $t0, $0 # $t1 gets 0xdeafbeef + subu $t3, $t1, $t0 + sltiu $v0, $t3, 1 + sltiu $v1, $t2, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/mul.asm b/o1vm/resources/programs/mips/src/mul.asm new file mode 100644 index 0000000000..2474b18357 --- /dev/null +++ b/o1vm/resources/programs/mips/src/mul.asm @@ -0,0 +1,42 @@ +############################################################################### +# File : mul.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'mul' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0x1234 + ori $t0, 0x5678 + lui $t1, 0xc001 + ori $t1, 0xcafe + mul $t2, $t0, $t1 # 0xb2a07b10 + lui $t3, 0xb2a0 + ori $t3, 0x7b10 + subu $t4, $t2, $t3 + sltiu $v0, $t4, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/mult.asm b/o1vm/resources/programs/mips/src/mult.asm new file mode 100644 index 0000000000..19650b33df --- /dev/null +++ b/o1vm/resources/programs/mips/src/mult.asm @@ -0,0 +1,49 @@ +############################################################################### +# File : mult.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'mult' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0x1234 + ori $t0, 0x5678 + lui $t1, 0xc001 + ori $t1, 0xcafe + mult $t0, $t1 # 0xfb730b05b2a07b10 + mfhi $t2 + mflo $t3 + lui $t4, 0xfb73 + ori $t4, 0x0b05 + lui $t5, 0xb2a0 + ori $t5, 0x7b10 + subu $t6, $t2, $t4 + subu $t7, $t3, $t5 + sltiu $v0, $t6, 1 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/multu.asm b/o1vm/resources/programs/mips/src/multu.asm new file mode 100644 index 0000000000..7ecc099961 --- /dev/null +++ b/o1vm/resources/programs/mips/src/multu.asm @@ -0,0 +1,49 @@ +############################################################################### +# File : multu.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'multu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0x1234 + ori $t0, 0x5678 + lui $t1, 0xc001 + ori $t1, 0xcafe + multu $t0, $t1 # 0x0da7617db2a07b10 + mfhi $t2 + mflo $t3 + lui $t4, 0x0da7 + ori $t4, 0x617d + lui $t5, 0xb2a0 + ori $t5, 0x7b10 + subu $t6, $t2, $t4 + subu $t7, $t3, $t5 + sltiu $v0, $t6, 1 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/nor.asm b/o1vm/resources/programs/mips/src/nor.asm new file mode 100644 index 0000000000..01b6799195 --- /dev/null +++ b/o1vm/resources/programs/mips/src/nor.asm @@ -0,0 +1,41 @@ +############################################################################### +# File : nor.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'nor' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, $t0, 0xbeef + lui $t1, 0x3141 # B = 0x31415926 + ori $t1, $t1, 0x5926 + lui $t2, 0xffff # C = 0xfffffffe + ori $t2, $t2, 0xfffe + nor $t3, $t0, $t1 # D = nor(A,B) = 0x00100010 + nor $v0, $t2, $t3 # E = nor(C,D) = 0x1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/oracle.asm b/o1vm/resources/programs/mips/src/oracle.asm new file mode 100644 index 0000000000..87759ab131 --- /dev/null +++ b/o1vm/resources/programs/mips/src/oracle.asm @@ -0,0 +1,102 @@ +.section .text +.global __start + +# load hash at 0x30001000 +# 0x47173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world") +# 0x02173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world").key +__start: + lui $s0, 0x3000 + ori $s0, 0x1000 + + lui $t0, 0x0217 + ori $t0, 0x3285 + sw $t0, 0($s0) + lui $t0, 0xa8d7 + ori $t0, 0x341e + sw $t0, 4($s0) + lui $t0, 0x5e97 + ori $t0, 0x2fc6 + sw $t0, 8($s0) + lui $t0, 0x7728 + ori $t0, 0x6384 + sw $t0, 0xc($s0) + lui $t0, 0xf802 + ori $t0, 0xf8ef + sw $t0, 0x10($s0) + lui $t0, 0x42a5 + ori $t0, 0xec5f + sw $t0, 0x14($s0) + lui $t0, 0x03bb + ori $t0, 0xfa25 + sw $t0, 0x18($s0) + lui $t0, 0x4cb0 + ori $t0, 0x1fad + sw $t0, 0x1c($s0) + +# preimage request - write(fdPreimageWrite, preimageData, 32) + li $a0, 6 + li $a1, 0x30001000 + li $t0, 8 + li $a2, 4 +$writeloop: + li $v0, 4004 + syscall + addiu $a1, $a1, 4 + addiu $t0, $t0, -1 + bnez $t0, $writeloop + nop + +# preimage response to 0x30002000 - read(fdPreimageRead, addr, count) +# read preimage length + li $a0, 5 + li $a1, 0x31000000 + li $a2, 4 + li $v0, 4003 + syscall + li $a1, 0x31000004 + li $v0, 4003 + syscall +# read the preimage data + li $a1, 0x31000008 + li $t0, 3 +$readloop: + li $v0, 4003 + syscall + addiu $a1, $a1, 4 + addiu $t0, $t0, -1 + bnez $t0, $readloop + nop + +# length at 0x31000000. We also check that the lower 32 bits are zero + lui $s1, 0x3100 + lw $t0, 0($s1) + sltiu $t6, $t0, 1 + li $s1, 0x31000004 + lw $t0, 0($s1) +# should be len("hello world") == 11 + li $t4, 11 + subu $t5, $t0, $t4 + sltiu $v0, $t5, 1 + and $v0, $v0, $t6 + +# data at 0x31000008 + lw $t0, 4($s1) + lui $t4, 0x6865 + ori $t4, 0x6c6c + subu $t5, $t0, $t4 + sltiu $v1, $t5, 1 + + and $v0, $v0, $v1 + +# save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/oracle_kzg.asm b/o1vm/resources/programs/mips/src/oracle_kzg.asm new file mode 100644 index 0000000000..544737e2da --- /dev/null +++ b/o1vm/resources/programs/mips/src/oracle_kzg.asm @@ -0,0 +1,98 @@ +.section .text +.global __start + +# load hash at 0x30001000 +# point evaluation precompile input - 01e798154708fe7789429634053cbf9f99b619f9f084048927333fce637f549b564c0a11a0f704f4fc3e8acfe0f8245f0ad1347b378fbf96e206da11a5d3630624d25032e67a7e6a4910df5834b8fe70e6bcfeeac0352434196bdf4b2485d5a18f59a8d2a1a625a17f3fea0fe5eb8c896db3764f3185481bc22f91b4aaffcca25f26936857bc3a7c2539ea8ec3a952b7873033e038326e87ed3e1276fd140253fa08e9fc25fb2d9a98527fc22a2c9612fbeafdad446cbc7bcdbdcd780af2c16a +# 0x0a44472c cb798bc5 954fc466 e6ee2c31 e1ca8a87 d000966c 629d679a 4a29921f = keccak(address(0xa) ++ precompile_input) +# 0x0644472c cb798bc5 954fc466 e6ee2c31 e1ca8a87 d000966c 629d679a 4a29921f = keccak(address(0xa) ++ precompile_input).key (precompile) +__start: + lui $s0, 0x3000 + ori $s0, 0x1000 + + lui $t0, 0x0644 + ori $t0, 0x472c + sw $t0, 0($s0) + lui $t0, 0xcb79 + ori $t0, 0x8bc5 + sw $t0, 4($s0) + lui $t0, 0x954f + ori $t0, 0xc466 + sw $t0, 8($s0) + lui $t0, 0xe6ee + ori $t0, 0x2c31 + sw $t0, 0xc($s0) + lui $t0, 0xe1ca + ori $t0, 0x8a87 + sw $t0, 0x10($s0) + lui $t0, 0xd000 + ori $t0, 0x966c + sw $t0, 0x14($s0) + lui $t0, 0x629d + ori $t0, 0x679a + sw $t0, 0x18($s0) + lui $t0, 0x4a29 + ori $t0, 0x921f + sw $t0, 0x1c($s0) + +# preimage request - write(fdPreimageWrite, preimageData, 32) + li $a0, 6 + li $a1, 0x30001000 + li $t0, 8 + li $a2, 4 +$writeloop: + li $v0, 4004 + syscall + addiu $a1, $a1, 4 + addiu $t0, $t0, -1 + bnez $t0, $writeloop + nop + +# preimage response to 0x30002000 - read(fdPreimageRead, addr, count) +# read preimage length + li $a0, 5 + li $a1, 0x31000000 + li $a2, 4 + li $v0, 4003 + syscall + li $a1, 0x31000004 + li $v0, 4003 + syscall +# read the 1 byte precompile status and 3 bytes of return data + li $a1, 0x31000008 + li $v0, 4003 + syscall + nop + +# length at 0x31000000. We also check that the lower 32 bits are zero + lui $s1, 0x3100 + lw $t0, 0($s1) + sltiu $t6, $t0, 1 + li $s1, 0x31000004 + lw $t0, 0($s1) +# should be 1 + len(blobPrecompileReturnValue) = 65 + li $t4, 65 + subu $t5, $t0, $t4 + sltiu $v0, $t5, 1 + and $v0, $v0, $t6 + +# data at 0x31000008 +# first byte is 01 status. Next 3 bytes are 0 + lw $t0, 4($s1) + lui $t4, 0x0100 + ori $t4, 0x0000 + subu $t5, $t0, $t4 + sltiu $v1, $t5, 1 + and $v0, $v0, $v1 + +# save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/oracle_unaligned_read.asm b/o1vm/resources/programs/mips/src/oracle_unaligned_read.asm new file mode 100644 index 0000000000..2ee7128ba4 --- /dev/null +++ b/o1vm/resources/programs/mips/src/oracle_unaligned_read.asm @@ -0,0 +1,133 @@ +.section .text +.global __start + +# load hash at 0x30001000 +# 0x47173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world") +# 0x02173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world").key +__start: + lui $s0, 0x3000 + ori $s0, 0x1000 + + lui $t0, 0x0217 + ori $t0, 0x3285 + sw $t0, 0($s0) + lui $t0, 0xa8d7 + ori $t0, 0x341e + sw $t0, 4($s0) + lui $t0, 0x5e97 + ori $t0, 0x2fc6 + sw $t0, 8($s0) + lui $t0, 0x7728 + ori $t0, 0x6384 + sw $t0, 0xc($s0) + lui $t0, 0xf802 + ori $t0, 0xf8ef + sw $t0, 0x10($s0) + lui $t0, 0x42a5 + ori $t0, 0xec5f + sw $t0, 0x14($s0) + lui $t0, 0x03bb + ori $t0, 0xfa25 + sw $t0, 0x18($s0) + lui $t0, 0x4cb0 + ori $t0, 0x1fad + sw $t0, 0x1c($s0) + +# preimage request - write(fdPreimageWrite, preimageData, 32) + li $a0, 6 + li $a1, 0x30001000 + li $t0, 8 + li $a2, 4 +$writeloop: + li $v0, 4004 + syscall + addiu $a1, $a1, 4 + addiu $t0, $t0, -1 + bnez $t0, $writeloop + nop + +# preimage response to 0x30002000 - read(fdPreimageRead, addr, count) +# read preimage length to unaligned addr. This will read only up to the nearest aligned byte so we have to read again. + li $a0, 5 + li $a1, 0x31000001 + li $a2, 4 + li $v0, 4003 + syscall + li $a1, 0x31000004 + li $v0, 4003 + syscall + li $a1, 0x31000008 + li $a2, 1 + li $v0, 4003 + syscall +# read the preimage data + li $a1, 0x31000009 + li $t0, 11 +$readloop: + li $v0, 4003 + li $a2, 4 + syscall + addu $a1, $a1, $v0 + subu $t0, $t0, $v0 + bnez $t0, $readloop + nop + +# length at 0x31000001. We also check that the lower 32 bits are zero + li $s1, 0x31000001 + lb $t0, 0($s1) + lb $t2, 1($s1) + sll $t2, $t2, 8 + or $t0, $t0, $t2 + lb $t2, 2($s1) + sll $t2, $t2, 16 + or $t0, $t0, $t2 +# assert len[0:3] == 0 + sltiu $v0, $t0, 1 + +# assert len[4:8] == 0 + addiu $s1, $s1, 3 + lw $t1, 0($s1) + sltiu $v1, $t1, 1 + and $v0, $v0, $v1 + +# assert len[8:9] == 11 + addiu $s1, $s1, 4 + lb $t2, 0($s1) + li $t4, 11 + subu $t5, $t2, $t4 + sltiu $v1, $t5, 1 + and $v0, $v0, $v1 + +# data at 0x31000009 + addiu $s1, $s1, 1 + lb $t0, 0($s1) + lb $t2, 1($s1) + sll $t0, $t0, 8 + or $t0, $t0, $t2 + lb $t2, 2($s1) + sll $t0, $t0, 8 + or $t0, $t0, $t2 + lb $t2, 3($s1) + sll $t0, $t0, 8 + or $t0, $t0, $t2 + + #lw $t0, 0($s1) + lui $t4, 0x6865 + ori $t4, 0x6c6c + subu $t5, $t0, $t4 + sltiu $v1, $t5, 1 + + and $v0, $v0, $v1 + +# save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/oracle_unaligned_write.asm b/o1vm/resources/programs/mips/src/oracle_unaligned_write.asm new file mode 100644 index 0000000000..ca242f3490 --- /dev/null +++ b/o1vm/resources/programs/mips/src/oracle_unaligned_write.asm @@ -0,0 +1,123 @@ +.section .text +.global __start + +# load hash at 0x30001000 +# 0x47173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world") +# 0x02173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world").key +__start: + lui $s0, 0x3000 + ori $s0, 0x1000 + + lui $t0, 0x0217 + ori $t0, 0x3285 + sw $t0, 0($s0) + lui $t0, 0xa8d7 + ori $t0, 0x341e + sw $t0, 4($s0) + lui $t0, 0x5e97 + ori $t0, 0x2fc6 + sw $t0, 8($s0) + lui $t0, 0x7728 + ori $t0, 0x6384 + sw $t0, 0xc($s0) + lui $t0, 0xf802 + ori $t0, 0xf8ef + sw $t0, 0x10($s0) + lui $t0, 0x42a5 + ori $t0, 0xec5f + sw $t0, 0x14($s0) + lui $t0, 0x03bb + ori $t0, 0xfa25 + sw $t0, 0x18($s0) + lui $t0, 0x4cb0 + ori $t0, 0x1fad + sw $t0, 0x1c($s0) + +# preimage request - write(fdPreimageWrite, preimageData, 32) +# create stuffed buffer containing the first byte of the hash - [garbage, hash[0], garbage] + lui $s1, 0x3200 + ori $s1, 0x0000 + lui $t0, 0xFFFF + ori $t0, 0x02FF + sw $t0, 0($s1) + +# initial unaligned write for stuffed buffer + li $a0, 6 + li $a1, 0x32000002 + li $a2, 1 + li $v0, 4004 + syscall + +# write 3 bytes for realignment + li $a0, 6 + li $a1, 0x30001001 + li $a2, 3 + li $v0, 4004 + syscall + + li $a0, 6 + li $a1, 0x30001004 + li $t0, 7 + li $a2, 4 +$writeloop: + li $v0, 4004 + syscall + addiu $a1, $a1, 4 + addiu $t0, $t0, -1 + bnez $t0, $writeloop + nop + +# preimage response to 0x30002000 - read(fdPreimageRead, addr, count) +# read preimage length + li $a0, 5 + li $a1, 0x31000000 + li $a2, 4 + li $v0, 4003 + syscall + li $a1, 0x31000004 + li $v0, 4003 + syscall +# read the preimage data + li $a1, 0x31000008 + li $t0, 3 +$readloop: + li $v0, 4003 + syscall + addiu $a1, $a1, 4 + addiu $t0, $t0, -1 + bnez $t0, $readloop + nop + +# length at 0x31000000. We also check that the lower 32 bits are zero + lui $s1, 0x3100 + lw $t0, 0($s1) + sltiu $t6, $t0, 1 + li $s1, 0x31000004 + lw $t0, 0($s1) +# should be len("hello world") == 11 + li $t4, 11 + subu $t5, $t0, $t4 + sltiu $v0, $t5, 1 + and $v0, $v0, $t6 + +# data at 0x31000008 + lw $t0, 4($s1) + lui $t4, 0x6865 + ori $t4, 0x6c6c + subu $t5, $t0, $t4 + sltiu $v1, $t5, 1 + + and $v0, $v0, $v1 + +# save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/ori.asm b/o1vm/resources/programs/mips/src/ori.asm new file mode 100644 index 0000000000..d985d60ed5 --- /dev/null +++ b/o1vm/resources/programs/mips/src/ori.asm @@ -0,0 +1,34 @@ +############################################################################### +# File : ori.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'ori' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $v0, $s1, 0 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sb.asm b/o1vm/resources/programs/mips/src/sb.asm new file mode 100644 index 0000000000..d05d344420 --- /dev/null +++ b/o1vm/resources/programs/mips/src/sb.asm @@ -0,0 +1,54 @@ +############################################################################### +# File : sb.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sb' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + sw $0, 0($t0) + ori $t1, $0, 0xc0 + ori $t2, $0, 0x01 + ori $t3, $0, 0xca + ori $t4, $0, 0xfe + sb $t1, 0($t0) + sb $t2, 1($t0) + sb $t3, 2($t0) + sb $t4, 3($t0) + lw $t5, 0($t0) + .ifdef big_endian + lui $t6, 0xc001 + ori $t6, 0xcafe + .else + lui $t6, 0xfeca + ori $t6, 0x01c0 + .endif + subu $t7, $t5, $t6 + sltiu $v0, $t7, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sh.asm b/o1vm/resources/programs/mips/src/sh.asm new file mode 100644 index 0000000000..c4a0e81494 --- /dev/null +++ b/o1vm/resources/programs/mips/src/sh.asm @@ -0,0 +1,50 @@ +############################################################################### +# File : sh.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sh' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + sw $0, 0($t0) + ori $t1, $0, 0xc001 + ori $t2, $0, 0xcafe + sh $t1, 0($t0) + sh $t2, 2($t0) + lw $t3, 0($t0) + .ifdef big_endian + lui $t4, 0xc001 + ori $t4, 0xcafe + .else + lui $t4, 0xcafe + ori $t4, 0xc001 + .endif + subu $t5, $t3, $t4 + sltiu $v0, $t5, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sll.asm b/o1vm/resources/programs/mips/src/sll.asm new file mode 100644 index 0000000000..8483593f96 --- /dev/null +++ b/o1vm/resources/programs/mips/src/sll.asm @@ -0,0 +1,40 @@ +############################################################################### +# File : sll.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sll' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, 0xbeef + sll $t1, $t0, 4 # B = 0xdeafbeef << 4 = 0xeafbeef0 + lui $t2, 0xeafb # C = 0xeafbeef0 + ori $t2, 0xeef0 + subu $t3, $t1, $t2 + sltiu $v0, $t3, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sllv.asm b/o1vm/resources/programs/mips/src/sllv.asm new file mode 100644 index 0000000000..c6af8848e8 --- /dev/null +++ b/o1vm/resources/programs/mips/src/sllv.asm @@ -0,0 +1,41 @@ +############################################################################### +# File : sllv.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sllv' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, 0xbeef + ori $t1, $0, 12 + sllv $t2, $t0, $t1 # B = 0xdeafbeef << 12 = 0xfbeef000 + lui $t3, 0xfbee + ori $t3, 0xf000 + subu $t4, $t2, $t3 + sltiu $v0, $t4, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/slt.asm b/o1vm/resources/programs/mips/src/slt.asm new file mode 100644 index 0000000000..d0a233a4a1 --- /dev/null +++ b/o1vm/resources/programs/mips/src/slt.asm @@ -0,0 +1,36 @@ +############################################################################### +# File : slt.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'slt' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff + ori $t0, 0xffff + slt $v0, $t0, $s1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/slti.asm b/o1vm/resources/programs/mips/src/slti.asm new file mode 100644 index 0000000000..6a40b9f5ad --- /dev/null +++ b/o1vm/resources/programs/mips/src/slti.asm @@ -0,0 +1,37 @@ +############################################################################### +# File : slti.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'slti' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0x8000 + slti $v0, $t0, 0xffff + slti $v1, $t0, 0 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sltiu.asm b/o1vm/resources/programs/mips/src/sltiu.asm new file mode 100644 index 0000000000..3789706ecd --- /dev/null +++ b/o1vm/resources/programs/mips/src/sltiu.asm @@ -0,0 +1,37 @@ +############################################################################### +# File : sltiu.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sltiu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0x8000 + sltiu $v0, $t0, 0xffff + sltiu $v1, $0, 0xffff + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sltu.asm b/o1vm/resources/programs/mips/src/sltu.asm new file mode 100644 index 0000000000..878be3ea84 --- /dev/null +++ b/o1vm/resources/programs/mips/src/sltu.asm @@ -0,0 +1,36 @@ +############################################################################### +# File : sltu.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sltu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff + ori $t0, 0xffff + sltu $v0, $s1, $t0 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sra.asm b/o1vm/resources/programs/mips/src/sra.asm new file mode 100644 index 0000000000..96961d50fa --- /dev/null +++ b/o1vm/resources/programs/mips/src/sra.asm @@ -0,0 +1,40 @@ +############################################################################### +# File : sra.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sra' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, 0xbeef + sra $t1, $t0, 4 # B = 0xdeafbeef >> 4 = 0xfdeafbee + lui $t2, 0xfdea # C = 0xfdeafbee + ori $t2, 0xfbee + subu $t3, $t1, $t2 # D = B - C = 0 + sltiu $v0, $t3, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/srav.asm b/o1vm/resources/programs/mips/src/srav.asm new file mode 100644 index 0000000000..163a4240c8 --- /dev/null +++ b/o1vm/resources/programs/mips/src/srav.asm @@ -0,0 +1,41 @@ +############################################################################### +# File : srav.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'srav' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, 0xbeef + ori $t1, $0, 12 + srav $t2, $t0, $t1 # B = 0xdeafbeef >> 12 = 0xfffdeafb + lui $t3, 0xfffd + ori $t3, 0xeafb + subu $t4, $t2, $t3 + sltiu $v0, $t4, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/srl.asm b/o1vm/resources/programs/mips/src/srl.asm new file mode 100644 index 0000000000..66f6027ea6 --- /dev/null +++ b/o1vm/resources/programs/mips/src/srl.asm @@ -0,0 +1,40 @@ +############################################################################### +# File : srl.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'srl' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, 0xbeef + srl $t1, $t0, 4 # B = 0xdeafbeef >> 4 = 0x0deafbee + lui $t2, 0x0dea + ori $t2, 0xfbee + subu $t3, $t1, $t2 # D = B - C = 0 + sltiu $v0, $t3, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/srlv.asm b/o1vm/resources/programs/mips/src/srlv.asm new file mode 100644 index 0000000000..96ee97fd75 --- /dev/null +++ b/o1vm/resources/programs/mips/src/srlv.asm @@ -0,0 +1,41 @@ +############################################################################### +# File : srlv.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'srlv' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, 0xbeef + ori $t1, $0, 12 + srlv $t2, $t0, $t1 # B = 0xdeafbeef >> 12 = 0x000deafb + lui $t3, 0x000d + ori $t3, 0xeafb + subu $t4, $t2, $t3 + sltiu $v0, $t4, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sub.asm b/o1vm/resources/programs/mips/src/sub.asm new file mode 100644 index 0000000000..26da5a19f5 --- /dev/null +++ b/o1vm/resources/programs/mips/src/sub.asm @@ -0,0 +1,40 @@ +############################################################################### +# File : sub.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sub' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff # A = 0xfffffffd (-3) + ori $t0, 0xfffd + sub $t1, $t0, $t0 # B = A - A = 0 + sub $t2, $t1, $t0 # C = B - A = 0 - A = 3 + ori $t3, $0, 3 # D = 2 + sub $t4, $t2, $t3 # E = C - D = C - 2 = 0 + sltiu $v0, $t4, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/subu.asm b/o1vm/resources/programs/mips/src/subu.asm new file mode 100644 index 0000000000..0d9ab23154 --- /dev/null +++ b/o1vm/resources/programs/mips/src/subu.asm @@ -0,0 +1,42 @@ +############################################################################### +# File : subu.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'subu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff # A = 0xfffffffd (-3) + ori $t0, 0xfffd + ori $t1, $0, 4 # B = 4 + subu $t2, $t0, $t1 # C = A - B = 0xfffffff9 (-7) + lui $t3, 0xffff # D = 0xfffffff8 (like -8 mod 2^32) + ori $t3, 0xfff8 + subu $t4, $t2, $t3 # F = C - D = 1 + subu $t5, $t4, $s1 # G = F - 1 = 0 + sltiu $v0, $t5, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/swl.asm b/o1vm/resources/programs/mips/src/swl.asm new file mode 100644 index 0000000000..354dadf567 --- /dev/null +++ b/o1vm/resources/programs/mips/src/swl.asm @@ -0,0 +1,81 @@ +############################################################################### +# File : swl.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'swl' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007ec (last four words in 2KB starting + ori $t0, 0x07ec # from 0xbfc00000) + lui $t1, 0xc001 # Memory word is 0xc001cafe + ori $t1, 0xcafe + sw $t1, 0($t0) + sw $t1, 4($t0) + sw $t1, 8($t0) + sw $t1, 12($t0) + lui $t2, 0xdeaf # Register word is 0xdeafbeef + ori $t2, 0xbeef + swl $t2, 0($t0) + swl $t2, 5($t0) + swl $t2, 10($t0) + swl $t2, 15($t0) + lw $s2, 0($t0) + lw $s3, 4($t0) + lw $s4, 8($t0) + lw $s5, 12($t0) + .ifdef big_endian + lui $t3, 0xdeaf # 0xdeafbeef + ori $t3, 0xbeef + lui $t4, 0xc0de # 0xc0deafbe + ori $t4, 0xafbe + lui $t5, 0xc001 # 0xc001deaf + ori $t5, 0xdeaf + lui $t6, 0xc001 # 0xc001cade + ori $t6, 0xcade + .else + lui $t3, 0xc001 # 0xc001cade + ori $t3, 0xcade + lui $t4, 0xc001 # 0xc001deaf + ori $t4, 0xdeaf + lui $t5, 0xc0de # 0xc0deafbe + ori $t5, 0xafbe + lui $t6, 0xdeaf # 0xdeafbeef + ori $t6, 0xbeef + .endif + subu $t7, $s2, $t3 + sltiu $v0, $t7, 1 + subu $t7, $s3, $t4 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + subu $t7, $s4, $t5 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + subu $t7, $s5, $t6 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/swr.asm b/o1vm/resources/programs/mips/src/swr.asm new file mode 100644 index 0000000000..2a4301cca7 --- /dev/null +++ b/o1vm/resources/programs/mips/src/swr.asm @@ -0,0 +1,81 @@ +############################################################################### +# File : swr.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'swr' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007ec (last four words in 2KB starting + ori $t0, 0x07ec # from 0xbfc00000) + lui $t1, 0xc001 # Memory words are 0xc001cafe + ori $t1, 0xcafe + sw $t1, 0($t0) + sw $t1, 4($t0) + sw $t1, 8($t0) + sw $t1, 12($t0) + lui $t2, 0xdeaf # Register word is 0xdeafbeef + ori $t2, 0xbeef + swr $t2, 0($t0) + swr $t2, 5($t0) + swr $t2, 10($t0) + swr $t2, 15($t0) + lw $s2, 0($t0) + lw $s3, 4($t0) + lw $s4, 8($t0) + lw $s5, 12($t0) + .ifdef big_endian + lui $t3, 0xef01 # 0xef01cafe + ori $t3, 0xcafe + lui $t4, 0xbeef # 0xbeefcafe + ori $t4, 0xcafe + lui $t5, 0xafbe # 0xafbeeffe + ori $t5, 0xeffe + lui $t6, 0xdeaf # 0xdeafbeef + ori $t6, 0xbeef + .else + lui $t3, 0xdeaf # 0xdeafbeef + ori $t3, 0xbeef + lui $t4, 0xafbe # 0xafbeeffe + ori $t4, 0xeffe + lui $t5, 0xbeef # 0xbeefcafe + ori $t5, 0xcafe + lui $t6, 0xef01 # 0xef01cafe + ori $t6, 0xcafe + .endif + subu $t7, $s2, $t3 + sltiu $v0, $t7, 1 + subu $t7, $s3, $t4 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + subu $t7, $s4, $t5 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + subu $t7, $s5, $t6 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/xor.asm b/o1vm/resources/programs/mips/src/xor.asm new file mode 100644 index 0000000000..56770a0e93 --- /dev/null +++ b/o1vm/resources/programs/mips/src/xor.asm @@ -0,0 +1,43 @@ +############################################################################### +# File : xor.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'xor' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, 0xbeef + lui $t1, 0x3141 # B = 0x31415926 + ori $t1, 0x5926 + lui $t2, 0xefee # C = 0xefeee7c8 + ori $t2, 0xe7c8 + xor $t3, $t0, $t1 # D = xor(A,B) = 0xefeee7c8 + xor $t4, $t2, $t3 # E = xor(C,D) = 0x1 + xor $t5, $t4, $s1 # F = xor(E,1) = 0 + sltiu $v0, $t5, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/xori.asm b/o1vm/resources/programs/mips/src/xori.asm new file mode 100644 index 0000000000..491e3ba11b --- /dev/null +++ b/o1vm/resources/programs/mips/src/xori.asm @@ -0,0 +1,38 @@ +############################################################################### +# File : xori.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'xori' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $t0, $0, 0xdeaf # A = 0xdeaf + xori $t1, $t0, 0x3141 # B = xor(A, 0x3141) = 0xefee + xori $t2, $t1, 0xefef # C = xor(B, 0xefef) = 0x1 + xori $t3, $t2, 1 # D = xor(C, 1) = 0 + sltiu $v0, $t3, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop +