diff --git a/o1vm/src/interpreters/riscv32im/tests.rs b/o1vm/src/interpreters/riscv32im/tests.rs
index 37f5d396d3..09253c0122 100644
--- a/o1vm/src/interpreters/riscv32im/tests.rs
+++ b/o1vm/src/interpreters/riscv32im/tests.rs
@@ -146,6 +146,29 @@ pub fn generate_random_slt_instruction<RNG: RngCore + CryptoRng>(rng: &mut RNG)
     ]
 }
 
+pub fn generate_random_xor_instruction<RNG: RngCore + CryptoRng>(rng: &mut RNG) -> [u8; 4] {
+    let opcode = 0b0110011;
+    let rd = rng.gen_range(0..32);
+    let funct3 = 0b100;
+    let rs1 = rng.gen_range(0..32);
+    let rs2 = rng.gen_range(0..32);
+    let funct2 = 0b00;
+    let funct5 = 0b00000;
+    let instruction = opcode
+        | (rd << 7)
+        | (funct3 << 12)
+        | (rs1 << 15)
+        | (rs2 << 20)
+        | (funct2 << 25)
+        | (funct5 << 27);
+    [
+        instruction as u8,
+        (instruction >> 8) as u8,
+        (instruction >> 16) as u8,
+        (instruction >> 24) as u8,
+    ]
+}
+
 pub fn generate_random_sltu_instruction<RNG: RngCore + CryptoRng>(rng: &mut RNG) -> [u8; 4] {
     let opcode = 0b0110011;
     let rd = rng.gen_range(0..32);
@@ -236,3 +259,16 @@ pub fn test_instruction_decoding_sltu() {
         Instruction::RType(RInstruction::SetLessThanUnsigned)
     );
 }
+
+#[test]
+pub fn test_instruction_decoding_xor() {
+    let mut env: Env<Fp> = dummy_env();
+    let mut rng = o1_utils::tests::make_test_rng(None);
+    let instruction = generate_random_xor_instruction(&mut rng);
+    env.memory[0].1[0] = instruction[0];
+    env.memory[0].1[1] = instruction[1];
+    env.memory[0].1[2] = instruction[2];
+    env.memory[0].1[3] = instruction[3];
+    let (opcode, _instruction) = env.decode_instruction();
+    assert_eq!(opcode, Instruction::RType(RInstruction::Xor));
+}