From 7367e4b86bfdd08903ffd5ec4e27bb7be7731eff Mon Sep 17 00:00:00 2001
From: Danny Willems <be.danny.willems@gmail.com>
Date: Wed, 20 Nov 2024 16:43:33 +0100
Subject: [PATCH] o1vm/riscv32: implement M type instruction div

---
 o1vm/src/interpreters/riscv32im/interpreter.rs | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs
index 036107a200..438abaa065 100644
--- a/o1vm/src/interpreters/riscv32im/interpreter.rs
+++ b/o1vm/src/interpreters/riscv32im/interpreter.rs
@@ -2250,7 +2250,17 @@ pub fn interpret_mtype<Env: InterpreterEnv>(env: &mut Env, instr: MInstruction)
             env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32));
         }
         MInstruction::Div => {
-            unimplemented!("Div")
+            let rs1 = env.read_register(&rs1);
+            let rs2 = env.read_register(&rs2);
+            // FIXME: constrain
+            let res = {
+                let pos = env.alloc_scratch();
+                unsafe { env.div_signed(&rs1, &rs2, pos) }
+            };
+            env.write_register(&rd, res);
+
+            env.set_instruction_pointer(next_instruction_pointer.clone());
+            env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32));
         }
         MInstruction::Divu => {
             unimplemented!("Divu")