From 5a6e53b6e6e3675350b1402a6f4c5df0febbc548 Mon Sep 17 00:00:00 2001
From: Danny Willems <be.danny.willems@gmail.com>
Date: Mon, 23 Dec 2024 16:08:39 +0100
Subject: [PATCH] o1vm/riscv32im: add tests for XOR

---
 o1vm/resources/programs/riscv32im/bin/xor   | Bin 0 -> 480 bytes
 o1vm/resources/programs/riscv32im/src/xor.S |  30 ++++++++++++++++++++
 o1vm/tests/test_riscv_elf.rs                |  18 ++++++++++++
 3 files changed, 48 insertions(+)
 create mode 100755 o1vm/resources/programs/riscv32im/bin/xor
 create mode 100644 o1vm/resources/programs/riscv32im/src/xor.S

diff --git a/o1vm/resources/programs/riscv32im/bin/xor b/o1vm/resources/programs/riscv32im/bin/xor
new file mode 100755
index 0000000000000000000000000000000000000000..2a9f659899027a72af0500893945a842b8b65dc4
GIT binary patch
literal 480
zcma)2J5Iwu6r6PkL_!LnEoqQws4QaV08oG^kZ7o}*2WQ*Vz72M5lX`$d;#BqmI5jF
z;0%$t0P}1dTAnp;<~`5)GjCV7*Geh$72q2(dG;y!g2N7ZiW3AlqaN@=_0b<7C%;;J
za#qk)H;Gp;l;t5%2cOV`2Jh<>dfcEM1M%ILst-22w?Vv4plPlNy-Oza9+}W1@~8<M
zA9eY_W($`sq3$V%b{R)SR85jHs?HN5Y8F*d@+fUpWX{TdRm}3|ET@sWEEn^M2xH2Z
zPRy;#sDRKtId8p55&HbqBW&Ll8t-k9E_^QE@ZZ{}QPSYAwAp&{4bhimCv`+fzU{y!
Vx%K(VuFqDOzHJ?Iak`!Ud_R73L#hA(

literal 0
HcmV?d00001

diff --git a/o1vm/resources/programs/riscv32im/src/xor.S b/o1vm/resources/programs/riscv32im/src/xor.S
new file mode 100644
index 0000000000..ea78a68cca
--- /dev/null
+++ b/o1vm/resources/programs/riscv32im/src/xor.S
@@ -0,0 +1,30 @@
+.section .text
+.globl _start
+
+_start:
+
+    # Simple XOR
+    li t0, 0b1100         # t0 = 0b1100
+    li t1, 0b1010         # t1 = 0b1010
+    xor t2, t0, t1        # t2 = t0 ^ t1 (Expected: t2 = 0b0110)
+
+    # XOR with zero (no change)
+    li t3, 0b1010         # t3 = 0b1010
+    li t4, 0              # t4 = 0
+    xor t5, t3, t4        # t5 = t3 ^ t4 (Expected: t5 = 0b1010)
+
+    # XOR of identical values (result 0)
+    li t6, 0b1111         # t6 = 0b1111
+    li t0, 0b1111         # t0 = 0b1111
+    xor t1, t6, t0        # t1 = t6 ^ t0 (Expected: t1 = 0)
+
+    # Custom exit syscall
+    li a0, 0
+    li a1, 0
+    li a2, 0
+    li a3, 0
+    li a4, 0
+    li a5, 0
+    li a6, 0
+    li a7, 42
+    ecall
diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs
index 2c896e5d39..80f00f9169 100644
--- a/o1vm/tests/test_riscv_elf.rs
+++ b/o1vm/tests/test_riscv_elf.rs
@@ -300,3 +300,21 @@ fn test_sub_3() {
     assert_eq!(witness.registers[T1], 0);
     assert_eq!(witness.registers[T4], -2147483648_i32 as u32);
 }
+
+#[test]
+fn test_xor() {
+    let curr_dir = std::env::current_dir().unwrap();
+    let path = curr_dir.join(std::path::PathBuf::from(
+        "resources/programs/riscv32im/bin/xor",
+    ));
+    let state = o1vm::elf_loader::parse_riscv32(&path).unwrap();
+    let mut witness = Env::<Fp>::create(PAGE_SIZE.try_into().unwrap(), state);
+
+    while !witness.halt {
+        witness.step();
+    }
+
+    assert_eq!(witness.registers[T2], 0b0110); // Result: t2 = 0b0110
+    assert_eq!(witness.registers[T5], 0b1010); // Result: t5 = 0b1010
+    assert_eq!(witness.registers[T1], 0); // Result: t1 = 0
+}