From cb4276e8b23c761389e70221e5cf0bf5ae3ccb91 Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Tue, 26 Jul 2022 01:19:28 +0200
Subject: [PATCH] Prepare for release

---
 NEWS         | 13 +++++++++++++
 README.md    | 10 +++++-----
 serv.core    |  2 +-
 servant.core |  2 +-
 serving.core |  2 +-
 5 files changed, 21 insertions(+), 8 deletions(-)
 create mode 100644 NEWS

diff --git a/NEWS b/NEWS
new file mode 100644
index 00000000..bd8efa1b
--- /dev/null
+++ b/NEWS
@@ -0,0 +1,13 @@
+1.2.0 2022-07-25 Olof Kindgren
+======================================================
+
+* New Servant ports: EBAZ4205, Chameleion96, Nexys2, Alinx AX309
+* Support for M ISA extension
+* Support for C ISA extension
+* Fix occasionally wrong sign on immediates
+* Support for producing GDS with OpenLANE
+* Fix Model/QuestaSim compatibility
+* Add ViDBo support
+* Improved documentation
+* Less resource usage
+* Updated RISC-V Compliance support from 1.0 to 2.7.4
diff --git a/README.md b/README.md
index 621a3ec5..4ef036fb 100644
--- a/README.md
+++ b/README.md
@@ -43,7 +43,7 @@ If [Verilator](https://www.veripool.org/wiki/verilator) is installed, we can use
 
 If everything worked, the output should look like
 
-    INFO: Preparing ::serv:1.1.0
+    INFO: Preparing ::serv:1.2.0
     INFO: Setting up project
 
     INFO: Building simulation model
@@ -96,7 +96,7 @@ To run the RISC-V compliance tests, we need to supply the SERV-specific support
 
 Run the compliance tests
 
-    cd riscv-arch-test && make TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=I TARGET_SIM=$WORKSPACE/build/servant_1.1.0/verilator_tb-verilator/Vservant_sim
+    cd riscv-arch-test && make TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=I TARGET_SIM=$WORKSPACE/build/servant_1.2.0/verilator_tb-verilator/Vservant_sim
 
 The above will run all tests in the rv32i test suite. Since SERV also implement the `M`, `C`, `privilege` and `Zifencei` extensions, these can also be tested by choosing any of them instead of `I` as the `RISCV_DEVICE` variable.
 
@@ -150,7 +150,7 @@ serial console will show up.
 Pin D1 is used for UART output with 115200 baud rate.
 
     fusesoc run --target=orangecrab_r0.2 servant
-    dfu-util -d 1209:5af0 -D build/servant_1.1.0/orangecrab_r0.2-trellis/servant_1.1.0.bit
+    dfu-util -d 1209:5af0 -D build/servant_1.2.0/orangecrab_r0.2-trellis/servant_1.2.0.bit
 
 ### Arty A7 35T
 
@@ -219,14 +219,14 @@ Pin 61 is used for UART output with 115200 baud rate. This pin is connected to a
 Pin 95 is used as the GPIO output which is connected to the board's green LED. Due to this board's limited Embedded BRAM, programs with a maximum of 7168 bytes can be loaded. The default program for this board is blinky.hex.
 
     fusesoc run --target=icestick servant
-    iceprog build/servant_1.1.0/icestick-icestorm/servant_1.1.0.bin
+    iceprog build/servant_1.2.0/icestick-icestorm/servant_1.2.0.bin
 
 ### Nandland Go Board
 
 Pin 56 is used as the GPIO output which is connected to the board's LED1. Due to this board's limited Embedded BRAM, programs with a maximum of 7168 bytes can be loaded. The default program for this board is blinky.hex.
 
     fusesoc run --target=go_board servant
-    iceprog build/servant_1.1.0/go_board-icestorm/servant_1.1.0.bin
+    iceprog build/servant_1.2.0/go_board-icestorm/servant_1.2.0.bin
 
 ### Alinx ax309 (Spartan6 LX9)
 
diff --git a/serv.core b/serv.core
index 08e119a3..11bacedd 100644
--- a/serv.core
+++ b/serv.core
@@ -1,6 +1,6 @@
 CAPI=2:
 
-name : ::serv:1.1.0
+name : ::serv:1.2.0
 
 filesets:
   core:
diff --git a/servant.core b/servant.core
index ea913760..cfc74d25 100644
--- a/servant.core
+++ b/servant.core
@@ -1,6 +1,6 @@
 CAPI=2:
 
-name : ::servant:1.1.0
+name : ::servant:1.2.0
 
 filesets:
   service:
diff --git a/serving.core b/serving.core
index ac2b055b..6bcc7896 100644
--- a/serving.core
+++ b/serving.core
@@ -1,6 +1,6 @@
 CAPI=2:
 
-name : ::serving:1.1.0
+name : ::serving:1.2.0
 
 filesets:
   rtl: