Could we change the serv_compdec design scheme?

[stonechs]

serv_compdec.v occupy too many resourc. Statsisation report that it take about 709 gate, can we not to tranfer it to normal instr, but decode the compact instr directly. the serv_decode only about 100 gate. the following is the statsation from yosys.
=== serv_compdec ===

Number of wires: 681
Number of wire bits: 743
Number of public wires: 5
Number of public wire bits: 67
Number of ports: 5
Number of port bits: 67
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 709
$ANDNOT 57
$AND 15
$DFFE_PP 1
$MUX 140
$NAND 23
$NOR 267
$NOT 31
$ORNOT 149
$OR 26

=== $paramod\serv_decode\PRE_REGISTER=s32'00000000000000000000000000000001\MDU=1'0 ===

Number of wires: 151
Number of wire bits: 212
Number of public wires: 101
Number of public wire bits: 162
Number of ports: 48
Number of port bits: 90
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 100
$ANDNOT 5
$AND 7
$DFFE_PP 13
$MUX 1
$NAND 5
$NOR 27
$NOT 9
$ORNOT 24
$OR 9

[olofk]

That might be doable, but would require some work. I think the first thing we should do is just optimize it. The version we have now is basically an unmodified version copied from Ibex. I'm pretty sure we could make it a lot smaller by being less strict, like the main decoder.

[stonechs]

I tried modifying the code according to this schemes, but found that resource consumption actually increased. After reviewing the synthesize report, I discovered that the main reason is that the resource consumption is not in decoding itself, but in assembling the immediate value from different position. The date MUX consumption is huge . It seems this approach won't work. :=(